Pass 0 skeleton. The project builds and verifies byte-identical to the original ROM, but no disassembly exists yet: prg.s is a single .incbin "prg.bin" of the PRG image.

make assembles header.s, prg.s, chr.s, links them with ld65 and compares the result against rom.nes:

Byte-identical ROM verified.

ROM

Property	Value
Format	iNES
Mapper	65
Board	MAPPER65
Mirroring	Horizontal
Four-screen VRAM	no
Battery	yes
PRG	128 KB (8 x 16 KB), at file offset $0010
CHR	128 KB (16 x 8 KB)
Trainer	none
Footer	none
NMI vector	$C080
RESET vector	$FFE8
IRQ vector	$FFE8
ROM file	`Willow (U).nes`
SHA-256	`ca440c7f643a2c8388b1236e867ee62b6c3603fa3136a302b109f108b9a4b54a`

Header notes

header byte 7 is $44; its upper nybble selects mapper bits 4-7

Open work

Pass 1 - run nesdis.py over prg.bin to produce the code/data split. The tracer reads the vectors from the last six bytes of the PRG image, so the split seeds correctly.
Pass 1 must emit the canonical audit comment ; CPU:$C123 PRG:0123 AD 21 03 at column 35 for every instruction.
Pass 2 - replace the address-derived Label_XXXX names and the raw $XXXX call operands.
Pass 3 - semantic zero-page aliases (applied only at the sites where their role is proven) and named data tables.
Promotion to NROM/<name>/ once Pass 3 is done, as git mv.

Files

File	Purpose
`prg.s`	Pass 0 PRG include (replaced by the Pass 1 disassembly)
`header.s`	iNES header include
`chr.s`	CHR include
`prg.bin`	131072 bytes (128 KB) PRG image
`chr.bin`	131072 bytes (128 KB) CHR image
`rom.nes`	byte-identical copy of the original ROM
`linker.cfg`	HEADER / PRG / CHR memory areas
`symbols.inc`	NES hardware register names
`locals.inc`	zero-page aliases (empty at Pass 0)
`Makefile`	build and byte-identity check