tmerritt
2ddaf102a0
Standardized all 18 top-level projects to canonical audit comment format: ; CPU:$XXXX PRG:XXXX AA BB Changes per project: - CIRCUS: fixed 4,427 comments (CPU:XXXX -> CPU:$XXXX) - Excitebike (JU): fixed 48 double-semicolon comments (; state $XX ; CPU:...) - 9 projects received canonical comments via new audit_comment_tool.py: Balloon Fight, Baseball, Bomberman, Burger Time, Clu Clu Land, Defender 2, Donkey Kong 3, Donkey Kong Jr., Tennis New tool: _tools/audit_comment_tool.py - Uses nesdis.py tracer as ground truth for instruction bytes/addresses - Parses source while tracking PRG offset, emits canonical comments - Handles .byte/.word/.dword directives, instruction comments (short format) - Carves PRG from rom.nes when prg.bin missing Documentation updates: - TODO.md: Updated current state, item 3 (tool built), repo conventions, tool list - AGENTS.md: Added audit_comment_tool.py to _tools/, updated audit convention Verification: verify_pass1.py reports all 18 projects byte-identical with 'canoni' format.
7554 lines
478 KiB
ArmAsm
7554 lines
478 KiB
ArmAsm
; Bomberman NES - Phase 3 semantic refinement
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; Based on the user-validated Phase 2 recursive trace from NMI, RESET, and IRQ/BRK.
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; Reachable official 6502 opcodes are emitted as instructions.
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; Unreachable bytes are classified as explicit data regions.
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.setcpu "6502"
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.include "symbols.inc"
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.include "locals.inc"
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.segment "PRG"
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.org $C000
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; Routine: Reset
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; Global: Reachable code entry at CPU $C000 traced from the interrupt-root control-flow graph.
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; Local: Performs the instruction sequence below; semantic purpose remains provisional.
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; Parameters: Register and memory inputs are caller-dependent.
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; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
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; Side effects: Registers, flags, memory, and hardware registers written below.
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; Confidence: High for reachability and encoding; semantic role provisional.
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Reset:
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sei ; CPU:$C000 PRG:0000 78
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lda #$00 ; CPU:$C001 PRG:0001 A9 00
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sta PPUMASK ; CPU:$C003 PRG:0003 8D 01 20
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sta PPUCTRL ; CPU:$C006 PRG:0006 8D 00 20
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cld ; CPU:$C009 PRG:0009 D8
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ldx #$FF ; CPU:$C00A PRG:000A A2 FF
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txs ; CPU:$C00C PRG:000C 9A
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; Routine: WaitForFirstStartupVBlank
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; Global: Reachable code entry at CPU $C00D traced from the interrupt-root control-flow graph.
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; Local: Performs the instruction sequence below; semantic purpose remains provisional.
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; Parameters: Register and memory inputs are caller-dependent.
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; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
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; Side effects: Registers, flags, memory, and hardware registers written below.
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; Confidence: High for reachability and encoding; semantic role provisional.
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WaitForFirstStartupVBlank:
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lda PPUSTATUS ; CPU:$C00D PRG:000D AD 02 20
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bpl WaitForFirstStartupVBlank ; CPU:$C010 PRG:0010 10 FB
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; Routine: WaitForSecondStartupVBlank
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; Global: Reachable code entry at CPU $C012 traced from the interrupt-root control-flow graph.
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; Local: Performs the instruction sequence below; semantic purpose remains provisional.
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; Parameters: Register and memory inputs are caller-dependent.
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; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
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; Side effects: Registers, flags, memory, and hardware registers written below.
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; Confidence: High for reachability and encoding; semantic role provisional.
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WaitForSecondStartupVBlank:
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lda PPUSTATUS ; CPU:$C012 PRG:0012 AD 02 20
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bpl WaitForSecondStartupVBlank ; CPU:$C015 PRG:0015 10 FB
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jmp InitializeSystemAndRunMainLoop ; CPU:$C017 PRG:0017 4C 0C C3
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; Routine: NmiHandler
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; Global: Reachable code entry at CPU $C01A traced from the interrupt-root control-flow graph.
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; Local: Performs the instruction sequence below; semantic purpose remains provisional.
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; Parameters: Register and memory inputs are caller-dependent.
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; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
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; Side effects: Registers, flags, memory, and hardware registers written below.
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; Confidence: High for reachability and encoding; semantic role provisional.
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NmiHandler:
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pha ; CPU:$C01A PRG:001A 48
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txa ; CPU:$C01B PRG:001B 8A
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pha ; CPU:$C01C PRG:001C 48
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tya ; CPU:$C01D PRG:001D 98
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pha ; CPU:$C01E PRG:001E 48
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ldx #$00 ; CPU:$C01F PRG:001F A2 00
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stx FrameSyncFlag ; CPU:$C021 PRG:0021 86 0B
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stx OAMADDR ; CPU:$C023 PRG:0023 8E 03 20
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lda $60 ; CPU:$C026 PRG:0026 A5 60
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beq Nmi_TransferSpriteDmaPath_C03E ; CPU:$C028 PRG:0028 F0 14
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lda #$19 ; CPU:$C02A PRG:002A A9 19
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sta $0700 ; CPU:$C02C PRG:002C 8D 00 07
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lda #$EC ; CPU:$C02F PRG:002F A9 EC
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sta $0701 ; CPU:$C031 PRG:0031 8D 01 07
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lda #$00 ; CPU:$C034 PRG:0034 A9 00
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sta $0702 ; CPU:$C036 PRG:0036 8D 02 07
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lda #$F8 ; CPU:$C039 PRG:0039 A9 F8
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sta $0703 ; CPU:$C03B PRG:003B 8D 03 07
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; Routine: Nmi_TransferSpriteDmaPath_C03E
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; Global: Reachable code entry at CPU $C03E traced from the interrupt-root control-flow graph.
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; Local: Performs the instruction sequence below; semantic purpose remains provisional.
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; Parameters: Register and memory inputs are caller-dependent.
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; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
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; Side effects: Registers, flags, memory, and hardware registers written below.
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; Confidence: High for reachability and encoding; semantic role provisional.
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Nmi_TransferSpriteDmaPath_C03E:
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lda #$07 ; CPU:$C03E PRG:003E A9 07
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sta OAMDMA ; CPU:$C040 PRG:0040 8D 14 40
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ldx #$09 ; CPU:$C043 PRG:0043 A2 09
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stx $16 ; CPU:$C045 PRG:0045 86 16
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bne Nmi_ReadZp14_C0B3 ; CPU:$C047 PRG:0047 D0 6A
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; Routine: Nmi_TransferVramDataPath_C049
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; Global: Reachable code entry at CPU $C049 traced from the interrupt-root control-flow graph.
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; Local: Performs the instruction sequence below; semantic purpose remains provisional.
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; Parameters: Register and memory inputs are caller-dependent.
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; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
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; Side effects: Registers, flags, memory, and hardware registers written below.
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; Confidence: High for reachability and encoding; semantic role provisional.
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Nmi_TransferVramDataPath_C049:
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lda $0602,y ; CPU:$C049 PRG:0049 B9 02 06
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ora $0600,y ; CPU:$C04C PRG:004C 19 00 06
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pha ; CPU:$C04F PRG:004F 48
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sta PPUADDR ; CPU:$C050 PRG:0050 8D 06 20
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ldx $0601,y ; CPU:$C053 PRG:0053 BE 01 06
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stx PPUADDR ; CPU:$C056 PRG:0056 8E 06 20
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ldx $0603,y ; CPU:$C059 PRG:0059 BE 03 06
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lda $D9C6,x ; CPU:$C05C PRG:005C BD C6 D9
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sta PPUDATA ; CPU:$C05F PRG:005F 8D 07 20
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lda $D9C7,x ; CPU:$C062 PRG:0062 BD C7 D9
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sta PPUDATA ; CPU:$C065 PRG:0065 8D 07 20
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pla ; CPU:$C068 PRG:0068 68
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sta PPUADDR ; CPU:$C069 PRG:0069 8D 06 20
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lda $0601,y ; CPU:$C06C PRG:006C B9 01 06
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clc ; CPU:$C06F PRG:006F 18
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adc #$20 ; CPU:$C070 PRG:0070 69 20
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sta PPUADDR ; CPU:$C072 PRG:0072 8D 06 20
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lda $D9C8,x ; CPU:$C075 PRG:0075 BD C8 D9
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sta PPUDATA ; CPU:$C078 PRG:0078 8D 07 20
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lda $D9C9,x ; CPU:$C07B PRG:007B BD C9 D9
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sta PPUDATA ; CPU:$C07E PRG:007E 8D 07 20
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lda #$23 ; CPU:$C081 PRG:0081 A9 23
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ora $0600,y ; CPU:$C083 PRG:0083 19 00 06
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pha ; CPU:$C086 PRG:0086 48
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sta PPUADDR ; CPU:$C087 PRG:0087 8D 06 20
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lda $0604,y ; CPU:$C08A PRG:008A B9 04 06
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sta PPUADDR ; CPU:$C08D PRG:008D 8D 06 20
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tax ; CPU:$C090 PRG:0090 AA
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lda PPUDATA ; CPU:$C091 PRG:0091 AD 07 20
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lda PPUDATA ; CPU:$C094 PRG:0094 AD 07 20
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and $0606,y ; CPU:$C097 PRG:0097 39 06 06
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ora $0607,y ; CPU:$C09A PRG:009A 19 07 06
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tay ; CPU:$C09D PRG:009D A8
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pla ; CPU:$C09E PRG:009E 68
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sta PPUADDR ; CPU:$C09F PRG:009F 8D 06 20
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stx PPUADDR ; CPU:$C0A2 PRG:00A2 8E 06 20
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sty PPUDATA ; CPU:$C0A5 PRG:00A5 8C 07 20
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lda #$08 ; CPU:$C0A8 PRG:00A8 A9 08
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clc ; CPU:$C0AA PRG:00AA 18
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adc $14 ; CPU:$C0AB PRG:00AB 65 14
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sta $14 ; CPU:$C0AD PRG:00AD 85 14
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dec $16 ; CPU:$C0AF PRG:00AF C6 16
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beq Nmi_ReadScreenState_C0B9 ; CPU:$C0B1 PRG:00B1 F0 06
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; Routine: Nmi_ReadZp14_C0B3
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; Global: Reachable code entry at CPU $C0B3 traced from the interrupt-root control-flow graph.
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; Local: Performs the instruction sequence below; semantic purpose remains provisional.
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; Parameters: Register and memory inputs are caller-dependent.
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; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
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; Side effects: Registers, flags, memory, and hardware registers written below.
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; Confidence: High for reachability and encoding; semantic role provisional.
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Nmi_ReadZp14_C0B3:
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ldy $14 ; CPU:$C0B3 PRG:00B3 A4 14
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cpy $15 ; CPU:$C0B5 PRG:00B5 C4 15
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bne Nmi_TransferVramDataPath_C049 ; CPU:$C0B7 PRG:00B7 D0 90
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; Routine: Nmi_ReadScreenState_C0B9
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; Global: Reachable code entry at CPU $C0B9 traced from the interrupt-root control-flow graph.
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; Local: Performs the instruction sequence below; semantic purpose remains provisional.
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; Parameters: Register and memory inputs are caller-dependent.
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; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
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; Side effects: Registers, flags, memory, and hardware registers written below.
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; Confidence: High for reachability and encoding; semantic role provisional.
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Nmi_ReadScreenState_C0B9:
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lda $72 ; CPU:$C0B9 PRG:00B9 A5 72
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beq Nmi_ReadNmiWorkPending_C0E4 ; CPU:$C0BB PRG:00BB F0 27
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lda #$22 ; CPU:$C0BD PRG:00BD A9 22
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ldx #$68 ; CPU:$C0BF PRG:00BF A2 68
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jsr SetPpuAddress ; CPU:$C0C1 PRG:00C1 20 96 C1
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ldy #$B0 ; CPU:$C0C4 PRG:00C4 A0 B0
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lda $5F ; CPU:$C0C6 PRG:00C6 A5 5F
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bne Nmi_TransferVramDataPath_C0CC ; CPU:$C0C8 PRG:00C8 D0 02
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ldy #$40 ; CPU:$C0CA PRG:00CA A0 40
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; Routine: Nmi_TransferVramDataPath_C0CC
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; Global: Reachable code entry at CPU $C0CC traced from the interrupt-root control-flow graph.
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; Local: Performs the instruction sequence below; semantic purpose remains provisional.
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; Parameters: Register and memory inputs are caller-dependent.
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; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
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; Side effects: Registers, flags, memory, and hardware registers written below.
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; Confidence: High for reachability and encoding; semantic role provisional.
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Nmi_TransferVramDataPath_C0CC:
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sty PPUDATA ; CPU:$C0CC PRG:00CC 8C 07 20
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lda #$22 ; CPU:$C0CF PRG:00CF A9 22
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ldx #$70 ; CPU:$C0D1 PRG:00D1 A2 70
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jsr SetPpuAddress ; CPU:$C0D3 PRG:00D3 20 96 C1
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ldy #$B0 ; CPU:$C0D6 PRG:00D6 A0 B0
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lda $5F ; CPU:$C0D8 PRG:00D8 A5 5F
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beq Nmi_TransferVramDataPath_C0DE ; CPU:$C0DA PRG:00DA F0 02
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ldy #$40 ; CPU:$C0DC PRG:00DC A0 40
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; Routine: Nmi_TransferVramDataPath_C0DE
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; Global: Reachable code entry at CPU $C0DE traced from the interrupt-root control-flow graph.
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; Local: Performs the instruction sequence below; semantic purpose remains provisional.
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; Parameters: Register and memory inputs are caller-dependent.
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; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
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; Side effects: Registers, flags, memory, and hardware registers written below.
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; Confidence: High for reachability and encoding; semantic role provisional.
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Nmi_TransferVramDataPath_C0DE:
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sty PPUDATA ; CPU:$C0DE PRG:00DE 8C 07 20
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jmp Nmi_ReadPpuStatusPath_C126 ; CPU:$C0E1 PRG:00E1 4C 26 C1
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; Routine: Nmi_ReadNmiWorkPending_C0E4
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; Global: Reachable code entry at CPU $C0E4 traced from the interrupt-root control-flow graph.
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; Local: Performs the instruction sequence below; semantic purpose remains provisional.
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; Parameters: Register and memory inputs are caller-dependent.
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; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
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; Side effects: Registers, flags, memory, and hardware registers written below.
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; Confidence: High for reachability and encoding; semantic role provisional.
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Nmi_ReadNmiWorkPending_C0E4:
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lda $60 ; CPU:$C0E4 PRG:00E4 A5 60
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beq Nmi_ReadPpuStatusPath_C126 ; CPU:$C0E6 PRG:00E6 F0 3E
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lda $16 ; CPU:$C0E8 PRG:00E8 A5 16
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cmp #$04 ; CPU:$C0EA PRG:00EA C9 04
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bcc Nmi_ReadPpuStatusPath_C126 ; CPU:$C0EC PRG:00EC 90 38
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lda #$20 ; CPU:$C0EE PRG:00EE A9 20
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ldx #$4B ; CPU:$C0F0 PRG:00F0 A2 4B
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jsr SetPpuAddress ; CPU:$C0F2 PRG:00F2 20 96 C1
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ldx #$00 ; CPU:$C0F5 PRG:00F5 A2 00
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; Routine: Nmi_TransferVramDataPath_C0F7
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; Global: Reachable code entry at CPU $C0F7 traced from the interrupt-root control-flow graph.
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; Local: Performs the instruction sequence below; semantic purpose remains provisional.
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; Parameters: Register and memory inputs are caller-dependent.
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; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
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; Side effects: Registers, flags, memory, and hardware registers written below.
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; Confidence: High for reachability and encoding; semantic role provisional.
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Nmi_TransferVramDataPath_C0F7:
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lda $61,x ; CPU:$C0F7 PRG:00F7 B5 61
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bne Nmi_TransferVramDataPath_C107 ; CPU:$C0F9 PRG:00F9 D0 0C
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lda #$3A ; CPU:$C0FB PRG:00FB A9 3A
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sta PPUDATA ; CPU:$C0FD PRG:00FD 8D 07 20
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inx ; CPU:$C100 PRG:0100 E8
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cpx #$07 ; CPU:$C101 PRG:0101 E0 07
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bne Nmi_TransferVramDataPath_C0F7 ; CPU:$C103 PRG:0103 D0 F2
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beq Nmi_ReadZp93_C114 ; CPU:$C105 PRG:0105 F0 0D
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; Routine: Nmi_TransferVramDataPath_C107
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; Global: Reachable code entry at CPU $C107 traced from the interrupt-root control-flow graph.
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; Local: Performs the instruction sequence below; semantic purpose remains provisional.
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; Parameters: Register and memory inputs are caller-dependent.
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; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
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; Side effects: Registers, flags, memory, and hardware registers written below.
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; Confidence: High for reachability and encoding; semantic role provisional.
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Nmi_TransferVramDataPath_C107:
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lda $61,x ; CPU:$C107 PRG:0107 B5 61
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clc ; CPU:$C109 PRG:0109 18
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adc #$30 ; CPU:$C10A PRG:010A 69 30
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sta PPUDATA ; CPU:$C10C PRG:010C 8D 07 20
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inx ; CPU:$C10F PRG:010F E8
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cpx #$07 ; CPU:$C110 PRG:0110 E0 07
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bne Nmi_TransferVramDataPath_C107 ; CPU:$C112 PRG:0112 D0 F3
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; Routine: Nmi_ReadZp93_C114
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; Global: Reachable code entry at CPU $C114 traced from the interrupt-root control-flow graph.
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; Local: Performs the instruction sequence below; semantic purpose remains provisional.
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; Parameters: Register and memory inputs are caller-dependent.
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; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
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; Side effects: Registers, flags, memory, and hardware registers written below.
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; Confidence: High for reachability and encoding; semantic role provisional.
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Nmi_ReadZp93_C114:
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lda #$20 ; CPU:$C114 PRG:0114 A9 20
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ldx #$46 ; CPU:$C116 PRG:0116 A2 46
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jsr SetPpuAddress ; CPU:$C118 PRG:0118 20 96 C1
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lda $93 ; CPU:$C11B PRG:011B A5 93
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cmp #$FF ; CPU:$C11D PRG:011D C9 FF
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bne Nmi_CallHelper_C123 ; CPU:$C11F PRG:011F D0 02
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lda #$00 ; CPU:$C121 PRG:0121 A9 00
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; Routine: Nmi_CallHelper_C123
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; Global: Reachable code entry at CPU $C123 traced from the interrupt-root control-flow graph.
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; Local: Performs the instruction sequence below; semantic purpose remains provisional.
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; Parameters: Register and memory inputs are caller-dependent.
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; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
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; Side effects: Registers, flags, memory, and hardware registers written below.
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; Confidence: High for reachability and encoding; semantic role provisional.
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Nmi_CallHelper_C123:
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jsr Menu_HandleControl_DF48 ; CPU:$C123 PRG:0123 20 48 DF
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; Routine: Nmi_ReadPpuStatusPath_C126
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; Global: Reachable code entry at CPU $C126 traced from the interrupt-root control-flow graph.
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; Local: Performs the instruction sequence below; semantic purpose remains provisional.
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; Parameters: Register and memory inputs are caller-dependent.
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; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
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; Side effects: Registers, flags, memory, and hardware registers written below.
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; Confidence: High for reachability and encoding; semantic role provisional.
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Nmi_ReadPpuStatusPath_C126:
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lda PPUSTATUS ; CPU:$C126 PRG:0126 AD 02 20
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jsr CommitPpuStateAndScroll ; CPU:$C129 PRG:0129 20 96 C2
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inc $33 ; CPU:$C12C PRG:012C E6 33
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lda $6A ; CPU:$C12E PRG:012E A5 6A
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beq Nmi_UpdateAudioChannelPath_C13E ; CPU:$C130 PRG:0130 F0 0C
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inc $69 ; CPU:$C132 PRG:0132 E6 69
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lda $69 ; CPU:$C134 PRG:0134 A5 69
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cmp #$3C ; CPU:$C136 PRG:0136 C9 3C
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bcc Nmi_UpdateAudioChannelPath_C13E ; CPU:$C138 PRG:0138 90 04
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lda #$00 ; CPU:$C13A PRG:013A A9 00
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sta $6A ; CPU:$C13C PRG:013C 85 6A
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; Routine: Nmi_UpdateAudioChannelPath_C13E
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; Global: Reachable code entry at CPU $C13E traced from the interrupt-root control-flow graph.
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; Local: Performs the instruction sequence below; semantic purpose remains provisional.
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; Parameters: Register and memory inputs are caller-dependent.
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; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
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; Side effects: Registers, flags, memory, and hardware registers written below.
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; Confidence: High for reachability and encoding; semantic role provisional.
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Nmi_UpdateAudioChannelPath_C13E:
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sta $69 ; CPU:$C13E PRG:013E 85 69
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jsr Ppu_WriteZp10_C19D ; CPU:$C140 PRG:0140 20 9D C1
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jsr Gameplay_ReadZpB2_E4C7 ; CPU:$C143 PRG:0143 20 C7 E4
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jsr SoundUpdate ; CPU:$C146 PRG:0146 20 5F E6
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lda $38 ; CPU:$C149 PRG:0149 A5 38
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beq Nmi_ReadNmiWorkPending_C16E ; CPU:$C14B PRG:014B F0 21
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lda $59 ; CPU:$C14D PRG:014D A5 59
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bne Nmi_ReadNmiWorkPending_C16E ; CPU:$C14F PRG:014F D0 1D
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lda #$0E ; CPU:$C151 PRG:0151 A9 0E
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sta APUDMCCTRL ; CPU:$C153 PRG:0153 8D 10 40
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lda #$00 ; CPU:$C156 PRG:0156 A9 00
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sta $38 ; CPU:$C158 PRG:0158 85 38
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lda #$C0 ; CPU:$C15A PRG:015A A9 C0
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sta APUDMCADDR ; CPU:$C15C PRG:015C 8D 12 40
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lda #$FF ; CPU:$C15F PRG:015F A9 FF
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sta APUDMCLENGTH ; CPU:$C161 PRG:0161 8D 13 40
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lda #$0F ; CPU:$C164 PRG:0164 A9 0F
|
|
sta APUSTATUS ; CPU:$C166 PRG:0166 8D 15 40
|
|
lda #$1F ; CPU:$C169 PRG:0169 A9 1F
|
|
sta APUSTATUS ; CPU:$C16B PRG:016B 8D 15 40
|
|
; Routine: Nmi_ReadNmiWorkPending_C16E
|
|
; Global: Reachable code entry at CPU $C16E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Nmi_ReadNmiWorkPending_C16E:
|
|
lda $60 ; CPU:$C16E PRG:016E A5 60
|
|
beq Nmi_ToggleZpDB_C18A ; CPU:$C170 PRG:0170 F0 18
|
|
; Routine: Nmi_ReadPpuStatusPath_C172
|
|
; Global: Reachable code entry at CPU $C172 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Nmi_ReadPpuStatusPath_C172:
|
|
lda PPUSTATUS ; CPU:$C172 PRG:0172 AD 02 20
|
|
and #$40 ; CPU:$C175 PRG:0175 29 40
|
|
bne Nmi_ReadPpuStatusPath_C172 ; CPU:$C177 PRG:0177 D0 F9
|
|
; Routine: Nmi_ReadPpuStatusPath_C179
|
|
; Global: Reachable code entry at CPU $C179 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Nmi_ReadPpuStatusPath_C179:
|
|
lda PPUSTATUS ; CPU:$C179 PRG:0179 AD 02 20
|
|
and #$40 ; CPU:$C17C PRG:017C 29 40
|
|
beq Nmi_ReadPpuStatusPath_C179 ; CPU:$C17E PRG:017E F0 F9
|
|
lda $0E ; CPU:$C180 PRG:0180 A5 0E
|
|
sta PPUSCROLL ; CPU:$C182 PRG:0182 8D 05 20
|
|
lda $0F ; CPU:$C185 PRG:0185 A5 0F
|
|
sta PPUSCROLL ; CPU:$C187 PRG:0187 8D 05 20
|
|
; Routine: Nmi_ToggleZpDB_C18A
|
|
; Global: Reachable code entry at CPU $C18A traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Nmi_ToggleZpDB_C18A:
|
|
lda #$05 ; CPU:$C18A PRG:018A A9 05
|
|
eor $DB ; CPU:$C18C PRG:018C 45 DB
|
|
sta $DB ; CPU:$C18E PRG:018E 85 DB
|
|
pla ; CPU:$C190 PRG:0190 68
|
|
tay ; CPU:$C191 PRG:0191 A8
|
|
pla ; CPU:$C192 PRG:0192 68
|
|
tax ; CPU:$C193 PRG:0193 AA
|
|
pla ; CPU:$C194 PRG:0194 68
|
|
rti ; CPU:$C195 PRG:0195 40
|
|
; Routine: SetPpuAddress
|
|
; Global: Reachable code entry at CPU $C196 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
SetPpuAddress:
|
|
sta PPUADDR ; CPU:$C196 PRG:0196 8D 06 20
|
|
stx PPUADDR ; CPU:$C199 PRG:0199 8E 06 20
|
|
rts ; CPU:$C19C PRG:019C 60
|
|
; Routine: Ppu_WriteZp10_C19D
|
|
; Global: Reachable code entry at CPU $C19D traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_WriteZp10_C19D:
|
|
jsr Ppu_ReadControllerAndReturnA_C1BF ; CPU:$C19D PRG:019D 20 BF C1
|
|
lda ControllerState1 ; CPU:$C1A0 PRG:01A0 A5 12
|
|
sta $10 ; CPU:$C1A2 PRG:01A2 85 10
|
|
lda $13 ; CPU:$C1A4 PRG:01A4 A5 13
|
|
sta $11 ; CPU:$C1A6 PRG:01A6 85 11
|
|
jsr Ppu_ReadControllerAndReturnA_C1BF ; CPU:$C1A8 PRG:01A8 20 BF C1
|
|
lda ControllerState1 ; CPU:$C1AB PRG:01AB A5 12
|
|
cmp $10 ; CPU:$C1AD PRG:01AD C5 10
|
|
bne Ppu_WriteZp13_C1B8 ; CPU:$C1AF PRG:01AF D0 07
|
|
lda $13 ; CPU:$C1B1 PRG:01B1 A5 13
|
|
cmp $11 ; CPU:$C1B3 PRG:01B3 C5 11
|
|
bne Ppu_WriteZp13_C1B8 ; CPU:$C1B5 PRG:01B5 D0 01
|
|
rts ; CPU:$C1B7 PRG:01B7 60
|
|
; Routine: Ppu_WriteZp13_C1B8
|
|
; Global: Reachable code entry at CPU $C1B8 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_WriteZp13_C1B8:
|
|
lda #$00 ; CPU:$C1B8 PRG:01B8 A9 00
|
|
sta ControllerState1 ; CPU:$C1BA PRG:01BA 85 12
|
|
sta $13 ; CPU:$C1BC PRG:01BC 85 13
|
|
rts ; CPU:$C1BE PRG:01BE 60
|
|
; Routine: Ppu_ReadControllerAndReturnA_C1BF
|
|
; Global: Reachable code entry at CPU $C1BF traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_ReadControllerAndReturnA_C1BF:
|
|
lda #$01 ; CPU:$C1BF PRG:01BF A9 01
|
|
sta JOY1 ; CPU:$C1C1 PRG:01C1 8D 16 40
|
|
lda #$00 ; CPU:$C1C4 PRG:01C4 A9 00
|
|
sta JOY1 ; CPU:$C1C6 PRG:01C6 8D 16 40
|
|
tax ; CPU:$C1C9 PRG:01C9 AA
|
|
ldy #$08 ; CPU:$C1CA PRG:01CA A0 08
|
|
; Routine: Ppu_ReadControllerPath_C1CC
|
|
; Global: Reachable code entry at CPU $C1CC traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_ReadControllerPath_C1CC:
|
|
txa ; CPU:$C1CC PRG:01CC 8A
|
|
asl a ; CPU:$C1CD PRG:01CD 0A
|
|
tax ; CPU:$C1CE PRG:01CE AA
|
|
lda JOY1 ; CPU:$C1CF PRG:01CF AD 16 40
|
|
jsr Ppu_HandleControl_C1EB ; CPU:$C1D2 PRG:01D2 20 EB C1
|
|
bne Ppu_ReadControllerPath_C1CC ; CPU:$C1D5 PRG:01D5 D0 F5
|
|
stx ControllerState1 ; CPU:$C1D7 PRG:01D7 86 12
|
|
ldx #$00 ; CPU:$C1D9 PRG:01D9 A2 00
|
|
ldy #$08 ; CPU:$C1DB PRG:01DB A0 08
|
|
; Routine: Ppu_ReadControllerPath_C1DD
|
|
; Global: Reachable code entry at CPU $C1DD traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_ReadControllerPath_C1DD:
|
|
txa ; CPU:$C1DD PRG:01DD 8A
|
|
asl a ; CPU:$C1DE PRG:01DE 0A
|
|
tax ; CPU:$C1DF PRG:01DF AA
|
|
lda JOY2 ; CPU:$C1E0 PRG:01E0 AD 17 40
|
|
jsr Ppu_HandleControl_C1EB ; CPU:$C1E3 PRG:01E3 20 EB C1
|
|
bne Ppu_ReadControllerPath_C1DD ; CPU:$C1E6 PRG:01E6 D0 F5
|
|
stx $13 ; CPU:$C1E8 PRG:01E8 86 13
|
|
rts ; CPU:$C1EA PRG:01EA 60
|
|
; Routine: Ppu_HandleControl_C1EB
|
|
; Global: Reachable code entry at CPU $C1EB traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_HandleControl_C1EB:
|
|
and #$03 ; CPU:$C1EB PRG:01EB 29 03
|
|
beq Ppu_RetreatIndexY_C1F0 ; CPU:$C1ED PRG:01ED F0 01
|
|
inx ; CPU:$C1EF PRG:01EF E8
|
|
; Routine: Ppu_RetreatIndexY_C1F0
|
|
; Global: Reachable code entry at CPU $C1F0 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_RetreatIndexY_C1F0:
|
|
dey ; CPU:$C1F0 PRG:01F0 88
|
|
rts ; CPU:$C1F1 PRG:01F1 60
|
|
; Routine: InitializeVideoSystem
|
|
; Global: Reachable code entry at CPU $C1F2 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
InitializeVideoSystem:
|
|
jsr DisableRendering ; CPU:$C1F2 PRG:01F2 20 57 C2
|
|
jsr Ppu_HandleControl_C2B9 ; CPU:$C1F5 PRG:01F5 20 B9 C2
|
|
lda #$10 ; CPU:$C1F8 PRG:01F8 A9 10
|
|
sta PpuCtrlShadow ; CPU:$C1FA PRG:01FA 85 0C
|
|
sta PPUCTRL ; CPU:$C1FC PRG:01FC 8D 00 20
|
|
lda #$00 ; CPU:$C1FF PRG:01FF A9 00
|
|
sta $0E ; CPU:$C201 PRG:0201 85 0E
|
|
sta $14 ; CPU:$C203 PRG:0203 85 14
|
|
sta $15 ; CPU:$C205 PRG:0205 85 15
|
|
sta $0F ; CPU:$C207 PRG:0207 85 0F
|
|
jsr HideAllSprites ; CPU:$C209 PRG:0209 20 68 C2
|
|
jsr DisableRendering ; CPU:$C20C PRG:020C 20 57 C2
|
|
jsr WaitForVBlankTransition ; CPU:$C20F PRG:020F 20 8B C2
|
|
jsr UploadSystemPalette ; CPU:$C212 PRG:0212 20 C3 C2
|
|
; Routine: Ppu_HandleControl_C215
|
|
; Global: Reachable code entry at CPU $C215 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_HandleControl_C215:
|
|
lda #$20 ; CPU:$C215 PRG:0215 A9 20
|
|
ldx #$00 ; CPU:$C217 PRG:0217 A2 00
|
|
jsr SetPpuAddress ; CPU:$C219 PRG:0219 20 96 C1
|
|
ldy #$08 ; CPU:$C21C PRG:021C A0 08
|
|
lda #$B0 ; CPU:$C21E PRG:021E A9 B0
|
|
; Routine: Ppu_TransferVramDataPath_C220
|
|
; Global: Reachable code entry at CPU $C220 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_TransferVramDataPath_C220:
|
|
sta PPUDATA ; CPU:$C220 PRG:0220 8D 07 20
|
|
dex ; CPU:$C223 PRG:0223 CA
|
|
bne Ppu_TransferVramDataPath_C220 ; CPU:$C224 PRG:0224 D0 FA
|
|
dey ; CPU:$C226 PRG:0226 88
|
|
bne Ppu_TransferVramDataPath_C220 ; CPU:$C227 PRG:0227 D0 F7
|
|
lda #$23 ; CPU:$C229 PRG:0229 A9 23
|
|
ldx #$C0 ; CPU:$C22B PRG:022B A2 C0
|
|
jsr SetPpuAddress ; CPU:$C22D PRG:022D 20 96 C1
|
|
ldx #$40 ; CPU:$C230 PRG:0230 A2 40
|
|
lda #$00 ; CPU:$C232 PRG:0232 A9 00
|
|
; Routine: Ppu_TransferVramDataPath_C234
|
|
; Global: Reachable code entry at CPU $C234 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_TransferVramDataPath_C234:
|
|
sta PPUDATA ; CPU:$C234 PRG:0234 8D 07 20
|
|
dex ; CPU:$C237 PRG:0237 CA
|
|
bne Ppu_TransferVramDataPath_C234 ; CPU:$C238 PRG:0238 D0 FA
|
|
rts ; CPU:$C23A PRG:023A 60
|
|
; Routine: Ppu_CallHelper_C23B
|
|
; Global: Reachable code entry at CPU $C23B traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_CallHelper_C23B:
|
|
jsr Ppu_HandleControl_C2B9 ; CPU:$C23B PRG:023B 20 B9 C2
|
|
jsr WaitForVBlankTransition ; CPU:$C23E PRG:023E 20 8B C2
|
|
lda #$0E ; CPU:$C241 PRG:0241 A9 0E
|
|
jsr Ppu_UpdatePpuState_C25C ; CPU:$C243 PRG:0243 20 5C C2
|
|
jsr Ppu_TransferSpriteDmaAndReturnA_C24C ; CPU:$C246 PRG:0246 20 4C C2
|
|
jmp EnableNmiInPpuControl ; CPU:$C249 PRG:0249 4C B0 C2
|
|
; Routine: Ppu_TransferSpriteDmaAndReturnA_C24C
|
|
; Global: Reachable code entry at CPU $C24C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_TransferSpriteDmaAndReturnA_C24C:
|
|
lda #$00 ; CPU:$C24C PRG:024C A9 00
|
|
sta OAMADDR ; CPU:$C24E PRG:024E 8D 03 20
|
|
lda #$07 ; CPU:$C251 PRG:0251 A9 07
|
|
sta OAMDMA ; CPU:$C253 PRG:0253 8D 14 40
|
|
rts ; CPU:$C256 PRG:0256 60
|
|
; Routine: DisableRendering
|
|
; Global: Reachable code entry at CPU $C257 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
DisableRendering:
|
|
jsr WaitForVBlankTransition ; CPU:$C257 PRG:0257 20 8B C2
|
|
lda #$00 ; CPU:$C25A PRG:025A A9 00
|
|
; Routine: Ppu_UpdatePpuState_C25C
|
|
; Global: Reachable code entry at CPU $C25C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_UpdatePpuState_C25C:
|
|
sta PPUMASK ; CPU:$C25C PRG:025C 8D 01 20
|
|
; Routine: Ppu_HandleControl_C25F
|
|
; Global: Reachable code entry at CPU $C25F traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_HandleControl_C25F:
|
|
sta PpuMaskShadow ; CPU:$C25F PRG:025F 85 0D
|
|
rts ; CPU:$C261 PRG:0261 60
|
|
; Routine: Ppu_HandleControl_C262
|
|
; Global: Reachable code entry at CPU $C262 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_HandleControl_C262:
|
|
lda PpuMaskShadow ; CPU:$C262 PRG:0262 A5 0D
|
|
ora #$10 ; CPU:$C264 PRG:0264 09 10
|
|
bne Ppu_HandleControl_C25F ; CPU:$C266 PRG:0266 D0 F7
|
|
; Routine: HideAllSprites
|
|
; Global: Reachable code entry at CPU $C268 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
HideAllSprites:
|
|
ldy #$1C ; CPU:$C268 PRG:0268 A0 1C
|
|
lda #$F8 ; CPU:$C26A PRG:026A A9 F8
|
|
; Routine: Ppu_WriteRam0700_C26C
|
|
; Global: Reachable code entry at CPU $C26C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_WriteRam0700_C26C:
|
|
sta $0700,y ; CPU:$C26C PRG:026C 99 00 07
|
|
sta $0720,y ; CPU:$C26F PRG:026F 99 20 07
|
|
sta $0740,y ; CPU:$C272 PRG:0272 99 40 07
|
|
sta $0760,y ; CPU:$C275 PRG:0275 99 60 07
|
|
sta $0780,y ; CPU:$C278 PRG:0278 99 80 07
|
|
sta $07A0,y ; CPU:$C27B PRG:027B 99 A0 07
|
|
sta $07C0,y ; CPU:$C27E PRG:027E 99 C0 07
|
|
sta $07E0,y ; CPU:$C281 PRG:0281 99 E0 07
|
|
dey ; CPU:$C284 PRG:0284 88
|
|
dey ; CPU:$C285 PRG:0285 88
|
|
dey ; CPU:$C286 PRG:0286 88
|
|
dey ; CPU:$C287 PRG:0287 88
|
|
bpl Ppu_WriteRam0700_C26C ; CPU:$C288 PRG:0288 10 E2
|
|
rts ; CPU:$C28A PRG:028A 60
|
|
; Routine: WaitForVBlankTransition
|
|
; Global: Reachable code entry at CPU $C28B traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
WaitForVBlankTransition:
|
|
lda PPUSTATUS ; CPU:$C28B PRG:028B AD 02 20
|
|
bmi WaitForVBlankTransition ; CPU:$C28E PRG:028E 30 FB
|
|
; Routine: Ppu_WaitPpuStatusPath_C290
|
|
; Global: Reachable code entry at CPU $C290 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_WaitPpuStatusPath_C290:
|
|
lda PPUSTATUS ; CPU:$C290 PRG:0290 AD 02 20
|
|
bpl Ppu_WaitPpuStatusPath_C290 ; CPU:$C293 PRG:0293 10 FB
|
|
rts ; CPU:$C295 PRG:0295 60
|
|
; Routine: CommitPpuStateAndScroll
|
|
; Global: Reachable code entry at CPU $C296 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
CommitPpuStateAndScroll:
|
|
lda PpuMaskShadow ; CPU:$C296 PRG:0296 A5 0D
|
|
sta PPUMASK ; CPU:$C298 PRG:0298 8D 01 20
|
|
lda #$00 ; CPU:$C29B PRG:029B A9 00
|
|
ldx #$00 ; CPU:$C29D PRG:029D A2 00
|
|
jsr SetPpuAddress ; CPU:$C29F PRG:029F 20 96 C1
|
|
lda #$00 ; CPU:$C2A2 PRG:02A2 A9 00
|
|
sta PPUSCROLL ; CPU:$C2A4 PRG:02A4 8D 05 20
|
|
sta PPUSCROLL ; CPU:$C2A7 PRG:02A7 8D 05 20
|
|
lda PpuCtrlShadow ; CPU:$C2AA PRG:02AA A5 0C
|
|
sta PPUCTRL ; CPU:$C2AC PRG:02AC 8D 00 20
|
|
rts ; CPU:$C2AF PRG:02AF 60
|
|
; Routine: EnableNmiInPpuControl
|
|
; Global: Reachable code entry at CPU $C2B0 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
EnableNmiInPpuControl:
|
|
jsr WaitForVBlankTransition ; CPU:$C2B0 PRG:02B0 20 8B C2
|
|
lda PpuCtrlShadow ; CPU:$C2B3 PRG:02B3 A5 0C
|
|
ora #$80 ; CPU:$C2B5 PRG:02B5 09 80
|
|
bne Ppu_UpdatePpuStatePath_C2BD ; CPU:$C2B7 PRG:02B7 D0 04
|
|
; Routine: Ppu_HandleControl_C2B9
|
|
; Global: Reachable code entry at CPU $C2B9 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_HandleControl_C2B9:
|
|
lda PpuCtrlShadow ; CPU:$C2B9 PRG:02B9 A5 0C
|
|
and #$7F ; CPU:$C2BB PRG:02BB 29 7F
|
|
; Routine: Ppu_UpdatePpuStatePath_C2BD
|
|
; Global: Reachable code entry at CPU $C2BD traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_UpdatePpuStatePath_C2BD:
|
|
sta PpuCtrlShadow ; CPU:$C2BD PRG:02BD 85 0C
|
|
sta PPUCTRL ; CPU:$C2BF PRG:02BF 8D 00 20
|
|
rts ; CPU:$C2C2 PRG:02C2 60
|
|
; Routine: UploadSystemPalette
|
|
; Global: Reachable code entry at CPU $C2C3 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
UploadSystemPalette:
|
|
lda #$3F ; CPU:$C2C3 PRG:02C3 A9 3F
|
|
ldx #$00 ; CPU:$C2C5 PRG:02C5 A2 00
|
|
jsr SetPpuAddress ; CPU:$C2C7 PRG:02C7 20 96 C1
|
|
ldy #$20 ; CPU:$C2CA PRG:02CA A0 20
|
|
; Routine: Ppu_TransferVramDataPath_C2CC
|
|
; Global: Reachable code entry at CPU $C2CC traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_TransferVramDataPath_C2CC:
|
|
lda $C2E7,x ; CPU:$C2CC PRG:02CC BD E7 C2
|
|
sta PPUDATA ; CPU:$C2CF PRG:02CF 8D 07 20
|
|
inx ; CPU:$C2D2 PRG:02D2 E8
|
|
dey ; CPU:$C2D3 PRG:02D3 88
|
|
bne Ppu_TransferVramDataPath_C2CC ; CPU:$C2D4 PRG:02D4 D0 F6
|
|
; Routine: Ppu_SetVramAddress_C2D6
|
|
; Global: Reachable code entry at CPU $C2D6 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Ppu_SetVramAddress_C2D6:
|
|
lda #$3F ; CPU:$C2D6 PRG:02D6 A9 3F
|
|
sta PPUADDR ; CPU:$C2D8 PRG:02D8 8D 06 20
|
|
lda #$00 ; CPU:$C2DB PRG:02DB A9 00
|
|
sta PPUADDR ; CPU:$C2DD PRG:02DD 8D 06 20
|
|
sta PPUADDR ; CPU:$C2E0 PRG:02E0 8D 06 20
|
|
sta PPUADDR ; CPU:$C2E3 PRG:02E3 8D 06 20
|
|
rts ; CPU:$C2E6 PRG:02E6 60
|
|
|
|
; Data region: CPU $C2E7-$C306; unreachable by direct recursive trace.
|
|
SystemPaletteData:
|
|
.byte $19, $0F, $10, $30, $19, $16, $26, $36, $19, $0F, $18, $28, $19, $0F, $17, $07 ; CPU:$C2E7 PRG:02E7 19 0F 10 30 19 16 26 36 19 0F 18 28 19 0F 17 07
|
|
.byte $19, $30, $21, $26, $19, $0F, $26, $30, $19, $0F, $15, $30, $19, $0F, $21, $30 ; CPU:$C2F7 PRG:02F7 19 30 21 26 19 0F 26 30 19 0F 15 30 19 0F 21 30
|
|
; Routine: WaitForFrameBoundary
|
|
; Global: Reachable code entry at CPU $C307 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
WaitForFrameBoundary:
|
|
lda ControllerState1 ; CPU:$C307 PRG:0307 A5 12
|
|
bne WaitForFrameBoundary ; CPU:$C309 PRG:0309 D0 FC
|
|
rts ; CPU:$C30B PRG:030B 60
|
|
; Routine: InitializeSystemAndRunMainLoop
|
|
; Global: Reachable code entry at CPU $C30C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
InitializeSystemAndRunMainLoop:
|
|
ldy #$00 ; CPU:$C30C PRG:030C A0 00
|
|
sty $E0 ; CPU:$C30E PRG:030E 84 E0
|
|
iny ; CPU:$C310 PRG:0310 C8
|
|
sty $E1 ; CPU:$C311 PRG:0311 84 E1
|
|
dey ; CPU:$C313 PRG:0313 88
|
|
tya ; CPU:$C314 PRG:0314 98
|
|
ldx #$07 ; CPU:$C315 PRG:0315 A2 07
|
|
; Routine: Main_WriteSoundDispatchIndex_C317
|
|
; Global: Reachable code entry at CPU $C317 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteSoundDispatchIndex_C317:
|
|
sta ($E0),y ; CPU:$C317 PRG:0317 91 E0
|
|
iny ; CPU:$C319 PRG:0319 C8
|
|
bne Main_WriteSoundDispatchIndex_C317 ; CPU:$C31A PRG:031A D0 FB
|
|
inc $E1 ; CPU:$C31C PRG:031C E6 E1
|
|
dex ; CPU:$C31E PRG:031E CA
|
|
bne Main_WriteSoundDispatchIndex_C317 ; CPU:$C31F PRG:031F D0 F6
|
|
ldx #$00 ; CPU:$C321 PRG:0321 A2 00
|
|
ldy $08 ; CPU:$C323 PRG:0323 A4 08
|
|
cpy #$93 ; CPU:$C325 PRG:0325 C0 93
|
|
bne Main_WriteZp00_C333 ; CPU:$C327 PRG:0327 D0 0A
|
|
ldy $09 ; CPU:$C329 PRG:0329 A4 09
|
|
bne Main_WriteZp00_C333 ; CPU:$C32B PRG:032B D0 06
|
|
ldy $0A ; CPU:$C32D PRG:032D A4 0A
|
|
bne Main_WriteZp00_C333 ; CPU:$C32F PRG:032F D0 02
|
|
ldx #$08 ; CPU:$C331 PRG:0331 A2 08
|
|
; Routine: Main_WriteZp00_C333
|
|
; Global: Reachable code entry at CPU $C333 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteZp00_C333:
|
|
sta $00,x ; CPU:$C333 PRG:0333 95 00
|
|
inx ; CPU:$C335 PRG:0335 E8
|
|
bne Main_WriteZp00_C333 ; CPU:$C336 PRG:0336 D0 FB
|
|
lda #$93 ; CPU:$C338 PRG:0338 A9 93
|
|
sta $08 ; CPU:$C33A PRG:033A 85 08
|
|
; Routine: Main_WriteZpDB_C33C
|
|
; Global: Reachable code entry at CPU $C33C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteZpDB_C33C:
|
|
jsr InitializeVideoSystem ; CPU:$C33C PRG:033C 20 F2 C1
|
|
lda #$00 ; CPU:$C33F PRG:033F A9 00
|
|
sta $DB ; CPU:$C341 PRG:0341 85 DB
|
|
jsr InitializeApu ; CPU:$C343 PRG:0343 20 42 E6
|
|
lda #$01 ; CPU:$C346 PRG:0346 A9 01
|
|
sta $B5 ; CPU:$C348 PRG:0348 85 B5
|
|
; Routine: Main_UpdateAudioChannelPath_C34A
|
|
; Global: Reachable code entry at CPU $C34A traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_UpdateAudioChannelPath_C34A:
|
|
ldx #$FF ; CPU:$C34A PRG:034A A2 FF
|
|
txs ; CPU:$C34C PRG:034C 9A
|
|
lda #$0F ; CPU:$C34D PRG:034D A9 0F
|
|
sta APUSTATUS ; CPU:$C34F PRG:034F 8D 15 40
|
|
lda #$00 ; CPU:$C352 PRG:0352 A9 00
|
|
sta $38 ; CPU:$C354 PRG:0354 85 38
|
|
sta $59 ; CPU:$C356 PRG:0356 85 59
|
|
sta $B2 ; CPU:$C358 PRG:0358 85 B2
|
|
sta $60 ; CPU:$C35A PRG:035A 85 60
|
|
sta $70 ; CPU:$C35C PRG:035C 85 70
|
|
jsr ComposeStatusScreen ; CPU:$C35E PRG:035E 20 83 DE
|
|
jsr EnableNmiInPpuControl ; CPU:$C361 PRG:0361 20 B0 C2
|
|
lda #$01 ; CPU:$C364 PRG:0364 A9 01
|
|
sta $72 ; CPU:$C366 PRG:0366 85 72
|
|
; Routine: MainGameLoop
|
|
; Global: Reachable code entry at CPU $C368 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
MainGameLoop:
|
|
lda ControllerState1 ; CPU:$C368 PRG:0368 A5 12
|
|
bne MainGameLoop ; CPU:$C36A PRG:036A D0 FC
|
|
; Routine: Main_WriteMainDelay_C36C
|
|
; Global: Reachable code entry at CPU $C36C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteMainDelay_C36C:
|
|
lda #$08 ; CPU:$C36C PRG:036C A9 08
|
|
sta $70 ; CPU:$C36E PRG:036E 85 70
|
|
; Routine: Main_ReadOptionState_C370
|
|
; Global: Reachable code entry at CPU $C370 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReadOptionState_C370:
|
|
jsr WaitForNmiFrameHandoff ; CPU:$C370 PRG:0370 20 FB CB
|
|
lda ControllerState1 ; CPU:$C373 PRG:0373 A5 12
|
|
and #$10 ; CPU:$C375 PRG:0375 29 10
|
|
bne Main_ReadGameState_C398 ; CPU:$C377 PRG:0377 D0 1F
|
|
lda ControllerState1 ; CPU:$C379 PRG:0379 A5 12
|
|
and #$20 ; CPU:$C37B PRG:037B 29 20
|
|
beq Main_DecrementSubDelay_C38B ; CPU:$C37D PRG:037D F0 0C
|
|
lda $5F ; CPU:$C37F PRG:037F A5 5F
|
|
eor #$01 ; CPU:$C381 PRG:0381 49 01
|
|
sta $5F ; CPU:$C383 PRG:0383 85 5F
|
|
jsr WaitForFrameBoundary ; CPU:$C385 PRG:0385 20 07 C3
|
|
jmp Main_WriteMainDelay_C36C ; CPU:$C388 PRG:0388 4C 6C C3
|
|
; Routine: Main_DecrementSubDelay_C38B
|
|
; Global: Reachable code entry at CPU $C38B traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_DecrementSubDelay_C38B:
|
|
jsr AdvanceRandomState ; CPU:$C38B PRG:038B 20 70 D6
|
|
dec $71 ; CPU:$C38E PRG:038E C6 71
|
|
bne Main_ReadOptionState_C370 ; CPU:$C390 PRG:0390 D0 DE
|
|
dec $70 ; CPU:$C392 PRG:0392 C6 70
|
|
bne Main_ReadOptionState_C370 ; CPU:$C394 PRG:0394 D0 DA
|
|
inc $59 ; CPU:$C396 PRG:0396 E6 59
|
|
; Routine: Main_ReadGameState_C398
|
|
; Global: Reachable code entry at CPU $C398 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReadGameState_C398:
|
|
lda $59 ; CPU:$C398 PRG:0398 A5 59
|
|
bne Main_WriteScreenState_C3A3 ; CPU:$C39A PRG:039A D0 07
|
|
lda $5F ; CPU:$C39C PRG:039C A5 5F
|
|
beq Main_WriteScreenState_C3A3 ; CPU:$C39E PRG:039E F0 03
|
|
jsr RunMenuSelectionScreen ; CPU:$C3A0 PRG:03A0 20 8E DA
|
|
; Routine: Main_WriteScreenState_C3A3
|
|
; Global: Reachable code entry at CPU $C3A3 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteScreenState_C3A3:
|
|
lda #$00 ; CPU:$C3A3 PRG:03A3 A9 00
|
|
sta $72 ; CPU:$C3A5 PRG:03A5 85 72
|
|
jsr WaitForFrameBoundary ; CPU:$C3A7 PRG:03A7 20 07 C3
|
|
lda #$02 ; CPU:$C3AA PRG:03AA A9 02
|
|
sta $68 ; CPU:$C3AC PRG:03AC 85 68
|
|
lda $59 ; CPU:$C3AE PRG:03AE A5 59
|
|
bne Main_WriteZp58_C3B6 ; CPU:$C3B0 PRG:03B0 D0 04
|
|
lda $5F ; CPU:$C3B2 PRG:03B2 A5 5F
|
|
bne Main_WriteObjectDirection_C40A ; CPU:$C3B4 PRG:03B4 D0 54
|
|
; Routine: Main_WriteZp58_C3B6
|
|
; Global: Reachable code entry at CPU $C3B6 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteZp58_C3B6:
|
|
lda #$01 ; CPU:$C3B6 PRG:03B6 A9 01
|
|
sta $58 ; CPU:$C3B8 PRG:03B8 85 58
|
|
lda $59 ; CPU:$C3BA PRG:03BA A5 59
|
|
bne Main_UpdateAudioChannelPath_C3C7 ; CPU:$C3BC PRG:03BC D0 09
|
|
ldx #$06 ; CPU:$C3BE PRG:03BE A2 06
|
|
lda #$00 ; CPU:$C3C0 PRG:03C0 A9 00
|
|
; Routine: Main_WriteZp61_C3C2
|
|
; Global: Reachable code entry at CPU $C3C2 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteZp61_C3C2:
|
|
sta $61,x ; CPU:$C3C2 PRG:03C2 95 61
|
|
dex ; CPU:$C3C4 PRG:03C4 CA
|
|
bpl Main_WriteZp61_C3C2 ; CPU:$C3C5 PRG:03C5 10 FB
|
|
; Routine: Main_UpdateAudioChannelPath_C3C7
|
|
; Global: Reachable code entry at CPU $C3C7 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_UpdateAudioChannelPath_C3C7:
|
|
lda #$10 ; CPU:$C3C7 PRG:03C7 A9 10
|
|
sta $73 ; CPU:$C3C9 PRG:03C9 85 73
|
|
lda #$00 ; CPU:$C3CB PRG:03CB A9 00
|
|
sta $74 ; CPU:$C3CD PRG:03CD 85 74
|
|
sta $77 ; CPU:$C3CF PRG:03CF 85 77
|
|
sta $75 ; CPU:$C3D1 PRG:03D1 85 75
|
|
sta $76 ; CPU:$C3D3 PRG:03D3 85 76
|
|
sta $79 ; CPU:$C3D5 PRG:03D5 85 79
|
|
sta $94 ; CPU:$C3D7 PRG:03D7 85 94
|
|
lda $59 ; CPU:$C3D9 PRG:03D9 A5 59
|
|
beq Main_WriteObjectDirection_C40A ; CPU:$C3DB PRG:03DB F0 2D
|
|
lda #$09 ; CPU:$C3DD PRG:03DD A9 09
|
|
sta $74 ; CPU:$C3DF PRG:03DF 85 74
|
|
lda #$40 ; CPU:$C3E1 PRG:03E1 A9 40
|
|
sta $73 ; CPU:$C3E3 PRG:03E3 85 73
|
|
lda #$01 ; CPU:$C3E5 PRG:03E5 A9 01
|
|
sta $77 ; CPU:$C3E7 PRG:03E7 85 77
|
|
lda #$00 ; CPU:$C3E9 PRG:03E9 A9 00
|
|
sta APUSTATUS ; CPU:$C3EB PRG:03EB 8D 15 40
|
|
sta RandomState0 ; CPU:$C3EE PRG:03EE 85 54
|
|
sta RandomState1 ; CPU:$C3F0 PRG:03F0 85 55
|
|
sta RandomState2 ; CPU:$C3F2 PRG:03F2 85 56
|
|
sta RandomState3 ; CPU:$C3F4 PRG:03F4 85 57
|
|
sta $33 ; CPU:$C3F6 PRG:03F6 85 33
|
|
lda #$F4 ; CPU:$C3F8 PRG:03F8 A9 F4
|
|
sta $AC ; CPU:$C3FA PRG:03FA 85 AC
|
|
lda #$ED ; CPU:$C3FC PRG:03FC A9 ED
|
|
sta $AD ; CPU:$C3FE PRG:03FE 85 AD
|
|
lda $EDF2 ; CPU:$C400 PRG:0400 AD F2 ED
|
|
sta $AE ; CPU:$C403 PRG:0403 85 AE
|
|
lda $EDF3 ; CPU:$C405 PRG:0405 AD F3 ED
|
|
sta $AF ; CPU:$C408 PRG:0408 85 AF
|
|
; Routine: Main_WriteObjectDirection_C40A
|
|
; Global: Reachable code entry at CPU $C40A traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteObjectDirection_C40A:
|
|
lda #$00 ; CPU:$C40A PRG:040A A9 00
|
|
sta $78 ; CPU:$C40C PRG:040C 85 78
|
|
sta $7A ; CPU:$C40E PRG:040E 85 7A
|
|
; Routine: Main_WriteZpB1_C410
|
|
; Global: Reachable code entry at CPU $C410 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteZpB1_C410:
|
|
lda #$00 ; CPU:$C410 PRG:0410 A9 00
|
|
sta $B1 ; CPU:$C412 PRG:0412 85 B1
|
|
sta $A8 ; CPU:$C414 PRG:0414 85 A8
|
|
sta $60 ; CPU:$C416 PRG:0416 85 60
|
|
sta $9E ; CPU:$C418 PRG:0418 85 9E
|
|
sta $9F ; CPU:$C41A PRG:041A 85 9F
|
|
sta $9C ; CPU:$C41C PRG:041C 85 9C
|
|
sta $A0 ; CPU:$C41E PRG:041E 85 A0
|
|
sta $A1 ; CPU:$C420 PRG:0420 85 A1
|
|
sta $A2 ; CPU:$C422 PRG:0422 85 A2
|
|
sta $A3 ; CPU:$C424 PRG:0424 85 A3
|
|
sta $A4 ; CPU:$C426 PRG:0426 85 A4
|
|
sta $A5 ; CPU:$C428 PRG:0428 85 A5
|
|
sta $A6 ; CPU:$C42A PRG:042A 85 A6
|
|
sta $A7 ; CPU:$C42C PRG:042C 85 A7
|
|
jsr Menu_WriteZp0E_DE1D ; CPU:$C42E PRG:042E 20 1D DE
|
|
lda #$02 ; CPU:$C431 PRG:0431 A9 02
|
|
sta $B5 ; CPU:$C433 PRG:0433 85 B5
|
|
jsr Main_ReadGameMode_C60B ; CPU:$C435 PRG:0435 20 0B C6
|
|
lda #$03 ; CPU:$C438 PRG:0438 A9 03
|
|
sta $B5 ; CPU:$C43A PRG:043A 85 B5
|
|
jsr Ppu_HandleControl_C2B9 ; CPU:$C43C PRG:043C 20 B9 C2
|
|
jsr Gameplay_WriteTransferPointer_CA4B ; CPU:$C43F PRG:043F 20 4B CA
|
|
jsr Main_WriteObjectType_C5CE ; CPU:$C442 PRG:0442 20 CE C5
|
|
jsr Gameplay_ReadZp58_E4AF ; CPU:$C445 PRG:0445 20 AF E4
|
|
jsr Main_CallHelper_C5FF ; CPU:$C448 PRG:0448 20 FF C5
|
|
lda #$C8 ; CPU:$C44B PRG:044B A9 C8
|
|
sta $93 ; CPU:$C44D PRG:044D 85 93
|
|
; Routine: Main_ReadZp5D_C44F
|
|
; Global: Reachable code entry at CPU $C44F traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReadZp5D_C44F:
|
|
jsr Main_WriteStageCounter_C613 ; CPU:$C44F PRG:044F 20 13 C6
|
|
jsr HideAllSprites ; CPU:$C452 PRG:0452 20 68 C2
|
|
jsr Frame_ReadZp7D_CC36 ; CPU:$C455 PRG:0455 20 36 CC
|
|
jsr Gameplay_HandleControl_C96A ; CPU:$C458 PRG:0458 20 6A C9
|
|
jsr Frame_ReadObjectIndex_CE5B ; CPU:$C45B PRG:045B 20 5B CE
|
|
jsr Object_WriteStageProgress_CFB0 ; CPU:$C45E PRG:045E 20 B0 CF
|
|
jsr Gameplay_HandleControl_CA1B ; CPU:$C461 PRG:0461 20 1B CA
|
|
jsr Main_ReadZp33_C644 ; CPU:$C464 PRG:0464 20 44 C6
|
|
jsr Gameplay_ReadStageProgress_E399 ; CPU:$C467 PRG:0467 20 99 E3
|
|
lda $5D ; CPU:$C46A PRG:046A A5 5D
|
|
bne Main_ReadGameState_C481 ; CPU:$C46C PRG:046C D0 13
|
|
lda $5E ; CPU:$C46E PRG:046E A5 5E
|
|
bne Main_ReadGameState_C4BF ; CPU:$C470 PRG:0470 D0 4D
|
|
lda $33 ; CPU:$C472 PRG:0472 A5 33
|
|
and #$03 ; CPU:$C474 PRG:0474 29 03
|
|
bne Main_ReadZp5D_C44F ; CPU:$C476 PRG:0476 D0 D7
|
|
jsr GameplayUpdate ; CPU:$C478 PRG:0478 20 9D C7
|
|
jsr Main_HandleControl_C66C ; CPU:$C47B PRG:047B 20 6C C6
|
|
jmp Main_ReadZp5D_C44F ; CPU:$C47E PRG:047E 4C 4F C4
|
|
; Routine: Main_ReadGameState_C481
|
|
; Global: Reachable code entry at CPU $C481 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReadGameState_C481:
|
|
lda $59 ; CPU:$C481 PRG:0481 A5 59
|
|
bne Main_WriteGameMode_C4C3 ; CPU:$C483 PRG:0483 D0 3E
|
|
lda #$00 ; CPU:$C485 PRG:0485 A9 00
|
|
sta $76 ; CPU:$C487 PRG:0487 85 76
|
|
sta $78 ; CPU:$C489 PRG:0489 85 78
|
|
sta $77 ; CPU:$C48B PRG:048B 85 77
|
|
sta $79 ; CPU:$C48D PRG:048D 85 79
|
|
sta $7A ; CPU:$C48F PRG:048F 85 7A
|
|
lda #$08 ; CPU:$C491 PRG:0491 A9 08
|
|
sta $B5 ; CPU:$C493 PRG:0493 85 B5
|
|
jsr Main_ReadGameMode_C60B ; CPU:$C495 PRG:0495 20 0B C6
|
|
dec $68 ; CPU:$C498 PRG:0498 C6 68
|
|
bmi Main_WriteNmiWorkPending_C49F ; CPU:$C49A PRG:049A 30 03
|
|
jmp Main_WriteZpB1_C410 ; CPU:$C49C PRG:049C 4C 10 C4
|
|
; Routine: Main_WriteNmiWorkPending_C49F
|
|
; Global: Reachable code entry at CPU $C49F traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteNmiWorkPending_C49F:
|
|
lda #$00 ; CPU:$C49F PRG:049F A9 00
|
|
sta $60 ; CPU:$C4A1 PRG:04A1 85 60
|
|
jsr Menu_CallHelper_DD3E ; CPU:$C4A3 PRG:04A3 20 3E DD
|
|
lda #$09 ; CPU:$C4A6 PRG:04A6 A9 09
|
|
sta $B5 ; CPU:$C4A8 PRG:04A8 85 B5
|
|
; Routine: Main_ReadGameMode_C4AA
|
|
; Global: Reachable code entry at CPU $C4AA traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReadGameMode_C4AA:
|
|
lda ControllerState1 ; CPU:$C4AA PRG:04AA A5 12
|
|
and #$10 ; CPU:$C4AC PRG:04AC 29 10
|
|
bne Main_WriteGameMode_C4B4 ; CPU:$C4AE PRG:04AE D0 04
|
|
lda $B5 ; CPU:$C4B0 PRG:04B0 A5 B5
|
|
bne Main_ReadGameMode_C4AA ; CPU:$C4B2 PRG:04B2 D0 F6
|
|
; Routine: Main_WriteGameMode_C4B4
|
|
; Global: Reachable code entry at CPU $C4B4 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteGameMode_C4B4:
|
|
lda #$00 ; CPU:$C4B4 PRG:04B4 A9 00
|
|
sta $B5 ; CPU:$C4B6 PRG:04B6 85 B5
|
|
; Routine: Main_HandleControl_C4B8
|
|
; Global: Reachable code entry at CPU $C4B8 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_HandleControl_C4B8:
|
|
lda ControllerState1 ; CPU:$C4B8 PRG:04B8 A5 12
|
|
beq Main_HandleControl_C4B8 ; CPU:$C4BA PRG:04BA F0 FC
|
|
jmp Main_UpdateAudioChannelPath_C34A ; CPU:$C4BC PRG:04BC 4C 4A C3
|
|
; Routine: Main_ReadGameState_C4BF
|
|
; Global: Reachable code entry at CPU $C4BF traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReadGameState_C4BF:
|
|
lda $59 ; CPU:$C4BF PRG:04BF A5 59
|
|
beq Main_WriteGameMode_C4D5 ; CPU:$C4C1 PRG:04C1 F0 12
|
|
; Routine: Main_WriteGameMode_C4C3
|
|
; Global: Reachable code entry at CPU $C4C3 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteGameMode_C4C3:
|
|
lda #$00 ; CPU:$C4C3 PRG:04C3 A9 00
|
|
sta $B5 ; CPU:$C4C5 PRG:04C5 85 B5
|
|
inc $B0 ; CPU:$C4C7 PRG:04C7 E6 B0
|
|
lda $B0 ; CPU:$C4C9 PRG:04C9 A5 B0
|
|
and #$03 ; CPU:$C4CB PRG:04CB 29 03
|
|
beq Main_Dispatch_C4D2 ; CPU:$C4CD PRG:04CD F0 03
|
|
jmp Main_UpdateAudioChannelPath_C34A ; CPU:$C4CF PRG:04CF 4C 4A C3
|
|
; Routine: Main_Dispatch_C4D2
|
|
; Global: Reachable code entry at CPU $C4D2 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_Dispatch_C4D2:
|
|
jmp Main_WriteZpDB_C33C ; CPU:$C4D2 PRG:04D2 4C 3C C3
|
|
; Routine: Main_WriteGameMode_C4D5
|
|
; Global: Reachable code entry at CPU $C4D5 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteGameMode_C4D5:
|
|
lda #$0A ; CPU:$C4D5 PRG:04D5 A9 0A
|
|
sta $B5 ; CPU:$C4D7 PRG:04D7 85 B5
|
|
jsr Main_ReadGameMode_C60B ; CPU:$C4D9 PRG:04D9 20 0B C6
|
|
inc $68 ; CPU:$C4DC PRG:04DC E6 68
|
|
inc $58 ; CPU:$C4DE PRG:04DE E6 58
|
|
ldy #$00 ; CPU:$C4E0 PRG:04E0 A0 00
|
|
lda $58 ; CPU:$C4E2 PRG:04E2 A5 58
|
|
cmp #$33 ; CPU:$C4E4 PRG:04E4 C9 33
|
|
bne Main_AdvanceIndexY_C4EB ; CPU:$C4E6 PRG:04E6 D0 03
|
|
jmp Main_WriteObjectX_C56C ; CPU:$C4E8 PRG:04E8 4C 6C C5
|
|
; Routine: Main_AdvanceIndexY_C4EB
|
|
; Global: Reachable code entry at CPU $C4EB traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_AdvanceIndexY_C4EB:
|
|
iny ; CPU:$C4EB PRG:04EB C8
|
|
sec ; CPU:$C4EC PRG:04EC 38
|
|
sbc #$05 ; CPU:$C4ED PRG:04ED E9 05
|
|
bcs Main_AdvanceIndexY_C4EB ; CPU:$C4EF PRG:04EF B0 FA
|
|
dey ; CPU:$C4F1 PRG:04F1 88
|
|
cpy #$08 ; CPU:$C4F2 PRG:04F2 C0 08
|
|
bcc Main_WriteZp7E_C4F8 ; CPU:$C4F4 PRG:04F4 90 02
|
|
ldy #$08 ; CPU:$C4F6 PRG:04F6 A0 08
|
|
; Routine: Main_WriteZp7E_C4F8
|
|
; Global: Reachable code entry at CPU $C4F8 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteZp7E_C4F8:
|
|
sty $7E ; CPU:$C4F8 PRG:04F8 84 7E
|
|
adc #$05 ; CPU:$C4FA PRG:04FA 69 05
|
|
cmp #$01 ; CPU:$C4FC PRG:04FC C9 01
|
|
beq Main_WriteNmiWorkPending_C503 ; CPU:$C4FE PRG:04FE F0 03
|
|
jmp Main_WriteZpB1_C410 ; CPU:$C500 PRG:0500 4C 10 C4
|
|
; Routine: Main_WriteNmiWorkPending_C503
|
|
; Global: Reachable code entry at CPU $C503 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteNmiWorkPending_C503:
|
|
lda #$00 ; CPU:$C503 PRG:0503 A9 00
|
|
sta $60 ; CPU:$C505 PRG:0505 85 60
|
|
jsr Menu_WriteZp0E_DE53 ; CPU:$C507 PRG:0507 20 53 DE
|
|
lda #$02 ; CPU:$C50A PRG:050A A9 02
|
|
sta $B5 ; CPU:$C50C PRG:050C 85 B5
|
|
jsr Main_ReadGameMode_C60B ; CPU:$C50E PRG:050E 20 0B C6
|
|
jsr Ppu_HandleControl_C2B9 ; CPU:$C511 PRG:0511 20 B9 C2
|
|
jsr Gameplay_WriteTransferPointer_CA72 ; CPU:$C514 PRG:0514 20 72 CA
|
|
jsr Main_WriteObjectType_C5CE ; CPU:$C517 PRG:0517 20 CE C5
|
|
jsr Main_CallHelper_C5FF ; CPU:$C51A PRG:051A 20 FF C5
|
|
jsr Gameplay_HandleControl_CBC5 ; CPU:$C51D PRG:051D 20 C5 CB
|
|
lda #$06 ; CPU:$C520 PRG:0520 A9 06
|
|
sta $B5 ; CPU:$C522 PRG:0522 85 B5
|
|
lda #$01 ; CPU:$C524 PRG:0524 A9 01
|
|
sta $7A ; CPU:$C526 PRG:0526 85 7A
|
|
sta $7D ; CPU:$C528 PRG:0528 85 7D
|
|
lda #$1E ; CPU:$C52A PRG:052A A9 1E
|
|
sta $93 ; CPU:$C52C PRG:052C 85 93
|
|
; Routine: Main_ReadZp93_C52E
|
|
; Global: Reachable code entry at CPU $C52E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReadZp93_C52E:
|
|
jsr Main_WriteStageCounter_C613 ; CPU:$C52E PRG:052E 20 13 C6
|
|
lda $93 ; CPU:$C531 PRG:0531 A5 93
|
|
beq Main_WriteGameMode_C55C ; CPU:$C533 PRG:0533 F0 27
|
|
jsr HideAllSprites ; CPU:$C535 PRG:0535 20 68 C2
|
|
jsr Gameplay_HandleControl_C8ED ; CPU:$C538 PRG:0538 20 ED C8
|
|
jsr Frame_ReadZp7D_CC36 ; CPU:$C53B PRG:053B 20 36 CC
|
|
jsr Gameplay_HandleControl_C96A ; CPU:$C53E PRG:053E 20 6A C9
|
|
jsr Frame_ReadObjectIndex_CE5B ; CPU:$C541 PRG:0541 20 5B CE
|
|
jsr Object_WriteStageProgress_CFB0 ; CPU:$C544 PRG:0544 20 B0 CF
|
|
jsr Gameplay_HandleControl_CA1B ; CPU:$C547 PRG:0547 20 1B CA
|
|
jsr Main_ReadZp33_C65F ; CPU:$C54A PRG:054A 20 5F C6
|
|
lda $33 ; CPU:$C54D PRG:054D A5 33
|
|
and #$01 ; CPU:$C54F PRG:054F 29 01
|
|
bne Main_ReadZp93_C52E ; CPU:$C551 PRG:0551 D0 DB
|
|
jsr GameplayUpdate ; CPU:$C553 PRG:0553 20 9D C7
|
|
jsr Main_HandleControl_C66C ; CPU:$C556 PRG:0556 20 6C C6
|
|
jmp Main_ReadZp93_C52E ; CPU:$C559 PRG:0559 4C 2E C5
|
|
; Routine: Main_WriteGameMode_C55C
|
|
; Global: Reachable code entry at CPU $C55C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteGameMode_C55C:
|
|
lda #$0A ; CPU:$C55C PRG:055C A9 0A
|
|
sta $B5 ; CPU:$C55E PRG:055E 85 B5
|
|
jsr Main_ReadGameMode_C60B ; CPU:$C560 PRG:0560 20 0B C6
|
|
lda #$00 ; CPU:$C563 PRG:0563 A9 00
|
|
sta $7D ; CPU:$C565 PRG:0565 85 7D
|
|
sta $7A ; CPU:$C567 PRG:0567 85 7A
|
|
jmp Main_WriteZpB1_C410 ; CPU:$C569 PRG:0569 4C 10 C4
|
|
; Routine: Main_WriteObjectX_C56C
|
|
; Global: Reachable code entry at CPU $C56C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteObjectX_C56C:
|
|
jsr InitializeVideoSystem ; CPU:$C56C PRG:056C 20 F2 C1
|
|
jsr Menu_WriteWorkValue_DBF9 ; CPU:$C56F PRG:056F 20 F9 DB
|
|
jsr Gameplay_WriteTransferPointer_CA72 ; CPU:$C572 PRG:0572 20 72 CA
|
|
lda #$08 ; CPU:$C575 PRG:0575 A9 08
|
|
sta $29 ; CPU:$C577 PRG:0577 85 29
|
|
sta $2B ; CPU:$C579 PRG:0579 85 2B
|
|
lda #$00 ; CPU:$C57B PRG:057B A9 00
|
|
sta $60 ; CPU:$C57D PRG:057D 85 60
|
|
sta $28 ; CPU:$C57F PRG:057F 85 28
|
|
lda #$09 ; CPU:$C581 PRG:0581 A9 09
|
|
sta $2A ; CPU:$C583 PRG:0583 85 2A
|
|
lda #$07 ; CPU:$C585 PRG:0585 A9 07
|
|
sta $B5 ; CPU:$C587 PRG:0587 85 B5
|
|
jsr Ppu_HandleControl_C262 ; CPU:$C589 PRG:0589 20 62 C2
|
|
jsr EnableNmiInPpuControl ; CPU:$C58C PRG:058C 20 B0 C2
|
|
; Routine: Main_WriteStageCounter_C58F
|
|
; Global: Reachable code entry at CPU $C58F traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteStageCounter_C58F:
|
|
jsr WaitForNmiFrameHandoff ; CPU:$C58F PRG:058F 20 FB CB
|
|
lda #$01 ; CPU:$C592 PRG:0592 A9 01
|
|
sta $39 ; CPU:$C594 PRG:0594 85 39
|
|
jsr HideAllSprites ; CPU:$C596 PRG:0596 20 68 C2
|
|
jsr Frame_ReadObjectIndex_CE5B ; CPU:$C599 PRG:0599 20 5B CE
|
|
lda $33 ; CPU:$C59C PRG:059C A5 33
|
|
ror a ; CPU:$C59E PRG:059E 6A
|
|
bcs Main_ReadObjectType_C5A4 ; CPU:$C59F PRG:059F B0 03
|
|
jsr Frame_ReadObjectX_CDD4 ; CPU:$C5A1 PRG:05A1 20 D4 CD
|
|
; Routine: Main_ReadObjectType_C5A4
|
|
; Global: Reachable code entry at CPU $C5A4 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReadObjectType_C5A4:
|
|
lda $28 ; CPU:$C5A4 PRG:05A4 A5 28
|
|
cmp #$08 ; CPU:$C5A6 PRG:05A6 C9 08
|
|
bne Main_WriteStageCounter_C58F ; CPU:$C5A8 PRG:05A8 D0 E5
|
|
; Routine: Main_WriteStageCounter_C5AA
|
|
; Global: Reachable code entry at CPU $C5AA traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteStageCounter_C5AA:
|
|
jsr WaitForNmiFrameHandoff ; CPU:$C5AA PRG:05AA 20 FB CB
|
|
lda #$01 ; CPU:$C5AD PRG:05AD A9 01
|
|
sta $39 ; CPU:$C5AF PRG:05AF 85 39
|
|
jsr HideAllSprites ; CPU:$C5B1 PRG:05B1 20 68 C2
|
|
jsr Frame_ReadZp2D_CEA7 ; CPU:$C5B4 PRG:05B4 20 A7 CE
|
|
lda $33 ; CPU:$C5B7 PRG:05B7 A5 33
|
|
ror a ; CPU:$C5B9 PRG:05B9 6A
|
|
bcs Main_ReadGameMode_C5BF ; CPU:$C5BA PRG:05BA B0 03
|
|
jsr Frame_ReadObjectX_CDD4 ; CPU:$C5BC PRG:05BC 20 D4 CD
|
|
; Routine: Main_ReadGameMode_C5BF
|
|
; Global: Reachable code entry at CPU $C5BF traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReadGameMode_C5BF:
|
|
lda $B5 ; CPU:$C5BF PRG:05BF A5 B5
|
|
bne Main_WriteStageCounter_C5AA ; CPU:$C5C1 PRG:05C1 D0 E7
|
|
; Routine: Main_WriteZp58_C5C3
|
|
; Global: Reachable code entry at CPU $C5C3 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteZp58_C5C3:
|
|
lda ControllerState1 ; CPU:$C5C3 PRG:05C3 A5 12
|
|
beq Main_WriteZp58_C5C3 ; CPU:$C5C5 PRG:05C5 F0 FC
|
|
lda #$01 ; CPU:$C5C7 PRG:05C7 A9 01
|
|
sta $58 ; CPU:$C5C9 PRG:05C9 85 58
|
|
jmp Main_WriteZpB1_C410 ; CPU:$C5CB PRG:05CB 4C 10 C4
|
|
; Routine: Main_WriteObjectType_C5CE
|
|
; Global: Reachable code entry at CPU $C5CE traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteObjectType_C5CE:
|
|
lda #$01 ; CPU:$C5CE PRG:05CE A9 01
|
|
sta $28 ; CPU:$C5D0 PRG:05D0 85 28
|
|
sta $2A ; CPU:$C5D2 PRG:05D2 85 2A
|
|
lda #$08 ; CPU:$C5D4 PRG:05D4 A9 08
|
|
sta $29 ; CPU:$C5D6 PRG:05D6 85 29
|
|
sta $2B ; CPU:$C5D8 PRG:05D8 85 2B
|
|
lda #$00 ; CPU:$C5DA PRG:05DA A9 00
|
|
sta $2C ; CPU:$C5DC PRG:05DC 85 2C
|
|
sta $5D ; CPU:$C5DE PRG:05DE 85 5D
|
|
sta $5C ; CPU:$C5E0 PRG:05E0 85 5C
|
|
sta $5E ; CPU:$C5E2 PRG:05E2 85 5E
|
|
jsr Gameplay_HandleControl_CBC5 ; CPU:$C5E4 PRG:05E4 20 C5 CB
|
|
jsr Stage_ReadZp58_D69A ; CPU:$C5E7 PRG:05E7 20 9A D6
|
|
jsr Gameplay_WriteWorkValue_CB06 ; CPU:$C5EA PRG:05EA 20 06 CB
|
|
jsr WaitForVBlankTransition ; CPU:$C5ED PRG:05ED 20 8B C2
|
|
jsr UploadSystemPalette ; CPU:$C5F0 PRG:05F0 20 C3 C2
|
|
ldx $58 ; CPU:$C5F3 PRG:05F3 A6 58
|
|
lda $CC03,x ; CPU:$C5F5 PRG:05F5 BD 03 CC
|
|
sta $5B ; CPU:$C5F8 PRG:05F8 85 5B
|
|
lda #$01 ; CPU:$C5FA PRG:05FA A9 01
|
|
sta $60 ; CPU:$C5FC PRG:05FC 85 60
|
|
rts ; CPU:$C5FE PRG:05FE 60
|
|
; Routine: Main_CallHelper_C5FF
|
|
; Global: Reachable code entry at CPU $C5FF traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_CallHelper_C5FF:
|
|
jsr HideAllSprites ; CPU:$C5FF PRG:05FF 20 68 C2
|
|
jsr EnableNmiInPpuControl ; CPU:$C602 PRG:0602 20 B0 C2
|
|
jsr Ppu_CallHelper_C23B ; CPU:$C605 PRG:0605 20 3B C2
|
|
jmp Ppu_HandleControl_C262 ; CPU:$C608 PRG:0608 4C 62 C2
|
|
; Routine: Main_ReadGameMode_C60B
|
|
; Global: Reachable code entry at CPU $C60B traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReadGameMode_C60B:
|
|
lda $B5 ; CPU:$C60B PRG:060B A5 B5
|
|
bne Main_ReadGameMode_C60B ; CPU:$C60D PRG:060D D0 FC
|
|
rts ; CPU:$C60F PRG:060F 60
|
|
; Routine: Main_Dispatch_C610
|
|
; Global: Reachable code entry at CPU $C610 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_Dispatch_C610:
|
|
jmp Main_WriteGameMode_C4C3 ; CPU:$C610 PRG:0610 4C C3 C4
|
|
; Routine: Main_WriteStageCounter_C613
|
|
; Global: Reachable code entry at CPU $C613 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteStageCounter_C613:
|
|
jsr WaitForNmiFrameHandoff ; CPU:$C613 PRG:0613 20 FB CB
|
|
lda #$01 ; CPU:$C616 PRG:0616 A9 01
|
|
sta $39 ; CPU:$C618 PRG:0618 85 39
|
|
lda ControllerState1 ; CPU:$C61A PRG:061A A5 12
|
|
and #$10 ; CPU:$C61C PRG:061C 29 10
|
|
beq Main_ReturnToCaller_C643 ; CPU:$C61E PRG:061E F0 23
|
|
lda $59 ; CPU:$C620 PRG:0620 A5 59
|
|
bne Main_Dispatch_C610 ; CPU:$C622 PRG:0622 D0 EC
|
|
lda #$01 ; CPU:$C624 PRG:0624 A9 01
|
|
sta $B2 ; CPU:$C626 PRG:0626 85 B2
|
|
lda #$06 ; CPU:$C628 PRG:0628 A9 06
|
|
sta $DF ; CPU:$C62A PRG:062A 85 DF
|
|
jsr WaitForFrameBoundary ; CPU:$C62C PRG:062C 20 07 C3
|
|
; Routine: Main_WriteSoundCommandState_C62F
|
|
; Global: Reachable code entry at CPU $C62F traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteSoundCommandState_C62F:
|
|
lda ControllerState1 ; CPU:$C62F PRG:062F A5 12
|
|
and #$10 ; CPU:$C631 PRG:0631 29 10
|
|
beq Main_WriteSoundCommandState_C62F ; CPU:$C633 PRG:0633 F0 FA
|
|
lda #$06 ; CPU:$C635 PRG:0635 A9 06
|
|
sta $DF ; CPU:$C637 PRG:0637 85 DF
|
|
lda #$00 ; CPU:$C639 PRG:0639 A9 00
|
|
sta $B2 ; CPU:$C63B PRG:063B 85 B2
|
|
jsr WaitForFrameBoundary ; CPU:$C63D PRG:063D 20 07 C3
|
|
jmp WaitForNmiFrameHandoff ; CPU:$C640 PRG:0640 4C FB CB
|
|
; Routine: Main_ReturnToCaller_C643
|
|
; Global: Reachable code entry at CPU $C643 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReturnToCaller_C643:
|
|
rts ; CPU:$C643 PRG:0643 60
|
|
; Routine: Main_ReadZp33_C644
|
|
; Global: Reachable code entry at CPU $C644 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReadZp33_C644:
|
|
lda $33 ; CPU:$C644 PRG:0644 A5 33
|
|
and #$3F ; CPU:$C646 PRG:0646 29 3F
|
|
bne Main_ReturnToCaller_C65E ; CPU:$C648 PRG:0648 D0 14
|
|
lda $93 ; CPU:$C64A PRG:064A A5 93
|
|
cmp #$FF ; CPU:$C64C PRG:064C C9 FF
|
|
beq Main_ReturnToCaller_C65E ; CPU:$C64E PRG:064E F0 0E
|
|
dec $93 ; CPU:$C650 PRG:0650 C6 93
|
|
bne Main_ReturnToCaller_C65E ; CPU:$C652 PRG:0652 D0 0A
|
|
jsr Gameplay_HandleControl_CBD7 ; CPU:$C654 PRG:0654 20 D7 CB
|
|
lda #$08 ; CPU:$C657 PRG:0657 A9 08
|
|
sta $7E ; CPU:$C659 PRG:0659 85 7E
|
|
jmp Gameplay_HandleControl_C8ED ; CPU:$C65B PRG:065B 4C ED C8
|
|
; Routine: Main_ReturnToCaller_C65E
|
|
; Global: Reachable code entry at CPU $C65E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReturnToCaller_C65E:
|
|
rts ; CPU:$C65E PRG:065E 60
|
|
; Routine: Main_ReadZp33_C65F
|
|
; Global: Reachable code entry at CPU $C65F traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReadZp33_C65F:
|
|
lda $33 ; CPU:$C65F PRG:065F A5 33
|
|
and #$3F ; CPU:$C661 PRG:0661 29 3F
|
|
bne Main_ReturnToCaller_C65E ; CPU:$C663 PRG:0663 D0 F9
|
|
lda $93 ; CPU:$C665 PRG:0665 A5 93
|
|
beq Main_ReturnToCaller_C65E ; CPU:$C667 PRG:0667 F0 F5
|
|
dec $93 ; CPU:$C669 PRG:0669 C6 93
|
|
rts ; CPU:$C66B PRG:066B 60
|
|
; Routine: Main_HandleControl_C66C
|
|
; Global: Reachable code entry at CPU $C66C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_HandleControl_C66C:
|
|
ldx #$4F ; CPU:$C66C PRG:066C A2 4F
|
|
; Routine: Main_ReadRam03E6_C66E
|
|
; Global: Reachable code entry at CPU $C66E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReadRam03E6_C66E:
|
|
lda $03E6,x ; CPU:$C66E PRG:066E BD E6 03
|
|
beq Main_Dispatch_C6CD ; CPU:$C671 PRG:0671 F0 5A
|
|
bpl Main_ReadRam0436_C688 ; CPU:$C673 PRG:0673 10 13
|
|
and #$7F ; CPU:$C675 PRG:0675 29 7F
|
|
tay ; CPU:$C677 PRG:0677 A8
|
|
lda $0436,x ; CPU:$C678 PRG:0678 BD 36 04
|
|
sta $1F ; CPU:$C67B PRG:067B 85 1F
|
|
lda $0486,x ; CPU:$C67D PRG:067D BD 86 04
|
|
sta $20 ; CPU:$C680 PRG:0680 85 20
|
|
lda $C75D,y ; CPU:$C682 PRG:0682 B9 5D C7
|
|
jmp Main_ReadZp5C_C6DA ; CPU:$C685 PRG:0685 4C DA C6
|
|
; Routine: Main_ReadRam0436_C688
|
|
; Global: Reachable code entry at CPU $C688 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReadRam0436_C688:
|
|
lda $0436,x ; CPU:$C688 PRG:0688 BD 36 04
|
|
sta $1F ; CPU:$C68B PRG:068B 85 1F
|
|
lda $0486,x ; CPU:$C68D PRG:068D BD 86 04
|
|
sta $20 ; CPU:$C690 PRG:0690 85 20
|
|
lda $0526,x ; CPU:$C692 PRG:0692 BD 26 05
|
|
and #$78 ; CPU:$C695 PRG:0695 29 78
|
|
beq Main_Dispatch_C6CD ; CPU:$C697 PRG:0697 F0 34
|
|
lda $0526,x ; CPU:$C699 PRG:0699 BD 26 05
|
|
bpl Main_WriteZp32_C6B2 ; CPU:$C69C PRG:069C 10 14
|
|
and #$07 ; CPU:$C69E PRG:069E 29 07
|
|
sta $32 ; CPU:$C6A0 PRG:06A0 85 32
|
|
lda $0526,x ; CPU:$C6A2 PRG:06A2 BD 26 05
|
|
lsr a ; CPU:$C6A5 PRG:06A5 4A
|
|
and #$3C ; CPU:$C6A6 PRG:06A6 29 3C
|
|
clc ; CPU:$C6A8 PRG:06A8 18
|
|
adc $32 ; CPU:$C6A9 PRG:06A9 65 32
|
|
tay ; CPU:$C6AB PRG:06AB A8
|
|
lda $C778,y ; CPU:$C6AC PRG:06AC B9 78 C7
|
|
jmp Main_ReadZp5C_C6DA ; CPU:$C6AF PRG:06AF 4C DA C6
|
|
; Routine: Main_WriteZp32_C6B2
|
|
; Global: Reachable code entry at CPU $C6B2 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_WriteZp32_C6B2:
|
|
and #$07 ; CPU:$C6B2 PRG:06B2 29 07
|
|
beq Main_ReadRam0526_C6D0 ; CPU:$C6B4 PRG:06B4 F0 1A
|
|
and #$01 ; CPU:$C6B6 PRG:06B6 29 01
|
|
eor #$01 ; CPU:$C6B8 PRG:06B8 49 01
|
|
sta $32 ; CPU:$C6BA PRG:06BA 85 32
|
|
lda $0526,x ; CPU:$C6BC PRG:06BC BD 26 05
|
|
lsr a ; CPU:$C6BF PRG:06BF 4A
|
|
lsr a ; CPU:$C6C0 PRG:06C0 4A
|
|
and #$1E ; CPU:$C6C1 PRG:06C1 29 1E
|
|
clc ; CPU:$C6C3 PRG:06C3 18
|
|
adc $32 ; CPU:$C6C4 PRG:06C4 65 32
|
|
clc ; CPU:$C6C6 PRG:06C6 18
|
|
adc #$07 ; CPU:$C6C7 PRG:06C7 69 07
|
|
tay ; CPU:$C6C9 PRG:06C9 A8
|
|
jmp Main_ReadRamC764_C6D6 ; CPU:$C6CA PRG:06CA 4C D6 C6
|
|
; Routine: Main_Dispatch_C6CD
|
|
; Global: Reachable code entry at CPU $C6CD traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_Dispatch_C6CD:
|
|
jmp Main_RetreatIndexX_C756 ; CPU:$C6CD PRG:06CD 4C 56 C7
|
|
; Routine: Main_ReadRam0526_C6D0
|
|
; Global: Reachable code entry at CPU $C6D0 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReadRam0526_C6D0:
|
|
lda $0526,x ; CPU:$C6D0 PRG:06D0 BD 26 05
|
|
lsr a ; CPU:$C6D3 PRG:06D3 4A
|
|
lsr a ; CPU:$C6D4 PRG:06D4 4A
|
|
lsr a ; CPU:$C6D5 PRG:06D5 4A
|
|
; Routine: Main_ReadRamC764_C6D6
|
|
; Global: Reachable code entry at CPU $C6D6 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReadRamC764_C6D6:
|
|
tay ; CPU:$C6D6 PRG:06D6 A8
|
|
lda $C764,y ; CPU:$C6D7 PRG:06D7 B9 64 C7
|
|
; Routine: Main_ReadZp5C_C6DA
|
|
; Global: Reachable code entry at CPU $C6DA traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReadZp5C_C6DA:
|
|
and #$FF ; CPU:$C6DA PRG:06DA 29 FF
|
|
beq Main_CallHelper_C753 ; CPU:$C6DC PRG:06DC F0 75
|
|
jsr Stage_WriteObjectWorkX_D8FC ; CPU:$C6DE PRG:06DE 20 FC D8
|
|
lda $5C ; CPU:$C6E1 PRG:06E1 A5 5C
|
|
bne Main_HandleControl_C705 ; CPU:$C6E3 PRG:06E3 D0 20
|
|
lda $79 ; CPU:$C6E5 PRG:06E5 A5 79
|
|
bne Main_HandleControl_C705 ; CPU:$C6E7 PRG:06E7 D0 1C
|
|
lda $7A ; CPU:$C6E9 PRG:06E9 A5 7A
|
|
bne Main_HandleControl_C705 ; CPU:$C6EB PRG:06EB D0 18
|
|
lda $28 ; CPU:$C6ED PRG:06ED A5 28
|
|
cmp $1F ; CPU:$C6EF PRG:06EF C5 1F
|
|
bne Main_HandleControl_C705 ; CPU:$C6F1 PRG:06F1 D0 12
|
|
lda $2A ; CPU:$C6F3 PRG:06F3 A5 2A
|
|
cmp $20 ; CPU:$C6F5 PRG:06F5 C5 20
|
|
bne Main_HandleControl_C705 ; CPU:$C6F7 PRG:06F7 D0 0C
|
|
lda #$05 ; CPU:$C6F9 PRG:06F9 A9 05
|
|
sta $DF ; CPU:$C6FB PRG:06FB 85 DF
|
|
lda #$01 ; CPU:$C6FD PRG:06FD A9 01
|
|
sta $5C ; CPU:$C6FF PRG:06FF 85 5C
|
|
lda #$0C ; CPU:$C701 PRG:0701 A9 0C
|
|
sta $2C ; CPU:$C703 PRG:0703 85 2C
|
|
; Routine: Main_HandleControl_C705
|
|
; Global: Reachable code entry at CPU $C705 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_HandleControl_C705:
|
|
ldy #$09 ; CPU:$C705 PRG:0705 A0 09
|
|
; Routine: Main_ReadRam0576_C707
|
|
; Global: Reachable code entry at CPU $C707 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReadRam0576_C707:
|
|
lda $0576,y ; CPU:$C707 PRG:0707 B9 76 05
|
|
beq Main_RetreatIndexY_C74E ; CPU:$C70A PRG:070A F0 42
|
|
cmp #$09 ; CPU:$C70C PRG:070C C9 09
|
|
bcs Main_RetreatIndexY_C74E ; CPU:$C70E PRG:070E B0 3E
|
|
lda $0580,y ; CPU:$C710 PRG:0710 B9 80 05
|
|
cmp $1F ; CPU:$C713 PRG:0713 C5 1F
|
|
bne Main_RetreatIndexY_C74E ; CPU:$C715 PRG:0715 D0 37
|
|
lda $0594,y ; CPU:$C717 PRG:0717 B9 94 05
|
|
cmp $20 ; CPU:$C71A PRG:071A C5 20
|
|
bne Main_RetreatIndexY_C74E ; CPU:$C71C PRG:071C D0 30
|
|
inc $9E ; CPU:$C71E PRG:071E E6 9E
|
|
lda #$00 ; CPU:$C720 PRG:0720 A9 00
|
|
sta $A0 ; CPU:$C722 PRG:0722 85 A0
|
|
sta $A1 ; CPU:$C724 PRG:0724 85 A1
|
|
sta $A2 ; CPU:$C726 PRG:0726 85 A2
|
|
sta $A3 ; CPU:$C728 PRG:0728 85 A3
|
|
lda #$64 ; CPU:$C72A PRG:072A A9 64
|
|
sta $05C6,y ; CPU:$C72C PRG:072C 99 C6 05
|
|
lda $0576,y ; CPU:$C72F PRG:072F B9 76 05
|
|
sta $05D0,y ; CPU:$C732 PRG:0732 99 D0 05
|
|
lda $6A ; CPU:$C735 PRG:0735 A5 6A
|
|
sta $05DA,y ; CPU:$C737 PRG:0737 99 DA 05
|
|
inc $6A ; CPU:$C73A PRG:073A E6 6A
|
|
lda #$09 ; CPU:$C73C PRG:073C A9 09
|
|
sta $0576,y ; CPU:$C73E PRG:073E 99 76 05
|
|
lda $05A8,y ; CPU:$C741 PRG:0741 B9 A8 05
|
|
lsr a ; CPU:$C744 PRG:0744 4A
|
|
lsr a ; CPU:$C745 PRG:0745 4A
|
|
and #$07 ; CPU:$C746 PRG:0746 29 07
|
|
clc ; CPU:$C748 PRG:0748 18
|
|
adc #$20 ; CPU:$C749 PRG:0749 69 20
|
|
sta $05A8,y ; CPU:$C74B PRG:074B 99 A8 05
|
|
; Routine: Main_RetreatIndexY_C74E
|
|
; Global: Reachable code entry at CPU $C74E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_RetreatIndexY_C74E:
|
|
dey ; CPU:$C74E PRG:074E 88
|
|
bpl Main_ReadRam0576_C707 ; CPU:$C74F PRG:074F 10 B6
|
|
bmi Main_RetreatIndexX_C756 ; CPU:$C751 PRG:0751 30 03
|
|
; Routine: Main_CallHelper_C753
|
|
; Global: Reachable code entry at CPU $C753 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_CallHelper_C753:
|
|
jsr Stage_WriteObjectWorkX_D8FC ; CPU:$C753 PRG:0753 20 FC D8
|
|
; Routine: Main_RetreatIndexX_C756
|
|
; Global: Reachable code entry at CPU $C756 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_RetreatIndexX_C756:
|
|
dex ; CPU:$C756 PRG:0756 CA
|
|
bmi Main_ReturnToCaller_C75C ; CPU:$C757 PRG:0757 30 03
|
|
jmp Main_ReadRam03E6_C66E ; CPU:$C759 PRG:0759 4C 6E C6
|
|
; Routine: Main_ReturnToCaller_C75C
|
|
; Global: Reachable code entry at CPU $C75C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Main_ReturnToCaller_C75C:
|
|
rts ; CPU:$C75C PRG:075C 60
|
|
|
|
; Data region: CPU $C75D-$C79C; unreachable by direct recursive trace.
|
|
MainStateDispatchTable:
|
|
.byte $27, $03, $04, $05, $06, $07, $00, $00, $0B, $0C, $0D, $0E, $0D, $0C, $0B, $00 ; CPU:$C75D PRG:075D 27 03 04 05 06 07 00 00 0B 0C 0D 0E 0D 0C 0B 00
|
|
.byte $0F, $10, $11, $12, $13, $14, $15, $16, $13, $14, $11, $12, $0F, $10, $00, $00 ; CPU:$C76D PRG:076D 0F 10 11 12 13 14 15 16 13 14 11 12 0F 10 00 00
|
|
.byte $17, $18, $19, $1A, $1B, $1C, $1D, $1E, $1F, $20, $21, $22, $23, $24, $25, $26 ; CPU:$C77D PRG:077D 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26
|
|
.byte $1F, $20, $21, $22, $1B, $1C, $1D, $1E, $17, $18, $19, $1A, $00, $00, $00, $00 ; CPU:$C78D PRG:078D 1F 20 21 22 1B 1C 1D 1E 17 18 19 1A 00 00 00 00
|
|
; Routine: GameplayUpdate
|
|
; Global: Reachable code entry at CPU $C79D traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
GameplayUpdate:
|
|
ldx #$4F ; CPU:$C79D PRG:079D A2 4F
|
|
; Routine: Gameplay_ReadRam03E6_C79F
|
|
; Global: Reachable code entry at CPU $C79F traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadRam03E6_C79F:
|
|
lda $03E6,x ; CPU:$C79F PRG:079F BD E6 03
|
|
bne Gameplay_ReadRam0486_C7A7 ; CPU:$C7A2 PRG:07A2 D0 03
|
|
; Routine: Gameplay_Dispatch_C7A4
|
|
; Global: Reachable code entry at CPU $C7A4 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_Dispatch_C7A4:
|
|
jmp Gameplay_RetreatIndexX_C8A6 ; CPU:$C7A4 PRG:07A4 4C A6 C8
|
|
; Routine: Gameplay_ReadRam0486_C7A7
|
|
; Global: Reachable code entry at CPU $C7A7 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadRam0486_C7A7:
|
|
pha ; CPU:$C7A7 PRG:07A7 48
|
|
ldy $0486,x ; CPU:$C7A8 PRG:07A8 BC 86 04
|
|
sty $20 ; CPU:$C7AB PRG:07AB 84 20
|
|
jsr Gameplay_ReadRamE2A3_CBEB ; CPU:$C7AD PRG:07AD 20 EB CB
|
|
ldy $0436,x ; CPU:$C7B0 PRG:07B0 BC 36 04
|
|
sty $1F ; CPU:$C7B3 PRG:07B3 84 1F
|
|
pla ; CPU:$C7B5 PRG:07B5 68
|
|
bpl Gameplay_ReadTransferPointer_C7CB ; CPU:$C7B6 PRG:07B6 10 13
|
|
inc $03E6,x ; CPU:$C7B8 PRG:07B8 FE E6 03
|
|
lda $03E6,x ; CPU:$C7BB PRG:07BB BD E6 03
|
|
cmp #$87 ; CPU:$C7BE PRG:07BE C9 87
|
|
bne Gameplay_Dispatch_C7A4 ; CPU:$C7C0 PRG:07C0 D0 E2
|
|
lda #$00 ; CPU:$C7C2 PRG:07C2 A9 00
|
|
sta $03E6,x ; CPU:$C7C4 PRG:07C4 9D E6 03
|
|
sta ($34),y ; CPU:$C7C7 PRG:07C7 91 34
|
|
beq Gameplay_Dispatch_C7A4 ; CPU:$C7C9 PRG:07C9 F0 D9
|
|
; Routine: Gameplay_ReadTransferPointer_C7CB
|
|
; Global: Reachable code entry at CPU $C7CB traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadTransferPointer_C7CB:
|
|
lda ($34),y ; CPU:$C7CB PRG:07CB B1 34
|
|
tay ; CPU:$C7CD PRG:07CD A8
|
|
beq Gameplay_ReadRam0526_C838 ; CPU:$C7CE PRG:07CE F0 68
|
|
cpy #$02 ; CPU:$C7D0 PRG:07D0 C0 02
|
|
bne Gameplay_ReadRam04D6_C7DE ; CPU:$C7D2 PRG:07D2 D0 0A
|
|
inc $A4 ; CPU:$C7D4 PRG:07D4 E6 A4
|
|
lda #$80 ; CPU:$C7D6 PRG:07D6 A9 80
|
|
sta $03E6,x ; CPU:$C7D8 PRG:07D8 9D E6 03
|
|
jmp Gameplay_RetreatIndexX_C8A6 ; CPU:$C7DB PRG:07DB 4C A6 C8
|
|
; Routine: Gameplay_ReadRam04D6_C7DE
|
|
; Global: Reachable code entry at CPU $C7DE traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadRam04D6_C7DE:
|
|
cpy #$03 ; CPU:$C7DE PRG:07DE C0 03
|
|
bne Gameplay_ReadWorkIndex_C7EE ; CPU:$C7E0 PRG:07E0 D0 0C
|
|
lda $04D6,x ; CPU:$C7E2 PRG:07E2 BD D6 04
|
|
ora #$10 ; CPU:$C7E5 PRG:07E5 09 10
|
|
ldy $1F ; CPU:$C7E7 PRG:07E7 A4 1F
|
|
sta ($34),y ; CPU:$C7E9 PRG:07E9 91 34
|
|
jmp Gameplay_WriteRam03E6_C830 ; CPU:$C7EB PRG:07EB 4C 30 C8
|
|
; Routine: Gameplay_ReadWorkIndex_C7EE
|
|
; Global: Reachable code entry at CPU $C7EE traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadWorkIndex_C7EE:
|
|
cpy #$04 ; CPU:$C7EE PRG:07EE C0 04
|
|
bne Gameplay_ReadWorkIndex_C800 ; CPU:$C7F0 PRG:07F0 D0 0E
|
|
ldy $1F ; CPU:$C7F2 PRG:07F2 A4 1F
|
|
lda #$08 ; CPU:$C7F4 PRG:07F4 A9 08
|
|
sta ($34),y ; CPU:$C7F6 PRG:07F6 91 34
|
|
lda #$28 ; CPU:$C7F8 PRG:07F8 A9 28
|
|
jsr Stage_WriteObjectWorkX_D8FC ; CPU:$C7FA PRG:07FA 20 FC D8
|
|
jmp Gameplay_WriteRam03E6_C830 ; CPU:$C7FD PRG:07FD 4C 30 C8
|
|
; Routine: Gameplay_ReadWorkIndex_C800
|
|
; Global: Reachable code entry at CPU $C800 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadWorkIndex_C800:
|
|
cpy #$05 ; CPU:$C800 PRG:0800 C0 05
|
|
bne Gameplay_ReadWorkIndex_C815 ; CPU:$C802 PRG:0802 D0 11
|
|
ldy $1F ; CPU:$C804 PRG:0804 A4 1F
|
|
lda #$06 ; CPU:$C806 PRG:0806 A9 06
|
|
sta ($34),y ; CPU:$C808 PRG:0808 91 34
|
|
lda #$28 ; CPU:$C80A PRG:080A A9 28
|
|
clc ; CPU:$C80C PRG:080C 18
|
|
adc $5B ; CPU:$C80D PRG:080D 65 5B
|
|
jsr Stage_WriteObjectWorkX_D8FC ; CPU:$C80F PRG:080F 20 FC D8
|
|
jmp Gameplay_WriteRam03E6_C830 ; CPU:$C812 PRG:0812 4C 30 C8
|
|
; Routine: Gameplay_ReadWorkIndex_C815
|
|
; Global: Reachable code entry at CPU $C815 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadWorkIndex_C815:
|
|
cpy #$08 ; CPU:$C815 PRG:0815 C0 08
|
|
beq Gameplay_IncrementBonusTimer_C828 ; CPU:$C817 PRG:0817 F0 0F
|
|
cpy #$06 ; CPU:$C819 PRG:0819 C0 06
|
|
bne Gameplay_WriteRam03E6_C830 ; CPU:$C81B PRG:081B D0 13
|
|
ldy $1F ; CPU:$C81D PRG:081D A4 1F
|
|
lda #$00 ; CPU:$C81F PRG:081F A9 00
|
|
sta ($34),y ; CPU:$C821 PRG:0821 91 34
|
|
jsr Stage_WriteObjectWorkX_D8FC ; CPU:$C823 PRG:0823 20 FC D8
|
|
dec $A7 ; CPU:$C826 PRG:0826 C6 A7
|
|
; Routine: Gameplay_IncrementBonusTimer_C828
|
|
; Global: Reachable code entry at CPU $C828 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_IncrementBonusTimer_C828:
|
|
inc $A7 ; CPU:$C828 PRG:0828 E6 A7
|
|
jsr Gameplay_HandleControl_C8AD ; CPU:$C82A PRG:082A 20 AD C8
|
|
jmp Gameplay_WriteRam03E6_C830 ; CPU:$C82D PRG:082D 4C 30 C8
|
|
; Routine: Gameplay_WriteRam03E6_C830
|
|
; Global: Reachable code entry at CPU $C830 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteRam03E6_C830:
|
|
lda #$00 ; CPU:$C830 PRG:0830 A9 00
|
|
sta $03E6,x ; CPU:$C832 PRG:0832 9D E6 03
|
|
; Routine: Gameplay_Dispatch_C835
|
|
; Global: Reachable code entry at CPU $C835 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_Dispatch_C835:
|
|
jmp Gameplay_RetreatIndexX_C8A6 ; CPU:$C835 PRG:0835 4C A6 C8
|
|
; Routine: Gameplay_ReadRam0526_C838
|
|
; Global: Reachable code entry at CPU $C838 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadRam0526_C838:
|
|
lda $0526,x ; CPU:$C838 PRG:0838 BD 26 05
|
|
clc ; CPU:$C83B PRG:083B 18
|
|
adc #$08 ; CPU:$C83C PRG:083C 69 08
|
|
sta $0526,x ; CPU:$C83E PRG:083E 9D 26 05
|
|
and #$7F ; CPU:$C841 PRG:0841 29 7F
|
|
cmp #$48 ; CPU:$C843 PRG:0843 C9 48
|
|
bcs Gameplay_ReadWorkIndex_C7EE ; CPU:$C845 PRG:0845 B0 A7
|
|
lda $04D6,x ; CPU:$C847 PRG:0847 BD D6 04
|
|
sta $36 ; CPU:$C84A PRG:084A 85 36
|
|
and #$07 ; CPU:$C84C PRG:084C 29 07
|
|
beq Gameplay_Dispatch_C835 ; CPU:$C84E PRG:084E F0 E5
|
|
tay ; CPU:$C850 PRG:0850 A8
|
|
lda #$00 ; CPU:$C851 PRG:0851 A9 00
|
|
sta $04D6,x ; CPU:$C853 PRG:0853 9D D6 04
|
|
lda $0436,x ; CPU:$C856 PRG:0856 BD 36 04
|
|
clc ; CPU:$C859 PRG:0859 18
|
|
adc $CA16,y ; CPU:$C85A PRG:085A 79 16 CA
|
|
sta $1F ; CPU:$C85D PRG:085D 85 1F
|
|
lda $0486,x ; CPU:$C85F PRG:085F BD 86 04
|
|
clc ; CPU:$C862 PRG:0862 18
|
|
adc $CA11,y ; CPU:$C863 PRG:0863 79 11 CA
|
|
sta $20 ; CPU:$C866 PRG:0866 85 20
|
|
ldy #$4F ; CPU:$C868 PRG:0868 A0 4F
|
|
jsr Gameplay_ReadRam03E6_CBE5 ; CPU:$C86A PRG:086A 20 E5 CB
|
|
bne Gameplay_RetreatIndexX_C8A6 ; CPU:$C86D PRG:086D D0 37
|
|
lda $1F ; CPU:$C86F PRG:086F A5 1F
|
|
sta $0436,y ; CPU:$C871 PRG:0871 99 36 04
|
|
lda $20 ; CPU:$C874 PRG:0874 A5 20
|
|
sta $0486,y ; CPU:$C876 PRG:0876 99 86 04
|
|
lda #$01 ; CPU:$C879 PRG:0879 A9 01
|
|
sta $03E6,y ; CPU:$C87B PRG:087B 99 E6 03
|
|
lda $36 ; CPU:$C87E PRG:087E A5 36
|
|
and #$07 ; CPU:$C880 PRG:0880 29 07
|
|
sta $0526,y ; CPU:$C882 PRG:0882 99 26 05
|
|
lda $36 ; CPU:$C885 PRG:0885 A5 36
|
|
clc ; CPU:$C887 PRG:0887 18
|
|
adc #$10 ; CPU:$C888 PRG:0888 69 10
|
|
cmp $73 ; CPU:$C88A PRG:088A C5 73
|
|
bcc Gameplay_WriteRam04D6_C89E ; CPU:$C88C PRG:088C 90 10
|
|
lda #$00 ; CPU:$C88E PRG:088E A9 00
|
|
sta $03E6,y ; CPU:$C890 PRG:0890 99 E6 03
|
|
lda $0526,x ; CPU:$C893 PRG:0893 BD 26 05
|
|
ora #$80 ; CPU:$C896 PRG:0896 09 80
|
|
sta $0526,x ; CPU:$C898 PRG:0898 9D 26 05
|
|
jmp Gameplay_WriteRam04D6_C8A1 ; CPU:$C89B PRG:089B 4C A1 C8
|
|
; Routine: Gameplay_WriteRam04D6_C89E
|
|
; Global: Reachable code entry at CPU $C89E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteRam04D6_C89E:
|
|
sta $04D6,y ; CPU:$C89E PRG:089E 99 D6 04
|
|
; Routine: Gameplay_WriteRam04D6_C8A1
|
|
; Global: Reachable code entry at CPU $C8A1 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteRam04D6_C8A1:
|
|
lda #$00 ; CPU:$C8A1 PRG:08A1 A9 00
|
|
sta $04D6,x ; CPU:$C8A3 PRG:08A3 9D D6 04
|
|
; Routine: Gameplay_RetreatIndexX_C8A6
|
|
; Global: Reachable code entry at CPU $C8A6 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_RetreatIndexX_C8A6:
|
|
dex ; CPU:$C8A6 PRG:08A6 CA
|
|
bmi Gameplay_ReturnToCaller_C8AC ; CPU:$C8A7 PRG:08A7 30 03
|
|
jmp Gameplay_ReadRam03E6_C79F ; CPU:$C8A9 PRG:08A9 4C 9F C7
|
|
; Routine: Gameplay_ReturnToCaller_C8AC
|
|
; Global: Reachable code entry at CPU $C8AC traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReturnToCaller_C8AC:
|
|
rts ; CPU:$C8AC PRG:08AC 60
|
|
; Routine: Gameplay_HandleControl_C8AD
|
|
; Global: Reachable code entry at CPU $C8AD traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_HandleControl_C8AD:
|
|
ldy #$09 ; CPU:$C8AD PRG:08AD A0 09
|
|
; Routine: Gameplay_ReadRam0576_C8AF
|
|
; Global: Reachable code entry at CPU $C8AF traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadRam0576_C8AF:
|
|
lda $0576,y ; CPU:$C8AF PRG:08AF B9 76 05
|
|
bne Gameplay_RetreatIndexY_C8E9 ; CPU:$C8B2 PRG:08B2 D0 35
|
|
lda $5B ; CPU:$C8B4 PRG:08B4 A5 5B
|
|
sta $0576,y ; CPU:$C8B6 PRG:08B6 99 76 05
|
|
sta $05A8,y ; CPU:$C8B9 PRG:08B9 99 A8 05
|
|
lda #$08 ; CPU:$C8BC PRG:08BC A9 08
|
|
sta $058A,y ; CPU:$C8BE PRG:08BE 99 8A 05
|
|
sta $059E,y ; CPU:$C8C1 PRG:08C1 99 9E 05
|
|
jsr AdvanceRandomState ; CPU:$C8C4 PRG:08C4 20 70 D6
|
|
and #$03 ; CPU:$C8C7 PRG:08C7 29 03
|
|
clc ; CPU:$C8C9 PRG:08C9 18
|
|
adc #$01 ; CPU:$C8CA PRG:08CA 69 01
|
|
sta $05D0,y ; CPU:$C8CC PRG:08CC 99 D0 05
|
|
lda $1F ; CPU:$C8CF PRG:08CF A5 1F
|
|
sta $0580,y ; CPU:$C8D1 PRG:08D1 99 80 05
|
|
lda $20 ; CPU:$C8D4 PRG:08D4 A5 20
|
|
sta $0594,y ; CPU:$C8D6 PRG:08D6 99 94 05
|
|
lda #$00 ; CPU:$C8D9 PRG:08D9 A9 00
|
|
sta $05DA,y ; CPU:$C8DB PRG:08DB 99 DA 05
|
|
sta $05C6,y ; CPU:$C8DE PRG:08DE 99 C6 05
|
|
sta $05E4,y ; CPU:$C8E1 PRG:08E1 99 E4 05
|
|
lda #$1E ; CPU:$C8E4 PRG:08E4 A9 1E
|
|
sta $05B2,y ; CPU:$C8E6 PRG:08E6 99 B2 05
|
|
; Routine: Gameplay_RetreatIndexY_C8E9
|
|
; Global: Reachable code entry at CPU $C8E9 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_RetreatIndexY_C8E9:
|
|
dey ; CPU:$C8E9 PRG:08E9 88
|
|
bpl Gameplay_ReadRam0576_C8AF ; CPU:$C8EA PRG:08EA 10 C3
|
|
rts ; CPU:$C8EC PRG:08EC 60
|
|
; Routine: Gameplay_HandleControl_C8ED
|
|
; Global: Reachable code entry at CPU $C8ED traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_HandleControl_C8ED:
|
|
ldy #$09 ; CPU:$C8ED PRG:08ED A0 09
|
|
; Routine: Gameplay_ReadRam0576_C8EF
|
|
; Global: Reachable code entry at CPU $C8EF traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadRam0576_C8EF:
|
|
lda $0576,y ; CPU:$C8EF PRG:08EF B9 76 05
|
|
bne Gameplay_RetreatIndexY_C935 ; CPU:$C8F2 PRG:08F2 D0 41
|
|
lda $7E ; CPU:$C8F4 PRG:08F4 A5 7E
|
|
sta $0576,y ; CPU:$C8F6 PRG:08F6 99 76 05
|
|
sec ; CPU:$C8F9 PRG:08F9 38
|
|
sbc #$01 ; CPU:$C8FA PRG:08FA E9 01
|
|
asl a ; CPU:$C8FC PRG:08FC 0A
|
|
asl a ; CPU:$C8FD PRG:08FD 0A
|
|
sta $05A8,y ; CPU:$C8FE PRG:08FE 99 A8 05
|
|
lda #$08 ; CPU:$C901 PRG:0901 A9 08
|
|
sta $058A,y ; CPU:$C903 PRG:0903 99 8A 05
|
|
sta $059E,y ; CPU:$C906 PRG:0906 99 9E 05
|
|
jsr AdvanceRandomState ; CPU:$C909 PRG:0909 20 70 D6
|
|
and #$03 ; CPU:$C90C PRG:090C 29 03
|
|
clc ; CPU:$C90E PRG:090E 18
|
|
adc #$01 ; CPU:$C90F PRG:090F 69 01
|
|
sta $05D0,y ; CPU:$C911 PRG:0911 99 D0 05
|
|
sty $5A ; CPU:$C914 PRG:0914 84 5A
|
|
jsr Gameplay_WriteObjectWorkX_CACF ; CPU:$C916 PRG:0916 20 CF CA
|
|
ldy $5A ; CPU:$C919 PRG:0919 A4 5A
|
|
lda $24 ; CPU:$C91B PRG:091B A5 24
|
|
sta $0580,y ; CPU:$C91D PRG:091D 99 80 05
|
|
lda $25 ; CPU:$C920 PRG:0920 A5 25
|
|
sta $0594,y ; CPU:$C922 PRG:0922 99 94 05
|
|
lda #$00 ; CPU:$C925 PRG:0925 A9 00
|
|
sta $05DA,y ; CPU:$C927 PRG:0927 99 DA 05
|
|
sta $05C6,y ; CPU:$C92A PRG:092A 99 C6 05
|
|
sta $05E4,y ; CPU:$C92D PRG:092D 99 E4 05
|
|
lda #$1E ; CPU:$C930 PRG:0930 A9 1E
|
|
sta $05B2,y ; CPU:$C932 PRG:0932 99 B2 05
|
|
; Routine: Gameplay_RetreatIndexY_C935
|
|
; Global: Reachable code entry at CPU $C935 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_RetreatIndexY_C935:
|
|
dey ; CPU:$C935 PRG:0935 88
|
|
bpl Gameplay_ReadRam0576_C8EF ; CPU:$C936 PRG:0936 10 B7
|
|
rts ; CPU:$C938 PRG:0938 60
|
|
; Routine: Gameplay_HandleControl_C939
|
|
; Global: Reachable code entry at CPU $C939 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_HandleControl_C939:
|
|
ldx #$09 ; CPU:$C939 PRG:0939 A2 09
|
|
; Routine: Gameplay_ReadRam03A0_C93B
|
|
; Global: Reachable code entry at CPU $C93B traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadRam03A0_C93B:
|
|
lda $03A0,x ; CPU:$C93B PRG:093B BD A0 03
|
|
beq Gameplay_RetreatIndexX_C966 ; CPU:$C93E PRG:093E F0 26
|
|
ldy $03B4,x ; CPU:$C940 PRG:0940 BC B4 03
|
|
lda $E2A3,y ; CPU:$C943 PRG:0943 B9 A3 E2
|
|
sta $34 ; CPU:$C946 PRG:0946 85 34
|
|
lda $E2B0,y ; CPU:$C948 PRG:0948 B9 B0 E2
|
|
sta $35 ; CPU:$C94B PRG:094B 85 35
|
|
sty $20 ; CPU:$C94D PRG:094D 84 20
|
|
ldy $03AA,x ; CPU:$C94F PRG:094F BC AA 03
|
|
sty $1F ; CPU:$C952 PRG:0952 84 1F
|
|
lda #$00 ; CPU:$C954 PRG:0954 A9 00
|
|
jsr Gameplay_WriteZp2F_C9B6 ; CPU:$C956 PRG:0956 20 B6 C9
|
|
jsr Gameplay_WriteDisplayMode_CBF6 ; CPU:$C959 PRG:0959 20 F6 CB
|
|
lda #$00 ; CPU:$C95C PRG:095C A9 00
|
|
sta ($34),y ; CPU:$C95E PRG:095E 91 34
|
|
lda #$00 ; CPU:$C960 PRG:0960 A9 00
|
|
sta $03A0,x ; CPU:$C962 PRG:0962 9D A0 03
|
|
rts ; CPU:$C965 PRG:0965 60
|
|
; Routine: Gameplay_RetreatIndexX_C966
|
|
; Global: Reachable code entry at CPU $C966 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_RetreatIndexX_C966:
|
|
dex ; CPU:$C966 PRG:0966 CA
|
|
bpl Gameplay_ReadRam03A0_C93B ; CPU:$C967 PRG:0967 10 D2
|
|
rts ; CPU:$C969 PRG:0969 60
|
|
; Routine: Gameplay_HandleControl_C96A
|
|
; Global: Reachable code entry at CPU $C96A traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_HandleControl_C96A:
|
|
ldx #$09 ; CPU:$C96A PRG:096A A2 09
|
|
; Routine: Gameplay_ReadRam03A0_C96C
|
|
; Global: Reachable code entry at CPU $C96C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadRam03A0_C96C:
|
|
lda $03A0,x ; CPU:$C96C PRG:096C BD A0 03
|
|
beq Gameplay_RetreatIndexX_C9B2 ; CPU:$C96F PRG:096F F0 41
|
|
ldy $03B4,x ; CPU:$C971 PRG:0971 BC B4 03
|
|
lda $E2A3,y ; CPU:$C974 PRG:0974 B9 A3 E2
|
|
sta $34 ; CPU:$C977 PRG:0977 85 34
|
|
lda $E2B0,y ; CPU:$C979 PRG:0979 B9 B0 E2
|
|
sta $35 ; CPU:$C97C PRG:097C 85 35
|
|
sty $20 ; CPU:$C97E PRG:097E 84 20
|
|
ldy $03AA,x ; CPU:$C980 PRG:0980 BC AA 03
|
|
sty $1F ; CPU:$C983 PRG:0983 84 1F
|
|
lda ($34),y ; CPU:$C985 PRG:0985 B1 34
|
|
cmp #$03 ; CPU:$C987 PRG:0987 C9 03
|
|
bne Gameplay_ReadFlamePass_C999 ; CPU:$C989 PRG:0989 D0 0E
|
|
inc $03D2,x ; CPU:$C98B PRG:098B FE D2 03
|
|
lda $77 ; CPU:$C98E PRG:098E A5 77
|
|
bne Gameplay_RetreatIndexX_C9B2 ; CPU:$C990 PRG:0990 D0 20
|
|
dec $03BE,x ; CPU:$C992 PRG:0992 DE BE 03
|
|
bne Gameplay_RetreatIndexX_C9B2 ; CPU:$C995 PRG:0995 D0 1B
|
|
lda #$00 ; CPU:$C997 PRG:0997 A9 00
|
|
; Routine: Gameplay_ReadFlamePass_C999
|
|
; Global: Reachable code entry at CPU $C999 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadFlamePass_C999:
|
|
and #$07 ; CPU:$C999 PRG:0999 29 07
|
|
jsr Gameplay_WriteZp2F_C9B6 ; CPU:$C99B PRG:099B 20 B6 C9
|
|
lda $A5 ; CPU:$C99E PRG:099E A5 A5
|
|
cmp #$FF ; CPU:$C9A0 PRG:09A0 C9 FF
|
|
beq Gameplay_WriteTransferPointer_C9A6 ; CPU:$C9A2 PRG:09A2 F0 02
|
|
inc $A5 ; CPU:$C9A4 PRG:09A4 E6 A5
|
|
; Routine: Gameplay_WriteTransferPointer_C9A6
|
|
; Global: Reachable code entry at CPU $C9A6 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteTransferPointer_C9A6:
|
|
jsr Gameplay_WriteDisplayMode_CBF6 ; CPU:$C9A6 PRG:09A6 20 F6 CB
|
|
lda #$00 ; CPU:$C9A9 PRG:09A9 A9 00
|
|
sta ($34),y ; CPU:$C9AB PRG:09AB 91 34
|
|
lda #$00 ; CPU:$C9AD PRG:09AD A9 00
|
|
sta $03A0,x ; CPU:$C9AF PRG:09AF 9D A0 03
|
|
; Routine: Gameplay_RetreatIndexX_C9B2
|
|
; Global: Reachable code entry at CPU $C9B2 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_RetreatIndexX_C9B2:
|
|
dex ; CPU:$C9B2 PRG:09B2 CA
|
|
bpl Gameplay_ReadRam03A0_C96C ; CPU:$C9B3 PRG:09B3 10 B7
|
|
; Routine: Gameplay_ReturnToCaller_C9B5
|
|
; Global: Reachable code entry at CPU $C9B5 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReturnToCaller_C9B5:
|
|
rts ; CPU:$C9B5 PRG:09B5 60
|
|
; Routine: Gameplay_WriteZp2F_C9B6
|
|
; Global: Reachable code entry at CPU $C9B6 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteZp2F_C9B6:
|
|
stx $2F ; CPU:$C9B6 PRG:09B6 86 2F
|
|
sty $30 ; CPU:$C9B8 PRG:09B8 84 30
|
|
tay ; CPU:$C9BA PRG:09BA A8
|
|
lda $C9DE,y ; CPU:$C9BB PRG:09BB B9 DE C9
|
|
sta $2E ; CPU:$C9BE PRG:09BE 85 2E
|
|
lda #$01 ; CPU:$C9C0 PRG:09C0 A9 01
|
|
jsr Gameplay_TestZp2E_C9E3 ; CPU:$C9C2 PRG:09C2 20 E3 C9
|
|
lda #$02 ; CPU:$C9C5 PRG:09C5 A9 02
|
|
jsr Gameplay_TestZp2E_C9E3 ; CPU:$C9C7 PRG:09C7 20 E3 C9
|
|
lda #$03 ; CPU:$C9CA PRG:09CA A9 03
|
|
jsr Gameplay_TestZp2E_C9E3 ; CPU:$C9CC PRG:09CC 20 E3 C9
|
|
lda #$04 ; CPU:$C9CF PRG:09CF A9 04
|
|
jsr Gameplay_TestZp2E_C9E3 ; CPU:$C9D1 PRG:09D1 20 E3 C9
|
|
lda #$00 ; CPU:$C9D4 PRG:09D4 A9 00
|
|
jsr Gameplay_TestZp2E_C9E3 ; CPU:$C9D6 PRG:09D6 20 E3 C9
|
|
ldx $2F ; CPU:$C9D9 PRG:09D9 A6 2F
|
|
ldy $30 ; CPU:$C9DB PRG:09DB A4 30
|
|
rts ; CPU:$C9DD PRG:09DD 60
|
|
|
|
; Data region: CPU $C9DE-$C9E2; unreachable by direct recursive trace.
|
|
GameplayDirectionDeltaTable:
|
|
.byte $FF, $03, $04, $01, $02 ; CPU:$C9DE PRG:09DE FF 03 04 01 02
|
|
; Routine: Gameplay_TestZp2E_C9E3
|
|
; Global: Reachable code entry at CPU $C9E3 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_TestZp2E_C9E3:
|
|
cmp $2E ; CPU:$C9E3 PRG:09E3 C5 2E
|
|
beq Gameplay_ReturnToCaller_C9B5 ; CPU:$C9E5 PRG:09E5 F0 CE
|
|
sta $31 ; CPU:$C9E7 PRG:09E7 85 31
|
|
tax ; CPU:$C9E9 PRG:09E9 AA
|
|
ldy #$4F ; CPU:$C9EA PRG:09EA A0 4F
|
|
jsr Gameplay_ReadRam03E6_CBE5 ; CPU:$C9EC PRG:09EC 20 E5 CB
|
|
bmi Gameplay_ReturnToCaller_CA10 ; CPU:$C9EF PRG:09EF 30 1F
|
|
lda $20 ; CPU:$C9F1 PRG:09F1 A5 20
|
|
clc ; CPU:$C9F3 PRG:09F3 18
|
|
adc $CA11,x ; CPU:$C9F4 PRG:09F4 7D 11 CA
|
|
sta $0486,y ; CPU:$C9F7 PRG:09F7 99 86 04
|
|
lda $1F ; CPU:$C9FA PRG:09FA A5 1F
|
|
clc ; CPU:$C9FC PRG:09FC 18
|
|
adc $CA16,x ; CPU:$C9FD PRG:09FD 7D 16 CA
|
|
sta $0436,y ; CPU:$CA00 PRG:0A00 99 36 04
|
|
lda $31 ; CPU:$CA03 PRG:0A03 A5 31
|
|
sta $04D6,y ; CPU:$CA05 PRG:0A05 99 D6 04
|
|
sta $0526,y ; CPU:$CA08 PRG:0A08 99 26 05
|
|
lda #$01 ; CPU:$CA0B PRG:0A0B A9 01
|
|
sta $03E6,y ; CPU:$CA0D PRG:0A0D 99 E6 03
|
|
; Routine: Gameplay_ReturnToCaller_CA10
|
|
; Global: Reachable code entry at CPU $CA10 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReturnToCaller_CA10:
|
|
rts ; CPU:$CA10 PRG:0A10 60
|
|
|
|
; Data region: CPU $CA11-$CA1A; unreachable by direct recursive trace.
|
|
GameplayObjectClassTable:
|
|
.byte $00, $00, $FF, $00, $01, $00, $01, $00, $FF, $00 ; CPU:$CA11 PRG:0A11 00 00 FF 00 01 00 01 00 FF 00
|
|
; Routine: Gameplay_HandleControl_CA1B
|
|
; Global: Reachable code entry at CPU $CA1B traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_HandleControl_CA1B:
|
|
ldx #$09 ; CPU:$CA1B PRG:0A1B A2 09
|
|
; Routine: Gameplay_ReadRam03A0_CA1D
|
|
; Global: Reachable code entry at CPU $CA1D traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadRam03A0_CA1D:
|
|
lda $03A0,x ; CPU:$CA1D PRG:0A1D BD A0 03
|
|
beq Gameplay_RetreatIndexX_CA43 ; CPU:$CA20 PRG:0A20 F0 21
|
|
lda $03AA,x ; CPU:$CA22 PRG:0A22 BD AA 03
|
|
sta $1F ; CPU:$CA25 PRG:0A25 85 1F
|
|
lda $03B4,x ; CPU:$CA27 PRG:0A27 BD B4 03
|
|
sta $20 ; CPU:$CA2A PRG:0A2A 85 20
|
|
lda $03D2,x ; CPU:$CA2C PRG:0A2C BD D2 03
|
|
and #$0F ; CPU:$CA2F PRG:0A2F 29 0F
|
|
bne Gameplay_RetreatIndexX_CA43 ; CPU:$CA31 PRG:0A31 D0 10
|
|
lda $03D2,x ; CPU:$CA33 PRG:0A33 BD D2 03
|
|
lsr a ; CPU:$CA36 PRG:0A36 4A
|
|
lsr a ; CPU:$CA37 PRG:0A37 4A
|
|
lsr a ; CPU:$CA38 PRG:0A38 4A
|
|
lsr a ; CPU:$CA39 PRG:0A39 4A
|
|
and #$03 ; CPU:$CA3A PRG:0A3A 29 03
|
|
tay ; CPU:$CA3C PRG:0A3C A8
|
|
lda $CA47,y ; CPU:$CA3D PRG:0A3D B9 47 CA
|
|
jsr Stage_WriteObjectWorkX_D8FC ; CPU:$CA40 PRG:0A40 20 FC D8
|
|
; Routine: Gameplay_RetreatIndexX_CA43
|
|
; Global: Reachable code entry at CPU $CA43 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_RetreatIndexX_CA43:
|
|
dex ; CPU:$CA43 PRG:0A43 CA
|
|
bpl Gameplay_ReadRam03A0_CA1D ; CPU:$CA44 PRG:0A44 10 D7
|
|
rts ; CPU:$CA46 PRG:0A46 60
|
|
|
|
; Data region: CPU $CA47-$CA4A; unreachable by direct recursive trace.
|
|
GameplayObjectAttributeTable:
|
|
.byte $09, $0A, $09, $08 ; CPU:$CA47 PRG:0A47 09 0A 09 08
|
|
; Routine: Gameplay_WriteTransferPointer_CA4B
|
|
; Global: Reachable code entry at CPU $CA4B traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteTransferPointer_CA4B:
|
|
jsr Gameplay_WriteTransferPointer_CA72 ; CPU:$CA4B PRG:0A4B 20 72 CA
|
|
jsr Gameplay_WriteObjectWorkX_CACF ; CPU:$CA4E PRG:0A4E 20 CF CA
|
|
lda #$04 ; CPU:$CA51 PRG:0A51 A9 04
|
|
sta ($34),y ; CPU:$CA53 PRG:0A53 91 34
|
|
jsr Gameplay_WriteObjectWorkX_CACF ; CPU:$CA55 PRG:0A55 20 CF CA
|
|
lda #$05 ; CPU:$CA58 PRG:0A58 A9 05
|
|
sta ($34),y ; CPU:$CA5A PRG:0A5A 91 34
|
|
lda #$32 ; CPU:$CA5C PRG:0A5C A9 32
|
|
clc ; CPU:$CA5E PRG:0A5E 18
|
|
adc $58 ; CPU:$CA5F PRG:0A5F 65 58
|
|
clc ; CPU:$CA61 PRG:0A61 18
|
|
adc $58 ; CPU:$CA62 PRG:0A62 65 58
|
|
sta $1F ; CPU:$CA64 PRG:0A64 85 1F
|
|
; Routine: Gameplay_WriteTransferPointer_CA66
|
|
; Global: Reachable code entry at CPU $CA66 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteTransferPointer_CA66:
|
|
jsr Gameplay_WriteObjectWorkX_CACF ; CPU:$CA66 PRG:0A66 20 CF CA
|
|
lda #$02 ; CPU:$CA69 PRG:0A69 A9 02
|
|
sta ($34),y ; CPU:$CA6B PRG:0A6B 91 34
|
|
dec $1F ; CPU:$CA6D PRG:0A6D C6 1F
|
|
bne Gameplay_WriteTransferPointer_CA66 ; CPU:$CA6F PRG:0A6F D0 F5
|
|
rts ; CPU:$CA71 PRG:0A71 60
|
|
; Routine: Gameplay_WriteTransferPointer_CA72
|
|
; Global: Reachable code entry at CPU $CA72 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteTransferPointer_CA72:
|
|
lda #$00 ; CPU:$CA72 PRG:0A72 A9 00
|
|
sta $34 ; CPU:$CA74 PRG:0A74 85 34
|
|
lda #$02 ; CPU:$CA76 PRG:0A76 A9 02
|
|
sta $35 ; CPU:$CA78 PRG:0A78 85 35
|
|
ldy #$00 ; CPU:$CA7A PRG:0A7A A0 00
|
|
ldx #$00 ; CPU:$CA7C PRG:0A7C A2 00
|
|
jsr Gameplay_WriteObjectWorkX_CABA ; CPU:$CA7E PRG:0A7E 20 BA CA
|
|
ldx #$20 ; CPU:$CA81 PRG:0A81 A2 20
|
|
jsr Gameplay_WriteObjectWorkX_CABA ; CPU:$CA83 PRG:0A83 20 BA CA
|
|
ldx #$40 ; CPU:$CA86 PRG:0A86 A2 40
|
|
jsr Gameplay_WriteObjectWorkX_CABA ; CPU:$CA88 PRG:0A88 20 BA CA
|
|
ldx #$20 ; CPU:$CA8B PRG:0A8B A2 20
|
|
jsr Gameplay_WriteObjectWorkX_CABA ; CPU:$CA8D PRG:0A8D 20 BA CA
|
|
ldx #$40 ; CPU:$CA90 PRG:0A90 A2 40
|
|
jsr Gameplay_WriteObjectWorkX_CABA ; CPU:$CA92 PRG:0A92 20 BA CA
|
|
ldx #$20 ; CPU:$CA95 PRG:0A95 A2 20
|
|
jsr Gameplay_WriteObjectWorkX_CABA ; CPU:$CA97 PRG:0A97 20 BA CA
|
|
ldx #$40 ; CPU:$CA9A PRG:0A9A A2 40
|
|
jsr Gameplay_WriteObjectWorkX_CABA ; CPU:$CA9C PRG:0A9C 20 BA CA
|
|
ldx #$20 ; CPU:$CA9F PRG:0A9F A2 20
|
|
jsr Gameplay_WriteObjectWorkX_CABA ; CPU:$CAA1 PRG:0AA1 20 BA CA
|
|
ldx #$40 ; CPU:$CAA4 PRG:0AA4 A2 40
|
|
jsr Gameplay_WriteObjectWorkX_CABA ; CPU:$CAA6 PRG:0AA6 20 BA CA
|
|
ldx #$20 ; CPU:$CAA9 PRG:0AA9 A2 20
|
|
jsr Gameplay_WriteObjectWorkX_CABA ; CPU:$CAAB PRG:0AAB 20 BA CA
|
|
ldx #$40 ; CPU:$CAAE PRG:0AAE A2 40
|
|
jsr Gameplay_WriteObjectWorkX_CABA ; CPU:$CAB0 PRG:0AB0 20 BA CA
|
|
ldx #$20 ; CPU:$CAB3 PRG:0AB3 A2 20
|
|
jsr Gameplay_WriteObjectWorkX_CABA ; CPU:$CAB5 PRG:0AB5 20 BA CA
|
|
ldx #$00 ; CPU:$CAB8 PRG:0AB8 A2 00
|
|
; Routine: Gameplay_WriteObjectWorkX_CABA
|
|
; Global: Reachable code entry at CPU $CABA traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteObjectWorkX_CABA:
|
|
lda #$20 ; CPU:$CABA PRG:0ABA A9 20
|
|
sta $24 ; CPU:$CABC PRG:0ABC 85 24
|
|
; Routine: Gameplay_ReadRamE243_CABE
|
|
; Global: Reachable code entry at CPU $CABE traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadRamE243_CABE:
|
|
lda $E243,x ; CPU:$CABE PRG:0ABE BD 43 E2
|
|
sta ($34),y ; CPU:$CAC1 PRG:0AC1 91 34
|
|
inc $34 ; CPU:$CAC3 PRG:0AC3 E6 34
|
|
bne Gameplay_DecrementObjectWorkX_CAC9 ; CPU:$CAC5 PRG:0AC5 D0 02
|
|
inc $35 ; CPU:$CAC7 PRG:0AC7 E6 35
|
|
; Routine: Gameplay_DecrementObjectWorkX_CAC9
|
|
; Global: Reachable code entry at CPU $CAC9 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_DecrementObjectWorkX_CAC9:
|
|
inx ; CPU:$CAC9 PRG:0AC9 E8
|
|
dec $24 ; CPU:$CACA PRG:0ACA C6 24
|
|
bne Gameplay_ReadRamE243_CABE ; CPU:$CACC PRG:0ACC D0 F0
|
|
rts ; CPU:$CACE PRG:0ACE 60
|
|
; Routine: Gameplay_WriteObjectWorkX_CACF
|
|
; Global: Reachable code entry at CPU $CACF traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteObjectWorkX_CACF:
|
|
jsr AdvanceRandomState ; CPU:$CACF PRG:0ACF 20 70 D6
|
|
ror a ; CPU:$CAD2 PRG:0AD2 6A
|
|
ror a ; CPU:$CAD3 PRG:0AD3 6A
|
|
and #$1F ; CPU:$CAD4 PRG:0AD4 29 1F
|
|
beq Gameplay_WriteObjectWorkX_CACF ; CPU:$CAD6 PRG:0AD6 F0 F7
|
|
sta $24 ; CPU:$CAD8 PRG:0AD8 85 24
|
|
; Routine: Gameplay_WriteObjectWorkY_CADA
|
|
; Global: Reachable code entry at CPU $CADA traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteObjectWorkY_CADA:
|
|
jsr AdvanceRandomState ; CPU:$CADA PRG:0ADA 20 70 D6
|
|
ror a ; CPU:$CADD PRG:0ADD 6A
|
|
ror a ; CPU:$CADE PRG:0ADE 6A
|
|
ror a ; CPU:$CADF PRG:0ADF 6A
|
|
and #$0F ; CPU:$CAE0 PRG:0AE0 29 0F
|
|
beq Gameplay_WriteObjectWorkY_CADA ; CPU:$CAE2 PRG:0AE2 F0 F6
|
|
cmp #$0C ; CPU:$CAE4 PRG:0AE4 C9 0C
|
|
bcs Gameplay_WriteObjectWorkY_CADA ; CPU:$CAE6 PRG:0AE6 B0 F2
|
|
sta $25 ; CPU:$CAE8 PRG:0AE8 85 25
|
|
tay ; CPU:$CAEA PRG:0AEA A8
|
|
lda $E2A3,y ; CPU:$CAEB PRG:0AEB B9 A3 E2
|
|
sta $34 ; CPU:$CAEE PRG:0AEE 85 34
|
|
lda $E2B0,y ; CPU:$CAF0 PRG:0AF0 B9 B0 E2
|
|
sta $35 ; CPU:$CAF3 PRG:0AF3 85 35
|
|
ldy $24 ; CPU:$CAF5 PRG:0AF5 A4 24
|
|
lda ($34),y ; CPU:$CAF7 PRG:0AF7 B1 34
|
|
bne Gameplay_WriteObjectWorkX_CACF ; CPU:$CAF9 PRG:0AF9 D0 D4
|
|
cpy #$03 ; CPU:$CAFB PRG:0AFB C0 03
|
|
bcs Gameplay_ReturnToCaller_CB05 ; CPU:$CAFD PRG:0AFD B0 06
|
|
lda $25 ; CPU:$CAFF PRG:0AFF A5 25
|
|
cmp #$03 ; CPU:$CB01 PRG:0B01 C9 03
|
|
bcc Gameplay_WriteObjectWorkX_CACF ; CPU:$CB03 PRG:0B03 90 CA
|
|
; Routine: Gameplay_ReturnToCaller_CB05
|
|
; Global: Reachable code entry at CPU $CB05 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReturnToCaller_CB05:
|
|
rts ; CPU:$CB05 PRG:0B05 60
|
|
; Routine: Gameplay_WriteWorkValue_CB06
|
|
; Global: Reachable code entry at CPU $CB06 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteWorkValue_CB06:
|
|
jsr DisableRendering ; CPU:$CB06 PRG:0B06 20 57 C2
|
|
lda #$00 ; CPU:$CB09 PRG:0B09 A9 00
|
|
sta $20 ; CPU:$CB0B PRG:0B0B 85 20
|
|
lda #$00 ; CPU:$CB0D PRG:0B0D A9 00
|
|
sta $26 ; CPU:$CB0F PRG:0B0F 85 26
|
|
lda #$02 ; CPU:$CB11 PRG:0B11 A9 02
|
|
sta $27 ; CPU:$CB13 PRG:0B13 85 27
|
|
ldy #$00 ; CPU:$CB15 PRG:0B15 A0 00
|
|
; Routine: Gameplay_WriteWorkIndex_CB17
|
|
; Global: Reachable code entry at CPU $CB17 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteWorkIndex_CB17:
|
|
lda #$00 ; CPU:$CB17 PRG:0B17 A9 00
|
|
sta $1F ; CPU:$CB19 PRG:0B19 85 1F
|
|
; Routine: Gameplay_ReadZp94_CB1B
|
|
; Global: Reachable code entry at CPU $CB1B traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadZp94_CB1B:
|
|
lda $94 ; CPU:$CB1B PRG:0B1B A5 94
|
|
beq Gameplay_ReadDataPointer_CB24 ; CPU:$CB1D PRG:0B1D F0 05
|
|
lda ($26),y ; CPU:$CB1F PRG:0B1F B1 26
|
|
jmp Gameplay_IncrementZp27_CB30 ; CPU:$CB21 PRG:0B21 4C 30 CB
|
|
; Routine: Gameplay_ReadDataPointer_CB24
|
|
; Global: Reachable code entry at CPU $CB24 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadDataPointer_CB24:
|
|
lda ($26),y ; CPU:$CB24 PRG:0B24 B1 26
|
|
cmp #$04 ; CPU:$CB26 PRG:0B26 C9 04
|
|
beq Gameplay_HandleControl_CB2E ; CPU:$CB28 PRG:0B28 F0 04
|
|
cmp #$05 ; CPU:$CB2A PRG:0B2A C9 05
|
|
bne Gameplay_IncrementZp27_CB30 ; CPU:$CB2C PRG:0B2C D0 02
|
|
; Routine: Gameplay_HandleControl_CB2E
|
|
; Global: Reachable code entry at CPU $CB2E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_HandleControl_CB2E:
|
|
lda #$02 ; CPU:$CB2E PRG:0B2E A9 02
|
|
; Routine: Gameplay_IncrementZp27_CB30
|
|
; Global: Reachable code entry at CPU $CB30 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_IncrementZp27_CB30:
|
|
jsr Gameplay_WriteObjectWorkY_CB4E ; CPU:$CB30 PRG:0B30 20 4E CB
|
|
iny ; CPU:$CB33 PRG:0B33 C8
|
|
bne Gameplay_IncrementWorkIndex_CB38 ; CPU:$CB34 PRG:0B34 D0 02
|
|
inc $27 ; CPU:$CB36 PRG:0B36 E6 27
|
|
; Routine: Gameplay_IncrementWorkIndex_CB38
|
|
; Global: Reachable code entry at CPU $CB38 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_IncrementWorkIndex_CB38:
|
|
inc $1F ; CPU:$CB38 PRG:0B38 E6 1F
|
|
lda $1F ; CPU:$CB3A PRG:0B3A A5 1F
|
|
and #$20 ; CPU:$CB3C PRG:0B3C 29 20
|
|
beq Gameplay_ReadZp94_CB1B ; CPU:$CB3E PRG:0B3E F0 DB
|
|
inc $20 ; CPU:$CB40 PRG:0B40 E6 20
|
|
lda $20 ; CPU:$CB42 PRG:0B42 A5 20
|
|
cmp #$0D ; CPU:$CB44 PRG:0B44 C9 0D
|
|
bne Gameplay_WriteWorkIndex_CB17 ; CPU:$CB46 PRG:0B46 D0 CF
|
|
jsr Menu_HandleControl_DDC7 ; CPU:$CB48 PRG:0B48 20 C7 DD
|
|
jmp CommitPpuStateAndScroll ; CPU:$CB4B PRG:0B4B 4C 96 C2
|
|
; Routine: Gameplay_WriteObjectWorkY_CB4E
|
|
; Global: Reachable code entry at CPU $CB4E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteObjectWorkY_CB4E:
|
|
sty $25 ; CPU:$CB4E PRG:0B4E 84 25
|
|
jsr Stage_WriteZp1A_D924 ; CPU:$CB50 PRG:0B50 20 24 D9
|
|
ldx #$00 ; CPU:$CB53 PRG:0B53 A2 00
|
|
; Routine: Gameplay_ReadZp17_CB55
|
|
; Global: Reachable code entry at CPU $CB55 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadZp17_CB55:
|
|
lda $17,x ; CPU:$CB55 PRG:0B55 B5 17
|
|
sta $0600,x ; CPU:$CB57 PRG:0B57 9D 00 06
|
|
inx ; CPU:$CB5A PRG:0B5A E8
|
|
cpx #$08 ; CPU:$CB5B PRG:0B5B E0 08
|
|
bne Gameplay_ReadZp17_CB55 ; CPU:$CB5D PRG:0B5D D0 F6
|
|
jsr Gameplay_TransferVramData_CB65 ; CPU:$CB5F PRG:0B5F 20 65 CB
|
|
ldy $25 ; CPU:$CB62 PRG:0B62 A4 25
|
|
rts ; CPU:$CB64 PRG:0B64 60
|
|
; Routine: Gameplay_TransferVramData_CB65
|
|
; Global: Reachable code entry at CPU $CB65 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_TransferVramData_CB65:
|
|
lda $0602 ; CPU:$CB65 PRG:0B65 AD 02 06
|
|
ora $0600 ; CPU:$CB68 PRG:0B68 0D 00 06
|
|
pha ; CPU:$CB6B PRG:0B6B 48
|
|
sta PPUADDR ; CPU:$CB6C PRG:0B6C 8D 06 20
|
|
ldx $0601 ; CPU:$CB6F PRG:0B6F AE 01 06
|
|
stx PPUADDR ; CPU:$CB72 PRG:0B72 8E 06 20
|
|
ldx $0603 ; CPU:$CB75 PRG:0B75 AE 03 06
|
|
lda $D9C6,x ; CPU:$CB78 PRG:0B78 BD C6 D9
|
|
sta PPUDATA ; CPU:$CB7B PRG:0B7B 8D 07 20
|
|
lda $D9C7,x ; CPU:$CB7E PRG:0B7E BD C7 D9
|
|
sta PPUDATA ; CPU:$CB81 PRG:0B81 8D 07 20
|
|
pla ; CPU:$CB84 PRG:0B84 68
|
|
sta PPUADDR ; CPU:$CB85 PRG:0B85 8D 06 20
|
|
lda $0601 ; CPU:$CB88 PRG:0B88 AD 01 06
|
|
clc ; CPU:$CB8B PRG:0B8B 18
|
|
adc #$20 ; CPU:$CB8C PRG:0B8C 69 20
|
|
sta PPUADDR ; CPU:$CB8E PRG:0B8E 8D 06 20
|
|
lda $D9C8,x ; CPU:$CB91 PRG:0B91 BD C8 D9
|
|
sta PPUDATA ; CPU:$CB94 PRG:0B94 8D 07 20
|
|
lda $D9C9,x ; CPU:$CB97 PRG:0B97 BD C9 D9
|
|
sta PPUDATA ; CPU:$CB9A PRG:0B9A 8D 07 20
|
|
lda #$23 ; CPU:$CB9D PRG:0B9D A9 23
|
|
ora $0600 ; CPU:$CB9F PRG:0B9F 0D 00 06
|
|
pha ; CPU:$CBA2 PRG:0BA2 48
|
|
sta PPUADDR ; CPU:$CBA3 PRG:0BA3 8D 06 20
|
|
lda $0604 ; CPU:$CBA6 PRG:0BA6 AD 04 06
|
|
sta PPUADDR ; CPU:$CBA9 PRG:0BA9 8D 06 20
|
|
tax ; CPU:$CBAC PRG:0BAC AA
|
|
lda PPUDATA ; CPU:$CBAD PRG:0BAD AD 07 20
|
|
lda PPUDATA ; CPU:$CBB0 PRG:0BB0 AD 07 20
|
|
and $0606 ; CPU:$CBB3 PRG:0BB3 2D 06 06
|
|
ora $0607 ; CPU:$CBB6 PRG:0BB6 0D 07 06
|
|
tay ; CPU:$CBB9 PRG:0BB9 A8
|
|
pla ; CPU:$CBBA PRG:0BBA 68
|
|
sta PPUADDR ; CPU:$CBBB PRG:0BBB 8D 06 20
|
|
stx PPUADDR ; CPU:$CBBE PRG:0BBE 8E 06 20
|
|
sty PPUDATA ; CPU:$CBC1 PRG:0BC1 8C 07 20
|
|
rts ; CPU:$CBC4 PRG:0BC4 60
|
|
; Routine: Gameplay_HandleControl_CBC5
|
|
; Global: Reachable code entry at CPU $CBC5 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_HandleControl_CBC5:
|
|
ldx #$09 ; CPU:$CBC5 PRG:0BC5 A2 09
|
|
lda #$00 ; CPU:$CBC7 PRG:0BC7 A9 00
|
|
; Routine: Gameplay_WriteRam03A0_CBC9
|
|
; Global: Reachable code entry at CPU $CBC9 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteRam03A0_CBC9:
|
|
sta $03A0,x ; CPU:$CBC9 PRG:0BC9 9D A0 03
|
|
dex ; CPU:$CBCC PRG:0BCC CA
|
|
bpl Gameplay_WriteRam03A0_CBC9 ; CPU:$CBCD PRG:0BCD 10 FA
|
|
ldx #$4F ; CPU:$CBCF PRG:0BCF A2 4F
|
|
; Routine: Gameplay_WriteRam03E6_CBD1
|
|
; Global: Reachable code entry at CPU $CBD1 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteRam03E6_CBD1:
|
|
sta $03E6,x ; CPU:$CBD1 PRG:0BD1 9D E6 03
|
|
dex ; CPU:$CBD4 PRG:0BD4 CA
|
|
bpl Gameplay_WriteRam03E6_CBD1 ; CPU:$CBD5 PRG:0BD5 10 FA
|
|
; Routine: Gameplay_HandleControl_CBD7
|
|
; Global: Reachable code entry at CPU $CBD7 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_HandleControl_CBD7:
|
|
lda #$00 ; CPU:$CBD7 PRG:0BD7 A9 00
|
|
ldx #$09 ; CPU:$CBD9 PRG:0BD9 A2 09
|
|
; Routine: Gameplay_WriteRam0576_CBDB
|
|
; Global: Reachable code entry at CPU $CBDB traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteRam0576_CBDB:
|
|
sta $0576,x ; CPU:$CBDB PRG:0BDB 9D 76 05
|
|
dex ; CPU:$CBDE PRG:0BDE CA
|
|
bpl Gameplay_WriteRam0576_CBDB ; CPU:$CBDF PRG:0BDF 10 FA
|
|
rts ; CPU:$CBE1 PRG:0BE1 60
|
|
; Routine: Gameplay_RetreatIndexY_CBE2
|
|
; Global: Reachable code entry at CPU $CBE2 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_RetreatIndexY_CBE2:
|
|
dey ; CPU:$CBE2 PRG:0BE2 88
|
|
bmi Gameplay_ReturnToCaller_CBEA ; CPU:$CBE3 PRG:0BE3 30 05
|
|
; Routine: Gameplay_ReadRam03E6_CBE5
|
|
; Global: Reachable code entry at CPU $CBE5 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadRam03E6_CBE5:
|
|
lda $03E6,y ; CPU:$CBE5 PRG:0BE5 B9 E6 03
|
|
bne Gameplay_RetreatIndexY_CBE2 ; CPU:$CBE8 PRG:0BE8 D0 F8
|
|
; Routine: Gameplay_ReturnToCaller_CBEA
|
|
; Global: Reachable code entry at CPU $CBEA traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReturnToCaller_CBEA:
|
|
rts ; CPU:$CBEA PRG:0BEA 60
|
|
; Routine: Gameplay_ReadRamE2A3_CBEB
|
|
; Global: Reachable code entry at CPU $CBEB traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadRamE2A3_CBEB:
|
|
lda $E2A3,y ; CPU:$CBEB PRG:0BEB B9 A3 E2
|
|
sta $34 ; CPU:$CBEE PRG:0BEE 85 34
|
|
lda $E2B0,y ; CPU:$CBF0 PRG:0BF0 B9 B0 E2
|
|
sta $35 ; CPU:$CBF3 PRG:0BF3 85 35
|
|
rts ; CPU:$CBF5 PRG:0BF5 60
|
|
; Routine: Gameplay_WriteDisplayMode_CBF6
|
|
; Global: Reachable code entry at CPU $CBF6 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteDisplayMode_CBF6:
|
|
lda #$01 ; CPU:$CBF6 PRG:0BF6 A9 01
|
|
sta $38 ; CPU:$CBF8 PRG:0BF8 85 38
|
|
rts ; CPU:$CBFA PRG:0BFA 60
|
|
; Routine: WaitForNmiFrameHandoff
|
|
; Global: Reachable code entry at CPU $CBFB traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
WaitForNmiFrameHandoff:
|
|
lda FrameSyncFlag ; CPU:$CBFB PRG:0BFB A5 0B
|
|
bne WaitForNmiFrameHandoff ; CPU:$CBFD PRG:0BFD D0 FC
|
|
lda #$01 ; CPU:$CBFF PRG:0BFF A9 01
|
|
sta FrameSyncFlag ; CPU:$CC01 PRG:0C01 85 0B
|
|
rts ; CPU:$CC03 PRG:0C03 60
|
|
|
|
; Data region: CPU $CC04-$CC35; unreachable by direct recursive trace.
|
|
FrameAnimationSequenceTable:
|
|
.byte $02, $01, $05, $03, $01, $01, $02, $05, $06, $04, $01, $01, $05, $06, $02, $04 ; CPU:$CC04 PRG:0C04 02 01 05 03 01 01 02 05 06 04 01 01 05 06 02 04
|
|
.byte $01, $06, $01, $05, $06, $05, $01, $05, $06, $08, $02, $01, $05, $07, $04, $01 ; CPU:$CC14 PRG:0C14 01 06 01 05 06 05 01 05 06 08 02 01 05 07 04 01
|
|
.byte $05, $08, $06, $07, $05, $02, $04, $08, $05, $04, $06, $05, $08, $04, $06, $05 ; CPU:$CC24 PRG:0C24 05 08 06 07 05 02 04 08 05 04 06 05 08 04 06 05
|
|
.byte $07, $08 ; CPU:$CC34 PRG:0C34 07 08
|
|
; Routine: Frame_ReadZp7D_CC36
|
|
; Global: Reachable code entry at CPU $CC36 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReadZp7D_CC36:
|
|
lda $7D ; CPU:$CC36 PRG:0C36 A5 7D
|
|
bne Frame_ReadZp5C_CC4C ; CPU:$CC38 PRG:0C38 D0 12
|
|
lda $7A ; CPU:$CC3A PRG:0C3A A5 7A
|
|
beq Frame_ReadZp5C_CC4C ; CPU:$CC3C PRG:0C3C F0 0E
|
|
lda $33 ; CPU:$CC3E PRG:0C3E A5 33
|
|
and #$07 ; CPU:$CC40 PRG:0C40 29 07
|
|
bne Frame_ReadZp5C_CC4C ; CPU:$CC42 PRG:0C42 D0 08
|
|
dec $7A ; CPU:$CC44 PRG:0C44 C6 7A
|
|
bne Frame_ReadZp5C_CC4C ; CPU:$CC46 PRG:0C46 D0 04
|
|
lda #$03 ; CPU:$CC48 PRG:0C48 A9 03
|
|
sta $B5 ; CPU:$CC4A PRG:0C4A 85 B5
|
|
; Routine: Frame_ReadZp5C_CC4C
|
|
; Global: Reachable code entry at CPU $CC4C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReadZp5C_CC4C:
|
|
lda $5C ; CPU:$CC4C PRG:0C4C A5 5C
|
|
beq Frame_ReadObjectX_CC63 ; CPU:$CC4E PRG:0C4E F0 13
|
|
lda $33 ; CPU:$CC50 PRG:0C50 A5 33
|
|
and #$0F ; CPU:$CC52 PRG:0C52 29 0F
|
|
bne Frame_ReturnToCaller_CC62 ; CPU:$CC54 PRG:0C54 D0 0C
|
|
inc $2C ; CPU:$CC56 PRG:0C56 E6 2C
|
|
lda $2C ; CPU:$CC58 PRG:0C58 A5 2C
|
|
cmp #$14 ; CPU:$CC5A PRG:0C5A C9 14
|
|
bne Frame_ReturnToCaller_CC62 ; CPU:$CC5C PRG:0C5C D0 04
|
|
lda #$01 ; CPU:$CC5E PRG:0C5E A9 01
|
|
sta $5D ; CPU:$CC60 PRG:0C60 85 5D
|
|
; Routine: Frame_ReturnToCaller_CC62
|
|
; Global: Reachable code entry at CPU $CC62 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReturnToCaller_CC62:
|
|
rts ; CPU:$CC62 PRG:0C62 60
|
|
; Routine: Frame_ReadObjectX_CC63
|
|
; Global: Reachable code entry at CPU $CC63 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReadObjectX_CC63:
|
|
lda $29 ; CPU:$CC63 PRG:0C63 A5 29
|
|
cmp #$08 ; CPU:$CC65 PRG:0C65 C9 08
|
|
bne Frame_ReadObjectFlags_CCA4 ; CPU:$CC67 PRG:0C67 D0 3B
|
|
lda $2B ; CPU:$CC69 PRG:0C69 A5 2B
|
|
cmp #$08 ; CPU:$CC6B PRG:0C6B C9 08
|
|
bne Frame_ReadObjectFlags_CCA4 ; CPU:$CC6D PRG:0C6D D0 35
|
|
ldy $2A ; CPU:$CC6F PRG:0C6F A4 2A
|
|
sty $20 ; CPU:$CC71 PRG:0C71 84 20
|
|
lda $E2A3,y ; CPU:$CC73 PRG:0C73 B9 A3 E2
|
|
sta $34 ; CPU:$CC76 PRG:0C76 85 34
|
|
lda $E2B0,y ; CPU:$CC78 PRG:0C78 B9 B0 E2
|
|
sta $35 ; CPU:$CC7B PRG:0C7B 85 35
|
|
ldy $28 ; CPU:$CC7D PRG:0C7D A4 28
|
|
sty $1F ; CPU:$CC7F PRG:0C7F 84 1F
|
|
lda ($34),y ; CPU:$CC81 PRG:0C81 B1 34
|
|
cmp #$08 ; CPU:$CC83 PRG:0C83 C9 08
|
|
beq Frame_IncrementBombCapacity_CC95 ; CPU:$CC85 PRG:0C85 F0 0E
|
|
cmp #$06 ; CPU:$CC87 PRG:0C87 C9 06
|
|
bne Frame_ReadObjectFlags_CCA4 ; CPU:$CC89 PRG:0C89 D0 19
|
|
lda #$00 ; CPU:$CC8B PRG:0C8B A9 00
|
|
sta ($34),y ; CPU:$CC8D PRG:0C8D 91 34
|
|
jsr Stage_WriteObjectWorkX_D8FC ; CPU:$CC8F PRG:0C8F 20 FC D8
|
|
jmp Frame_WriteSoundCommandState_CEE9 ; CPU:$CC92 PRG:0C92 4C E9 CE
|
|
; Routine: Frame_IncrementBombCapacity_CC95
|
|
; Global: Reachable code entry at CPU $CC95 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_IncrementBombCapacity_CC95:
|
|
inc $9F ; CPU:$CC95 PRG:0C95 E6 9F
|
|
lda #$00 ; CPU:$CC97 PRG:0C97 A9 00
|
|
sta $A6 ; CPU:$CC99 PRG:0C99 85 A6
|
|
lda $9C ; CPU:$CC9B PRG:0C9B A5 9C
|
|
bne Frame_ReadObjectFlags_CCA4 ; CPU:$CC9D PRG:0C9D D0 05
|
|
lda #$01 ; CPU:$CC9F PRG:0C9F A9 01
|
|
sta $5E ; CPU:$CCA1 PRG:0CA1 85 5E
|
|
; Routine: Frame_ReturnToCaller_CCA3
|
|
; Global: Reachable code entry at CPU $CCA3 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReturnToCaller_CCA3:
|
|
rts ; CPU:$CCA3 PRG:0CA3 60
|
|
; Routine: Frame_ReadObjectFlags_CCA4
|
|
; Global: Reachable code entry at CPU $CCA4 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReadObjectFlags_CCA4:
|
|
lda $75 ; CPU:$CCA4 PRG:0CA4 A5 75
|
|
bne Frame_WriteInvincibilityTimer_CCAE ; CPU:$CCA6 PRG:0CA6 D0 06
|
|
lda $33 ; CPU:$CCA8 PRG:0CA8 A5 33
|
|
and #$03 ; CPU:$CCAA PRG:0CAA 29 03
|
|
beq Frame_ReturnToCaller_CCA3 ; CPU:$CCAC PRG:0CAC F0 F5
|
|
; Routine: Frame_WriteInvincibilityTimer_CCAE
|
|
; Global: Reachable code entry at CPU $CCAE traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_WriteInvincibilityTimer_CCAE:
|
|
jsr Object_ReadGameState_CF87 ; CPU:$CCAE PRG:0CAE 20 87 CF
|
|
bne Frame_CopyAToX_CCB7 ; CPU:$CCB1 PRG:0CB1 D0 04
|
|
sta $A6 ; CPU:$CCB3 PRG:0CB3 85 A6
|
|
sta $7B ; CPU:$CCB5 PRG:0CB5 85 7B
|
|
; Routine: Frame_CopyAToX_CCB7
|
|
; Global: Reachable code entry at CPU $CCB7 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_CopyAToX_CCB7:
|
|
tax ; CPU:$CCB7 PRG:0CB7 AA
|
|
and #$01 ; CPU:$CCB8 PRG:0CB8 29 01
|
|
beq Frame_CopyXToA_CCBF ; CPU:$CCBA PRG:0CBA F0 03
|
|
jsr Frame_ReadObjectX_CDD4 ; CPU:$CCBC PRG:0CBC 20 D4 CD
|
|
; Routine: Frame_CopyXToA_CCBF
|
|
; Global: Reachable code entry at CPU $CCBF traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_CopyXToA_CCBF:
|
|
txa ; CPU:$CCBF PRG:0CBF 8A
|
|
and #$02 ; CPU:$CCC0 PRG:0CC0 29 02
|
|
beq Frame_CopyXToA_CCC7 ; CPU:$CCC2 PRG:0CC2 F0 03
|
|
jsr Frame_ReadObjectX_CDA3 ; CPU:$CCC4 PRG:0CC4 20 A3 CD
|
|
; Routine: Frame_CopyXToA_CCC7
|
|
; Global: Reachable code entry at CPU $CCC7 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_CopyXToA_CCC7:
|
|
txa ; CPU:$CCC7 PRG:0CC7 8A
|
|
and #$08 ; CPU:$CCC8 PRG:0CC8 29 08
|
|
beq Frame_CopyXToA_CCCF ; CPU:$CCCA PRG:0CCA F0 03
|
|
jsr Frame_ReadObjectY_CD70 ; CPU:$CCCC PRG:0CCC 20 70 CD
|
|
; Routine: Frame_CopyXToA_CCCF
|
|
; Global: Reachable code entry at CPU $CCCF traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_CopyXToA_CCCF:
|
|
txa ; CPU:$CCCF PRG:0CCF 8A
|
|
and #$04 ; CPU:$CCD0 PRG:0CD0 29 04
|
|
beq Frame_ReadObjectSubtype_CCD7 ; CPU:$CCD2 PRG:0CD2 F0 03
|
|
jsr Frame_ReadObjectY_CD39 ; CPU:$CCD4 PRG:0CD4 20 39 CD
|
|
; Routine: Frame_ReadObjectSubtype_CCD7
|
|
; Global: Reachable code entry at CPU $CCD7 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReadObjectSubtype_CCD7:
|
|
txa ; CPU:$CCD7 PRG:0CD7 8A
|
|
and #$80 ; CPU:$CCD8 PRG:0CD8 29 80
|
|
bne Frame_ReadObjectState_CCEF ; CPU:$CCDA PRG:0CDA D0 13
|
|
lda $77 ; CPU:$CCDC PRG:0CDC A5 77
|
|
beq Frame_ReturnToCaller_CCEE ; CPU:$CCDE PRG:0CDE F0 0E
|
|
lda $7B ; CPU:$CCE0 PRG:0CE0 A5 7B
|
|
bne Frame_ReturnToCaller_CCEE ; CPU:$CCE2 PRG:0CE2 D0 0A
|
|
txa ; CPU:$CCE4 PRG:0CE4 8A
|
|
and #$40 ; CPU:$CCE5 PRG:0CE5 29 40
|
|
beq Frame_ReturnToCaller_CCEE ; CPU:$CCE7 PRG:0CE7 F0 05
|
|
sta $7B ; CPU:$CCE9 PRG:0CE9 85 7B
|
|
jsr Gameplay_HandleControl_C939 ; CPU:$CCEB PRG:0CEB 20 39 C9
|
|
; Routine: Frame_ReturnToCaller_CCEE
|
|
; Global: Reachable code entry at CPU $CCEE traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReturnToCaller_CCEE:
|
|
rts ; CPU:$CCEE PRG:0CEE 60
|
|
; Routine: Frame_ReadObjectState_CCEF
|
|
; Global: Reachable code entry at CPU $CCEF traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReadObjectState_CCEF:
|
|
ldy $2A ; CPU:$CCEF PRG:0CEF A4 2A
|
|
lda $E2A3,y ; CPU:$CCF1 PRG:0CF1 B9 A3 E2
|
|
sta $34 ; CPU:$CCF4 PRG:0CF4 85 34
|
|
lda $E2B0,y ; CPU:$CCF6 PRG:0CF6 B9 B0 E2
|
|
sta $35 ; CPU:$CCF9 PRG:0CF9 85 35
|
|
ldy $28 ; CPU:$CCFB PRG:0CFB A4 28
|
|
lda ($34),y ; CPU:$CCFD PRG:0CFD B1 34
|
|
bne Frame_ReturnToCaller_CCEE ; CPU:$CCFF PRG:0CFF D0 ED
|
|
jsr Frame_ReadObjectX_CE10 ; CPU:$CD01 PRG:0D01 20 10 CE
|
|
jsr Frame_ReadObjectY_CE1F ; CPU:$CD04 PRG:0D04 20 1F CE
|
|
ldx $74 ; CPU:$CD07 PRG:0D07 A6 74
|
|
; Routine: Frame_ReadRam03A0_CD09
|
|
; Global: Reachable code entry at CPU $CD09 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReadRam03A0_CD09:
|
|
lda $03A0,x ; CPU:$CD09 PRG:0D09 BD A0 03
|
|
beq Frame_WriteTransferPointer_CD12 ; CPU:$CD0C PRG:0D0C F0 04
|
|
dex ; CPU:$CD0E PRG:0D0E CA
|
|
bpl Frame_ReadRam03A0_CD09 ; CPU:$CD0F PRG:0D0F 10 F8
|
|
rts ; CPU:$CD11 PRG:0D11 60
|
|
; Routine: Frame_WriteTransferPointer_CD12
|
|
; Global: Reachable code entry at CPU $CD12 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_WriteTransferPointer_CD12:
|
|
lda #$03 ; CPU:$CD12 PRG:0D12 A9 03
|
|
sta ($34),y ; CPU:$CD14 PRG:0D14 91 34
|
|
lda $28 ; CPU:$CD16 PRG:0D16 A5 28
|
|
sta $03AA,x ; CPU:$CD18 PRG:0D18 9D AA 03
|
|
lda $2A ; CPU:$CD1B PRG:0D1B A5 2A
|
|
sta $03B4,x ; CPU:$CD1D PRG:0D1D 9D B4 03
|
|
lda #$00 ; CPU:$CD20 PRG:0D20 A9 00
|
|
sta $03D2,x ; CPU:$CD22 PRG:0D22 9D D2 03
|
|
lda #$00 ; CPU:$CD25 PRG:0D25 A9 00
|
|
sta $03C8,x ; CPU:$CD27 PRG:0D27 9D C8 03
|
|
lda #$A0 ; CPU:$CD2A PRG:0D2A A9 A0
|
|
sta $03BE,x ; CPU:$CD2C PRG:0D2C 9D BE 03
|
|
lda #$01 ; CPU:$CD2F PRG:0D2F A9 01
|
|
sta $03A0,x ; CPU:$CD31 PRG:0D31 9D A0 03
|
|
lda #$03 ; CPU:$CD34 PRG:0D34 A9 03
|
|
sta $DF ; CPU:$CD36 PRG:0D36 85 DF
|
|
rts ; CPU:$CD38 PRG:0D38 60
|
|
; Routine: Frame_ReadObjectY_CD39
|
|
; Global: Reachable code entry at CPU $CD39 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReadObjectY_CD39:
|
|
lda $2B ; CPU:$CD39 PRG:0D39 A5 2B
|
|
cmp #$08 ; CPU:$CD3B PRG:0D3B C9 08
|
|
bcs Frame_ReadObjectState_CD44 ; CPU:$CD3D PRG:0D3D B0 05
|
|
inc $2B ; CPU:$CD3F PRG:0D3F E6 2B
|
|
jmp Frame_HandleControl_CD69 ; CPU:$CD41 PRG:0D41 4C 69 CD
|
|
; Routine: Frame_ReadObjectState_CD44
|
|
; Global: Reachable code entry at CPU $CD44 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReadObjectState_CD44:
|
|
ldy $2A ; CPU:$CD44 PRG:0D44 A4 2A
|
|
iny ; CPU:$CD46 PRG:0D46 C8
|
|
lda $E2A3,y ; CPU:$CD47 PRG:0D47 B9 A3 E2
|
|
sta $34 ; CPU:$CD4A PRG:0D4A 85 34
|
|
lda $E2B0,y ; CPU:$CD4C PRG:0D4C B9 B0 E2
|
|
sta $35 ; CPU:$CD4F PRG:0D4F 85 35
|
|
ldy $28 ; CPU:$CD51 PRG:0D51 A4 28
|
|
jsr Object_ReadTransferPointer_CF60 ; CPU:$CD53 PRG:0D53 20 60 CF
|
|
bne Frame_HandleControl_CD69 ; CPU:$CD56 PRG:0D56 D0 11
|
|
jsr Frame_ReadObjectX_CE10 ; CPU:$CD58 PRG:0D58 20 10 CE
|
|
inc $2B ; CPU:$CD5B PRG:0D5B E6 2B
|
|
lda $2B ; CPU:$CD5D PRG:0D5D A5 2B
|
|
cmp #$10 ; CPU:$CD5F PRG:0D5F C9 10
|
|
bne Frame_HandleControl_CD69 ; CPU:$CD61 PRG:0D61 D0 06
|
|
lda #$00 ; CPU:$CD63 PRG:0D63 A9 00
|
|
sta $2B ; CPU:$CD65 PRG:0D65 85 2B
|
|
inc $2A ; CPU:$CD67 PRG:0D67 E6 2A
|
|
; Routine: Frame_HandleControl_CD69
|
|
; Global: Reachable code entry at CPU $CD69 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_HandleControl_CD69:
|
|
lda #$04 ; CPU:$CD69 PRG:0D69 A9 04
|
|
ldy #$07 ; CPU:$CD6B PRG:0D6B A0 07
|
|
jmp Frame_ReadZp33_CE2E ; CPU:$CD6D PRG:0D6D 4C 2E CE
|
|
; Routine: Frame_ReadObjectY_CD70
|
|
; Global: Reachable code entry at CPU $CD70 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReadObjectY_CD70:
|
|
lda $2B ; CPU:$CD70 PRG:0D70 A5 2B
|
|
cmp #$09 ; CPU:$CD72 PRG:0D72 C9 09
|
|
bcc Frame_ReadObjectState_CD7B ; CPU:$CD74 PRG:0D74 90 05
|
|
dec $2B ; CPU:$CD76 PRG:0D76 C6 2B
|
|
jmp Frame_HandleControl_CD9C ; CPU:$CD78 PRG:0D78 4C 9C CD
|
|
; Routine: Frame_ReadObjectState_CD7B
|
|
; Global: Reachable code entry at CPU $CD7B traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReadObjectState_CD7B:
|
|
ldy $2A ; CPU:$CD7B PRG:0D7B A4 2A
|
|
dey ; CPU:$CD7D PRG:0D7D 88
|
|
lda $E2A3,y ; CPU:$CD7E PRG:0D7E B9 A3 E2
|
|
sta $34 ; CPU:$CD81 PRG:0D81 85 34
|
|
lda $E2B0,y ; CPU:$CD83 PRG:0D83 B9 B0 E2
|
|
sta $35 ; CPU:$CD86 PRG:0D86 85 35
|
|
ldy $28 ; CPU:$CD88 PRG:0D88 A4 28
|
|
jsr Object_ReadTransferPointer_CF60 ; CPU:$CD8A PRG:0D8A 20 60 CF
|
|
bne Frame_HandleControl_CD9C ; CPU:$CD8D PRG:0D8D D0 0D
|
|
jsr Frame_ReadObjectX_CE10 ; CPU:$CD8F PRG:0D8F 20 10 CE
|
|
dec $2B ; CPU:$CD92 PRG:0D92 C6 2B
|
|
bpl Frame_HandleControl_CD9C ; CPU:$CD94 PRG:0D94 10 06
|
|
lda #$0F ; CPU:$CD96 PRG:0D96 A9 0F
|
|
sta $2B ; CPU:$CD98 PRG:0D98 85 2B
|
|
dec $2A ; CPU:$CD9A PRG:0D9A C6 2A
|
|
; Routine: Frame_HandleControl_CD9C
|
|
; Global: Reachable code entry at CPU $CD9C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_HandleControl_CD9C:
|
|
lda #$08 ; CPU:$CD9C PRG:0D9C A9 08
|
|
ldy #$0B ; CPU:$CD9E PRG:0D9E A0 0B
|
|
jmp Frame_ReadZp33_CE2E ; CPU:$CDA0 PRG:0DA0 4C 2E CE
|
|
; Routine: Frame_ReadObjectX_CDA3
|
|
; Global: Reachable code entry at CPU $CDA3 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReadObjectX_CDA3:
|
|
lda $29 ; CPU:$CDA3 PRG:0DA3 A5 29
|
|
cmp #$09 ; CPU:$CDA5 PRG:0DA5 C9 09
|
|
bcc Frame_ReadObjectState_CDAE ; CPU:$CDA7 PRG:0DA7 90 05
|
|
dec $29 ; CPU:$CDA9 PRG:0DA9 C6 29
|
|
jmp Frame_HandleControl_CDCF ; CPU:$CDAB PRG:0DAB 4C CF CD
|
|
; Routine: Frame_ReadObjectState_CDAE
|
|
; Global: Reachable code entry at CPU $CDAE traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReadObjectState_CDAE:
|
|
ldy $2A ; CPU:$CDAE PRG:0DAE A4 2A
|
|
lda $E2A3,y ; CPU:$CDB0 PRG:0DB0 B9 A3 E2
|
|
sta $34 ; CPU:$CDB3 PRG:0DB3 85 34
|
|
lda $E2B0,y ; CPU:$CDB5 PRG:0DB5 B9 B0 E2
|
|
sta $35 ; CPU:$CDB8 PRG:0DB8 85 35
|
|
ldy $28 ; CPU:$CDBA PRG:0DBA A4 28
|
|
dey ; CPU:$CDBC PRG:0DBC 88
|
|
jsr Object_ReadTransferPointer_CF60 ; CPU:$CDBD PRG:0DBD 20 60 CF
|
|
bne Frame_HandleControl_CDCF ; CPU:$CDC0 PRG:0DC0 D0 0D
|
|
jsr Frame_ReadObjectY_CE1F ; CPU:$CDC2 PRG:0DC2 20 1F CE
|
|
dec $29 ; CPU:$CDC5 PRG:0DC5 C6 29
|
|
bpl Frame_HandleControl_CDCF ; CPU:$CDC7 PRG:0DC7 10 06
|
|
lda #$0F ; CPU:$CDC9 PRG:0DC9 A9 0F
|
|
sta $29 ; CPU:$CDCB PRG:0DCB 85 29
|
|
dec $28 ; CPU:$CDCD PRG:0DCD C6 28
|
|
; Routine: Frame_HandleControl_CDCF
|
|
; Global: Reachable code entry at CPU $CDCF traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_HandleControl_CDCF:
|
|
lda #$00 ; CPU:$CDCF PRG:0DCF A9 00
|
|
jmp Frame_WriteZp2D_CE06 ; CPU:$CDD1 PRG:0DD1 4C 06 CE
|
|
; Routine: Frame_ReadObjectX_CDD4
|
|
; Global: Reachable code entry at CPU $CDD4 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReadObjectX_CDD4:
|
|
lda $29 ; CPU:$CDD4 PRG:0DD4 A5 29
|
|
cmp #$08 ; CPU:$CDD6 PRG:0DD6 C9 08
|
|
bcs Frame_ReadObjectState_CDDF ; CPU:$CDD8 PRG:0DD8 B0 05
|
|
inc $29 ; CPU:$CDDA PRG:0DDA E6 29
|
|
jmp Frame_HandleControl_CE04 ; CPU:$CDDC PRG:0DDC 4C 04 CE
|
|
; Routine: Frame_ReadObjectState_CDDF
|
|
; Global: Reachable code entry at CPU $CDDF traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReadObjectState_CDDF:
|
|
ldy $2A ; CPU:$CDDF PRG:0DDF A4 2A
|
|
lda $E2A3,y ; CPU:$CDE1 PRG:0DE1 B9 A3 E2
|
|
sta $34 ; CPU:$CDE4 PRG:0DE4 85 34
|
|
lda $E2B0,y ; CPU:$CDE6 PRG:0DE6 B9 B0 E2
|
|
sta $35 ; CPU:$CDE9 PRG:0DE9 85 35
|
|
ldy $28 ; CPU:$CDEB PRG:0DEB A4 28
|
|
iny ; CPU:$CDED PRG:0DED C8
|
|
jsr Object_ReadTransferPointer_CF60 ; CPU:$CDEE PRG:0DEE 20 60 CF
|
|
bne Frame_HandleControl_CE04 ; CPU:$CDF1 PRG:0DF1 D0 11
|
|
jsr Frame_ReadObjectY_CE1F ; CPU:$CDF3 PRG:0DF3 20 1F CE
|
|
inc $29 ; CPU:$CDF6 PRG:0DF6 E6 29
|
|
lda $29 ; CPU:$CDF8 PRG:0DF8 A5 29
|
|
cmp #$10 ; CPU:$CDFA PRG:0DFA C9 10
|
|
bne Frame_HandleControl_CE04 ; CPU:$CDFC PRG:0DFC D0 06
|
|
lda #$00 ; CPU:$CDFE PRG:0DFE A9 00
|
|
sta $29 ; CPU:$CE00 PRG:0E00 85 29
|
|
inc $28 ; CPU:$CE02 PRG:0E02 E6 28
|
|
; Routine: Frame_HandleControl_CE04
|
|
; Global: Reachable code entry at CPU $CE04 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_HandleControl_CE04:
|
|
lda #$40 ; CPU:$CE04 PRG:0E04 A9 40
|
|
; Routine: Frame_WriteZp2D_CE06
|
|
; Global: Reachable code entry at CPU $CE06 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_WriteZp2D_CE06:
|
|
sta $2D ; CPU:$CE06 PRG:0E06 85 2D
|
|
lda #$00 ; CPU:$CE08 PRG:0E08 A9 00
|
|
ldy #$03 ; CPU:$CE0A PRG:0E0A A0 03
|
|
jmp Frame_ReadZp33_CE2E ; CPU:$CE0C PRG:0E0C 4C 2E CE
|
|
|
|
; Data region: CPU $CE0F-$CE0F; unreachable by direct recursive trace.
|
|
FrameSingleByteConstant:
|
|
.byte $60 ; CPU:$CE0F PRG:0E0F 60
|
|
; Routine: Frame_ReadObjectX_CE10
|
|
; Global: Reachable code entry at CPU $CE10 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReadObjectX_CE10:
|
|
lda $29 ; CPU:$CE10 PRG:0E10 A5 29
|
|
cmp #$08 ; CPU:$CE12 PRG:0E12 C9 08
|
|
bcc Frame_IncrementObjectX_CE1B ; CPU:$CE14 PRG:0E14 90 05
|
|
beq Frame_ReturnToCaller_CE1E ; CPU:$CE16 PRG:0E16 F0 06
|
|
dec $29 ; CPU:$CE18 PRG:0E18 C6 29
|
|
rts ; CPU:$CE1A PRG:0E1A 60
|
|
; Routine: Frame_IncrementObjectX_CE1B
|
|
; Global: Reachable code entry at CPU $CE1B traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_IncrementObjectX_CE1B:
|
|
inc $29 ; CPU:$CE1B PRG:0E1B E6 29
|
|
rts ; CPU:$CE1D PRG:0E1D 60
|
|
; Routine: Frame_ReturnToCaller_CE1E
|
|
; Global: Reachable code entry at CPU $CE1E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReturnToCaller_CE1E:
|
|
rts ; CPU:$CE1E PRG:0E1E 60
|
|
; Routine: Frame_ReadObjectY_CE1F
|
|
; Global: Reachable code entry at CPU $CE1F traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReadObjectY_CE1F:
|
|
lda $2B ; CPU:$CE1F PRG:0E1F A5 2B
|
|
cmp #$08 ; CPU:$CE21 PRG:0E21 C9 08
|
|
bcc Frame_IncrementObjectY_CE2A ; CPU:$CE23 PRG:0E23 90 05
|
|
beq Frame_ReturnToCaller_CE2D ; CPU:$CE25 PRG:0E25 F0 06
|
|
dec $2B ; CPU:$CE27 PRG:0E27 C6 2B
|
|
rts ; CPU:$CE29 PRG:0E29 60
|
|
; Routine: Frame_IncrementObjectY_CE2A
|
|
; Global: Reachable code entry at CPU $CE2A traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_IncrementObjectY_CE2A:
|
|
inc $2B ; CPU:$CE2A PRG:0E2A E6 2B
|
|
rts ; CPU:$CE2C PRG:0E2C 60
|
|
; Routine: Frame_ReturnToCaller_CE2D
|
|
; Global: Reachable code entry at CPU $CE2D traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReturnToCaller_CE2D:
|
|
rts ; CPU:$CE2D PRG:0E2D 60
|
|
; Routine: Frame_ReadZp33_CE2E
|
|
; Global: Reachable code entry at CPU $CE2E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReadZp33_CE2E:
|
|
pha ; CPU:$CE2E PRG:0E2E 48
|
|
lda $33 ; CPU:$CE2F PRG:0E2F A5 33
|
|
and #$03 ; CPU:$CE31 PRG:0E31 29 03
|
|
cmp #$02 ; CPU:$CE33 PRG:0E33 C9 02
|
|
bne Frame_RestoreAccumulator_CE59 ; CPU:$CE35 PRG:0E35 D0 22
|
|
lda $33 ; CPU:$CE37 PRG:0E37 A5 33
|
|
pla ; CPU:$CE39 PRG:0E39 68
|
|
inc $A6 ; CPU:$CE3A PRG:0E3A E6 A6
|
|
inc $2C ; CPU:$CE3C PRG:0E3C E6 2C
|
|
cmp $2C ; CPU:$CE3E PRG:0E3E C5 2C
|
|
bcc Frame_TestObjectIndex_CE45 ; CPU:$CE40 PRG:0E40 90 03
|
|
sta $2C ; CPU:$CE42 PRG:0E42 85 2C
|
|
rts ; CPU:$CE44 PRG:0E44 60
|
|
; Routine: Frame_TestObjectIndex_CE45
|
|
; Global: Reachable code entry at CPU $CE45 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_TestObjectIndex_CE45:
|
|
cpy $2C ; CPU:$CE45 PRG:0E45 C4 2C
|
|
bcc Frame_WriteObjectIndex_CE4A ; CPU:$CE47 PRG:0E47 90 01
|
|
rts ; CPU:$CE49 PRG:0E49 60
|
|
; Routine: Frame_WriteObjectIndex_CE4A
|
|
; Global: Reachable code entry at CPU $CE4A traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_WriteObjectIndex_CE4A:
|
|
sta $2C ; CPU:$CE4A PRG:0E4A 85 2C
|
|
cmp #$04 ; CPU:$CE4C PRG:0E4C C9 04
|
|
bcc Frame_HandleControl_CE54 ; CPU:$CE4E PRG:0E4E 90 04
|
|
lda #$02 ; CPU:$CE50 PRG:0E50 A9 02
|
|
bne Frame_WriteSoundCommandState_CE56 ; CPU:$CE52 PRG:0E52 D0 02
|
|
; Routine: Frame_HandleControl_CE54
|
|
; Global: Reachable code entry at CPU $CE54 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_HandleControl_CE54:
|
|
lda #$01 ; CPU:$CE54 PRG:0E54 A9 01
|
|
; Routine: Frame_WriteSoundCommandState_CE56
|
|
; Global: Reachable code entry at CPU $CE56 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_WriteSoundCommandState_CE56:
|
|
sta $DF ; CPU:$CE56 PRG:0E56 85 DF
|
|
rts ; CPU:$CE58 PRG:0E58 60
|
|
; Routine: Frame_RestoreAccumulator_CE59
|
|
; Global: Reachable code entry at CPU $CE59 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_RestoreAccumulator_CE59:
|
|
pla ; CPU:$CE59 PRG:0E59 68
|
|
; Routine: Frame_ReturnToCaller_CE5A
|
|
; Global: Reachable code entry at CPU $CE5A traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReturnToCaller_CE5A:
|
|
rts ; CPU:$CE5A PRG:0E5A 60
|
|
; Routine: Frame_ReadObjectIndex_CE5B
|
|
; Global: Reachable code entry at CPU $CE5B traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReadObjectIndex_CE5B:
|
|
lda $2C ; CPU:$CE5B PRG:0E5B A5 2C
|
|
cmp #$13 ; CPU:$CE5D PRG:0E5D C9 13
|
|
bcs Frame_ReturnToCaller_CE5A ; CPU:$CE5F PRG:0E5F B0 F9
|
|
lda $2D ; CPU:$CE61 PRG:0E61 A5 2D
|
|
sta $3D ; CPU:$CE63 PRG:0E63 85 3D
|
|
ldy #$00 ; CPU:$CE65 PRG:0E65 A0 00
|
|
sty $3C ; CPU:$CE67 PRG:0E67 84 3C
|
|
lda $28 ; CPU:$CE69 PRG:0E69 A5 28
|
|
cmp #$08 ; CPU:$CE6B PRG:0E6B C9 08
|
|
bcc Frame_WriteZp0E_CE80 ; CPU:$CE6D PRG:0E6D 90 11
|
|
ldy #$F0 ; CPU:$CE6F PRG:0E6F A0 F0
|
|
cmp #$17 ; CPU:$CE71 PRG:0E71 C9 17
|
|
bcs Frame_WriteZp0E_CE80 ; CPU:$CE73 PRG:0E73 B0 0B
|
|
asl a ; CPU:$CE75 PRG:0E75 0A
|
|
asl a ; CPU:$CE76 PRG:0E76 0A
|
|
asl a ; CPU:$CE77 PRG:0E77 0A
|
|
asl a ; CPU:$CE78 PRG:0E78 0A
|
|
clc ; CPU:$CE79 PRG:0E79 18
|
|
adc $29 ; CPU:$CE7A PRG:0E7A 65 29
|
|
sec ; CPU:$CE7C PRG:0E7C 38
|
|
sbc #$80 ; CPU:$CE7D PRG:0E7D E9 80
|
|
tay ; CPU:$CE7F PRG:0E7F A8
|
|
; Routine: Frame_WriteZp0E_CE80
|
|
; Global: Reachable code entry at CPU $CE80 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_WriteZp0E_CE80:
|
|
sty $0E ; CPU:$CE80 PRG:0E80 84 0E
|
|
lda $28 ; CPU:$CE82 PRG:0E82 A5 28
|
|
asl a ; CPU:$CE84 PRG:0E84 0A
|
|
asl a ; CPU:$CE85 PRG:0E85 0A
|
|
asl a ; CPU:$CE86 PRG:0E86 0A
|
|
asl a ; CPU:$CE87 PRG:0E87 0A
|
|
clc ; CPU:$CE88 PRG:0E88 18
|
|
adc $29 ; CPU:$CE89 PRG:0E89 65 29
|
|
sec ; CPU:$CE8B PRG:0E8B 38
|
|
sbc #$08 ; CPU:$CE8C PRG:0E8C E9 08
|
|
sbc $0E ; CPU:$CE8E PRG:0E8E E5 0E
|
|
sta $3A ; CPU:$CE90 PRG:0E90 85 3A
|
|
lda $2A ; CPU:$CE92 PRG:0E92 A5 2A
|
|
asl a ; CPU:$CE94 PRG:0E94 0A
|
|
asl a ; CPU:$CE95 PRG:0E95 0A
|
|
asl a ; CPU:$CE96 PRG:0E96 0A
|
|
asl a ; CPU:$CE97 PRG:0E97 0A
|
|
clc ; CPU:$CE98 PRG:0E98 18
|
|
adc $2B ; CPU:$CE99 PRG:0E99 65 2B
|
|
adc #$17 ; CPU:$CE9B PRG:0E9B 69 17
|
|
sta $3B ; CPU:$CE9D PRG:0E9D 85 3B
|
|
ldx $2C ; CPU:$CE9F PRG:0E9F A6 2C
|
|
lda $CED6,x ; CPU:$CEA1 PRG:0EA1 BD D6 CE
|
|
jmp Stage_WriteZp3F_D5F2 ; CPU:$CEA4 PRG:0EA4 4C F2 D5
|
|
; Routine: Frame_ReadZp2D_CEA7
|
|
; Global: Reachable code entry at CPU $CEA7 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_ReadZp2D_CEA7:
|
|
lda $2D ; CPU:$CEA7 PRG:0EA7 A5 2D
|
|
sta $3D ; CPU:$CEA9 PRG:0EA9 85 3D
|
|
ldy #$03 ; CPU:$CEAB PRG:0EAB A0 03
|
|
sty $3C ; CPU:$CEAD PRG:0EAD 84 3C
|
|
lda $28 ; CPU:$CEAF PRG:0EAF A5 28
|
|
asl a ; CPU:$CEB1 PRG:0EB1 0A
|
|
asl a ; CPU:$CEB2 PRG:0EB2 0A
|
|
asl a ; CPU:$CEB3 PRG:0EB3 0A
|
|
asl a ; CPU:$CEB4 PRG:0EB4 0A
|
|
clc ; CPU:$CEB5 PRG:0EB5 18
|
|
adc $29 ; CPU:$CEB6 PRG:0EB6 65 29
|
|
sec ; CPU:$CEB8 PRG:0EB8 38
|
|
sbc #$08 ; CPU:$CEB9 PRG:0EB9 E9 08
|
|
sta $3A ; CPU:$CEBB PRG:0EBB 85 3A
|
|
lda $2A ; CPU:$CEBD PRG:0EBD A5 2A
|
|
asl a ; CPU:$CEBF PRG:0EBF 0A
|
|
asl a ; CPU:$CEC0 PRG:0EC0 0A
|
|
asl a ; CPU:$CEC1 PRG:0EC1 0A
|
|
asl a ; CPU:$CEC2 PRG:0EC2 0A
|
|
clc ; CPU:$CEC3 PRG:0EC3 18
|
|
adc $2B ; CPU:$CEC4 PRG:0EC4 65 2B
|
|
adc #$17 ; CPU:$CEC6 PRG:0EC6 69 17
|
|
sta $3B ; CPU:$CEC8 PRG:0EC8 85 3B
|
|
ldx $2C ; CPU:$CECA PRG:0ECA A6 2C
|
|
lda $CED2,x ; CPU:$CECC PRG:0ECC BD D2 CE
|
|
jmp Stage_WriteZp3F_D5F2 ; CPU:$CECF PRG:0ECF 4C F2 D5
|
|
|
|
; Data region: CPU $CED2-$CEE8; unreachable by direct recursive trace.
|
|
FrameObjectOffsetTable:
|
|
.byte $10, $11, $12, $11, $00, $01, $02, $01, $03, $04, $05, $04, $06, $07, $08, $07 ; CPU:$CED2 PRG:0ED2 10 11 12 11 00 01 02 01 03 04 05 04 06 07 08 07
|
|
.byte $09, $0A, $0B, $0C, $0D, $0E, $0F ; CPU:$CEE2 PRG:0EE2 09 0A 0B 0C 0D 0E 0F
|
|
; Routine: Frame_WriteSoundCommandState_CEE9
|
|
; Global: Reachable code entry at CPU $CEE9 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Frame_WriteSoundCommandState_CEE9:
|
|
lda #$04 ; CPU:$CEE9 PRG:0EE9 A9 04
|
|
sta $DF ; CPU:$CEEB PRG:0EEB 85 DF
|
|
lda #$0A ; CPU:$CEED PRG:0EED A9 0A
|
|
jsr Menu_WriteObjectWorkX_DD83 ; CPU:$CEEF PRG:0EEF 20 83 DD
|
|
ldx $5B ; CPU:$CEF2 PRG:0EF2 A6 5B
|
|
dex ; CPU:$CEF4 PRG:0EF4 CA
|
|
beq Object_ReadObjectTimer_CF0D ; CPU:$CEF5 PRG:0EF5 F0 16
|
|
dex ; CPU:$CEF7 PRG:0EF7 CA
|
|
beq Object_ReadObjectMode_CF1A ; CPU:$CEF8 PRG:0EF8 F0 20
|
|
dex ; CPU:$CEFA PRG:0EFA CA
|
|
beq Object_WriteObjectFlags_CF2A ; CPU:$CEFB PRG:0EFB F0 2D
|
|
dex ; CPU:$CEFD PRG:0EFD CA
|
|
beq Object_WriteObjectPhase_CF33 ; CPU:$CEFE PRG:0EFE F0 33
|
|
dex ; CPU:$CF00 PRG:0F00 CA
|
|
beq Object_WriteObjectSubtype_CF3C ; CPU:$CF01 PRG:0F01 F0 39
|
|
dex ; CPU:$CF03 PRG:0F03 CA
|
|
beq Object_WriteObjectDirection_CF45 ; CPU:$CF04 PRG:0F04 F0 3F
|
|
dex ; CPU:$CF06 PRG:0F06 CA
|
|
beq Object_WriteObjectSpeed_CF4E ; CPU:$CF07 PRG:0F07 F0 45
|
|
dex ; CPU:$CF09 PRG:0F09 CA
|
|
beq Object_WriteObjectCounter_CF57 ; CPU:$CF0A PRG:0F0A F0 4B
|
|
rts ; CPU:$CF0C PRG:0F0C 60
|
|
; Routine: Object_ReadObjectTimer_CF0D
|
|
; Global: Reachable code entry at CPU $CF0D traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_ReadObjectTimer_CF0D:
|
|
lda $74 ; CPU:$CF0D PRG:0F0D A5 74
|
|
cmp #$09 ; CPU:$CF0F PRG:0F0F C9 09
|
|
beq Object_WriteGameMode_CF15 ; CPU:$CF11 PRG:0F11 F0 02
|
|
inc $74 ; CPU:$CF13 PRG:0F13 E6 74
|
|
; Routine: Object_WriteGameMode_CF15
|
|
; Global: Reachable code entry at CPU $CF15 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_WriteGameMode_CF15:
|
|
lda #$04 ; CPU:$CF15 PRG:0F15 A9 04
|
|
sta $B5 ; CPU:$CF17 PRG:0F17 85 B5
|
|
rts ; CPU:$CF19 PRG:0F19 60
|
|
; Routine: Object_ReadObjectMode_CF1A
|
|
; Global: Reachable code entry at CPU $CF1A traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_ReadObjectMode_CF1A:
|
|
lda $73 ; CPU:$CF1A PRG:0F1A A5 73
|
|
cmp #$50 ; CPU:$CF1C PRG:0F1C C9 50
|
|
beq Object_WriteGameMode_CF25 ; CPU:$CF1E PRG:0F1E F0 05
|
|
clc ; CPU:$CF20 PRG:0F20 18
|
|
adc #$10 ; CPU:$CF21 PRG:0F21 69 10
|
|
sta $73 ; CPU:$CF23 PRG:0F23 85 73
|
|
; Routine: Object_WriteGameMode_CF25
|
|
; Global: Reachable code entry at CPU $CF25 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_WriteGameMode_CF25:
|
|
lda #$04 ; CPU:$CF25 PRG:0F25 A9 04
|
|
sta $B5 ; CPU:$CF27 PRG:0F27 85 B5
|
|
rts ; CPU:$CF29 PRG:0F29 60
|
|
; Routine: Object_WriteObjectFlags_CF2A
|
|
; Global: Reachable code entry at CPU $CF2A traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_WriteObjectFlags_CF2A:
|
|
lda #$01 ; CPU:$CF2A PRG:0F2A A9 01
|
|
sta $75 ; CPU:$CF2C PRG:0F2C 85 75
|
|
lda #$04 ; CPU:$CF2E PRG:0F2E A9 04
|
|
sta $B5 ; CPU:$CF30 PRG:0F30 85 B5
|
|
rts ; CPU:$CF32 PRG:0F32 60
|
|
; Routine: Object_WriteObjectPhase_CF33
|
|
; Global: Reachable code entry at CPU $CF33 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_WriteObjectPhase_CF33:
|
|
lda #$01 ; CPU:$CF33 PRG:0F33 A9 01
|
|
sta $76 ; CPU:$CF35 PRG:0F35 85 76
|
|
lda #$04 ; CPU:$CF37 PRG:0F37 A9 04
|
|
sta $B5 ; CPU:$CF39 PRG:0F39 85 B5
|
|
rts ; CPU:$CF3B PRG:0F3B 60
|
|
; Routine: Object_WriteObjectSubtype_CF3C
|
|
; Global: Reachable code entry at CPU $CF3C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_WriteObjectSubtype_CF3C:
|
|
lda #$01 ; CPU:$CF3C PRG:0F3C A9 01
|
|
sta $77 ; CPU:$CF3E PRG:0F3E 85 77
|
|
lda #$04 ; CPU:$CF40 PRG:0F40 A9 04
|
|
sta $B5 ; CPU:$CF42 PRG:0F42 85 B5
|
|
rts ; CPU:$CF44 PRG:0F44 60
|
|
; Routine: Object_WriteObjectDirection_CF45
|
|
; Global: Reachable code entry at CPU $CF45 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_WriteObjectDirection_CF45:
|
|
lda #$01 ; CPU:$CF45 PRG:0F45 A9 01
|
|
sta $78 ; CPU:$CF47 PRG:0F47 85 78
|
|
lda #$04 ; CPU:$CF49 PRG:0F49 A9 04
|
|
sta $B5 ; CPU:$CF4B PRG:0F4B 85 B5
|
|
rts ; CPU:$CF4D PRG:0F4D 60
|
|
; Routine: Object_WriteObjectSpeed_CF4E
|
|
; Global: Reachable code entry at CPU $CF4E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_WriteObjectSpeed_CF4E:
|
|
lda #$01 ; CPU:$CF4E PRG:0F4E A9 01
|
|
sta $79 ; CPU:$CF50 PRG:0F50 85 79
|
|
lda #$05 ; CPU:$CF52 PRG:0F52 A9 05
|
|
sta $B5 ; CPU:$CF54 PRG:0F54 85 B5
|
|
rts ; CPU:$CF56 PRG:0F56 60
|
|
; Routine: Object_WriteObjectCounter_CF57
|
|
; Global: Reachable code entry at CPU $CF57 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_WriteObjectCounter_CF57:
|
|
lda #$FF ; CPU:$CF57 PRG:0F57 A9 FF
|
|
sta $7A ; CPU:$CF59 PRG:0F59 85 7A
|
|
lda #$05 ; CPU:$CF5B PRG:0F5B A9 05
|
|
sta $B5 ; CPU:$CF5D PRG:0F5D 85 B5
|
|
rts ; CPU:$CF5F PRG:0F5F 60
|
|
; Routine: Object_ReadTransferPointer_CF60
|
|
; Global: Reachable code entry at CPU $CF60 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_ReadTransferPointer_CF60:
|
|
lda ($34),y ; CPU:$CF60 PRG:0F60 B1 34
|
|
beq Object_ReturnToCaller_CF7C ; CPU:$CF62 PRG:0F62 F0 18
|
|
cmp #$08 ; CPU:$CF64 PRG:0F64 C9 08
|
|
beq Object_ReturnToCaller_CF7C ; CPU:$CF66 PRG:0F66 F0 14
|
|
cmp #$06 ; CPU:$CF68 PRG:0F68 C9 06
|
|
beq Object_ReturnToCaller_CF7C ; CPU:$CF6A PRG:0F6A F0 10
|
|
cmp #$02 ; CPU:$CF6C PRG:0F6C C9 02
|
|
beq Object_ReadObjectPhase_CF7D ; CPU:$CF6E PRG:0F6E F0 0D
|
|
cmp #$04 ; CPU:$CF70 PRG:0F70 C9 04
|
|
beq Object_ReadObjectPhase_CF7D ; CPU:$CF72 PRG:0F72 F0 09
|
|
cmp #$05 ; CPU:$CF74 PRG:0F74 C9 05
|
|
beq Object_ReadObjectPhase_CF7D ; CPU:$CF76 PRG:0F76 F0 05
|
|
cmp #$03 ; CPU:$CF78 PRG:0F78 C9 03
|
|
beq Object_ReadObjectDirection_CF82 ; CPU:$CF7A PRG:0F7A F0 06
|
|
; Routine: Object_ReturnToCaller_CF7C
|
|
; Global: Reachable code entry at CPU $CF7C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_ReturnToCaller_CF7C:
|
|
rts ; CPU:$CF7C PRG:0F7C 60
|
|
; Routine: Object_ReadObjectPhase_CF7D
|
|
; Global: Reachable code entry at CPU $CF7D traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_ReadObjectPhase_CF7D:
|
|
lda $76 ; CPU:$CF7D PRG:0F7D A5 76
|
|
eor #$01 ; CPU:$CF7F PRG:0F7F 49 01
|
|
rts ; CPU:$CF81 PRG:0F81 60
|
|
; Routine: Object_ReadObjectDirection_CF82
|
|
; Global: Reachable code entry at CPU $CF82 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_ReadObjectDirection_CF82:
|
|
lda $78 ; CPU:$CF82 PRG:0F82 A5 78
|
|
eor #$01 ; CPU:$CF84 PRG:0F84 49 01
|
|
rts ; CPU:$CF86 PRG:0F86 60
|
|
; Routine: Object_ReadGameState_CF87
|
|
; Global: Reachable code entry at CPU $CF87 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_ReadGameState_CF87:
|
|
lda $59 ; CPU:$CF87 PRG:0F87 A5 59
|
|
beq Object_MergeZp13_CFA4 ; CPU:$CF89 PRG:0F89 F0 19
|
|
lda $AF ; CPU:$CF8B PRG:0F8B A5 AF
|
|
dec $AE ; CPU:$CF8D PRG:0F8D C6 AE
|
|
bne Object_ReturnToCaller_CFA3 ; CPU:$CF8F PRG:0F8F D0 12
|
|
pha ; CPU:$CF91 PRG:0F91 48
|
|
ldy #$00 ; CPU:$CF92 PRG:0F92 A0 00
|
|
lda ($AC),y ; CPU:$CF94 PRG:0F94 B1 AC
|
|
sta $AE ; CPU:$CF96 PRG:0F96 85 AE
|
|
jsr Object_IncrementZpAC_CFA9 ; CPU:$CF98 PRG:0F98 20 A9 CF
|
|
lda ($AC),y ; CPU:$CF9B PRG:0F9B B1 AC
|
|
sta $AF ; CPU:$CF9D PRG:0F9D 85 AF
|
|
jsr Object_IncrementZpAC_CFA9 ; CPU:$CF9F PRG:0F9F 20 A9 CF
|
|
pla ; CPU:$CFA2 PRG:0FA2 68
|
|
; Routine: Object_ReturnToCaller_CFA3
|
|
; Global: Reachable code entry at CPU $CFA3 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_ReturnToCaller_CFA3:
|
|
rts ; CPU:$CFA3 PRG:0FA3 60
|
|
; Routine: Object_MergeZp13_CFA4
|
|
; Global: Reachable code entry at CPU $CFA4 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_MergeZp13_CFA4:
|
|
lda ControllerState1 ; CPU:$CFA4 PRG:0FA4 A5 12
|
|
ora $13 ; CPU:$CFA6 PRG:0FA6 05 13
|
|
rts ; CPU:$CFA8 PRG:0FA8 60
|
|
; Routine: Object_IncrementZpAC_CFA9
|
|
; Global: Reachable code entry at CPU $CFA9 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_IncrementZpAC_CFA9:
|
|
inc $AC ; CPU:$CFA9 PRG:0FA9 E6 AC
|
|
bne Object_ReturnToCaller_CFAF ; CPU:$CFAB PRG:0FAB D0 02
|
|
inc $AD ; CPU:$CFAD PRG:0FAD E6 AD
|
|
; Routine: Object_ReturnToCaller_CFAF
|
|
; Global: Reachable code entry at CPU $CFAF traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_ReturnToCaller_CFAF:
|
|
rts ; CPU:$CFAF PRG:0FAF 60
|
|
; Routine: Object_WriteStageProgress_CFB0
|
|
; Global: Reachable code entry at CPU $CFB0 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_WriteStageProgress_CFB0:
|
|
lda #$00 ; CPU:$CFB0 PRG:0FB0 A9 00
|
|
sta $9C ; CPU:$CFB2 PRG:0FB2 85 9C
|
|
lda #$C0 ; CPU:$CFB4 PRG:0FB4 A9 C0
|
|
sta $6B ; CPU:$CFB6 PRG:0FB6 85 6B
|
|
ldx #$09 ; CPU:$CFB8 PRG:0FB8 A2 09
|
|
; Routine: Object_ReadRam0576_CFBA
|
|
; Global: Reachable code entry at CPU $CFBA traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_ReadRam0576_CFBA:
|
|
lda $0576,x ; CPU:$CFBA PRG:0FBA BD 76 05
|
|
beq Object_RetreatIndexX_CFE9 ; CPU:$CFBD PRG:0FBD F0 2A
|
|
cmp #$09 ; CPU:$CFBF PRG:0FBF C9 09
|
|
bcs Object_ReadRam05B2_CFC5 ; CPU:$CFC1 PRG:0FC1 B0 02
|
|
inc $9C ; CPU:$CFC3 PRG:0FC3 E6 9C
|
|
; Routine: Object_ReadRam05B2_CFC5
|
|
; Global: Reachable code entry at CPU $CFC5 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_ReadRam05B2_CFC5:
|
|
ldy $05B2,x ; CPU:$CFC5 PRG:0FC5 BC B2 05
|
|
beq Object_ReadRamD245_CFCF ; CPU:$CFC8 PRG:0FC8 F0 05
|
|
dec $05B2,x ; CPU:$CFCA PRG:0FCA DE B2 05
|
|
bne Object_RetreatIndexX_CFE9 ; CPU:$CFCD PRG:0FCD D0 1A
|
|
; Routine: Object_ReadRamD245_CFCF
|
|
; Global: Reachable code entry at CPU $CFCF traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_ReadRamD245_CFCF:
|
|
asl a ; CPU:$CFCF PRG:0FCF 0A
|
|
tay ; CPU:$CFD0 PRG:0FD0 A8
|
|
jsr Object_WriteZp4D_D1C8 ; CPU:$CFD1 PRG:0FD1 20 C8 D1
|
|
lda #$CF ; CPU:$CFD4 PRG:0FD4 A9 CF
|
|
pha ; CPU:$CFD6 PRG:0FD6 48
|
|
lda #$E2 ; CPU:$CFD7 PRG:0FD7 A9 E2
|
|
pha ; CPU:$CFD9 PRG:0FD9 48
|
|
lda $D245,y ; CPU:$CFDA PRG:0FDA B9 45 D2
|
|
pha ; CPU:$CFDD PRG:0FDD 48
|
|
lda $D244,y ; CPU:$CFDE PRG:0FDE B9 44 D2
|
|
pha ; CPU:$CFE1 PRG:0FE1 48
|
|
rts ; CPU:$CFE2 PRG:0FE2 60
|
|
|
|
; Data region: CPU $CFE3-$CFE8; unreachable by direct recursive trace.
|
|
ObjectPositionLimitTable:
|
|
.byte $20, $07, $D2, $20, $06, $D0 ; CPU:$CFE3 PRG:0FE3 20 07 D2 20 06 D0
|
|
; Routine: Object_RetreatIndexX_CFE9
|
|
; Global: Reachable code entry at CPU $CFE9 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_RetreatIndexX_CFE9:
|
|
dex ; CPU:$CFE9 PRG:0FE9 CA
|
|
bpl Object_ReadRam0576_CFBA ; CPU:$CFEA PRG:0FEA 10 CE
|
|
; Routine: Object_ReturnToCaller_CFEC
|
|
; Global: Reachable code entry at CPU $CFEC traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_ReturnToCaller_CFEC:
|
|
rts ; CPU:$CFEC PRG:0FEC 60
|
|
; Routine: Object_ReadStageIndex_CFED
|
|
; Global: Reachable code entry at CPU $CFED traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_ReadStageIndex_CFED:
|
|
lda $9D ; CPU:$CFED PRG:0FED A5 9D
|
|
clc ; CPU:$CFEF PRG:0FEF 18
|
|
adc #$2C ; CPU:$CFF0 PRG:0FF0 69 2C
|
|
sta $46 ; CPU:$CFF2 PRG:0FF2 85 46
|
|
lda $AA ; CPU:$CFF4 PRG:0FF4 A5 AA
|
|
sta $42 ; CPU:$CFF6 PRG:0FF6 85 42
|
|
lda $AB ; CPU:$CFF8 PRG:0FF8 A5 AB
|
|
sta $44 ; CPU:$CFFA PRG:0FFA 85 44
|
|
lda #$08 ; CPU:$CFFC PRG:0FFC A9 08
|
|
sta $43 ; CPU:$CFFE PRG:0FFE 85 43
|
|
sta $45 ; CPU:$D000 PRG:1000 85 45
|
|
lda #$00 ; CPU:$D002 PRG:1002 A9 00
|
|
beq Object_WriteZp3D_D010 ; CPU:$D004 PRG:1004 F0 0A
|
|
lda $41 ; CPU:$D006 PRG:1006 A5 41
|
|
beq Object_ReturnToCaller_CFEC ; CPU:$D008 PRG:1008 F0 E2
|
|
cmp #$0B ; CPU:$D00A PRG:100A C9 0B
|
|
beq Object_WriteZp3D_D08C ; CPU:$D00C PRG:100C F0 7E
|
|
lda $48 ; CPU:$D00E PRG:100E A5 48
|
|
; Routine: Object_WriteZp3D_D010
|
|
; Global: Reachable code entry at CPU $D010 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_WriteZp3D_D010:
|
|
sta $3D ; CPU:$D010 PRG:1010 85 3D
|
|
ldy #$00 ; CPU:$D012 PRG:1012 A0 00
|
|
sty $50 ; CPU:$D014 PRG:1014 84 50
|
|
lda $42 ; CPU:$D016 PRG:1016 A5 42
|
|
asl a ; CPU:$D018 PRG:1018 0A
|
|
asl a ; CPU:$D019 PRG:1019 0A
|
|
asl a ; CPU:$D01A PRG:101A 0A
|
|
asl a ; CPU:$D01B PRG:101B 0A
|
|
rol $50 ; CPU:$D01C PRG:101C 26 50
|
|
clc ; CPU:$D01E PRG:101E 18
|
|
adc $43 ; CPU:$D01F PRG:101F 65 43
|
|
sta $4F ; CPU:$D021 PRG:1021 85 4F
|
|
lda $50 ; CPU:$D023 PRG:1023 A5 50
|
|
adc #$00 ; CPU:$D025 PRG:1025 69 00
|
|
sta $50 ; CPU:$D027 PRG:1027 85 50
|
|
lda $4F ; CPU:$D029 PRG:1029 A5 4F
|
|
sec ; CPU:$D02B PRG:102B 38
|
|
sbc #$08 ; CPU:$D02C PRG:102C E9 08
|
|
sta $4F ; CPU:$D02E PRG:102E 85 4F
|
|
lda $50 ; CPU:$D030 PRG:1030 A5 50
|
|
sbc #$00 ; CPU:$D032 PRG:1032 E9 00
|
|
sta $50 ; CPU:$D034 PRG:1034 85 50
|
|
lda $4F ; CPU:$D036 PRG:1036 A5 4F
|
|
sec ; CPU:$D038 PRG:1038 38
|
|
sbc $0E ; CPU:$D039 PRG:1039 E5 0E
|
|
sta $4F ; CPU:$D03B PRG:103B 85 4F
|
|
lda $50 ; CPU:$D03D PRG:103D A5 50
|
|
sbc #$00 ; CPU:$D03F PRG:103F E9 00
|
|
bne Object_ReturnToCaller_D08B ; CPU:$D041 PRG:1041 D0 48
|
|
lda $4F ; CPU:$D043 PRG:1043 A5 4F
|
|
cmp #$F8 ; CPU:$D045 PRG:1045 C9 F8
|
|
bcs Object_ReturnToCaller_D08B ; CPU:$D047 PRG:1047 B0 42
|
|
sta $3A ; CPU:$D049 PRG:1049 85 3A
|
|
lda $44 ; CPU:$D04B PRG:104B A5 44
|
|
asl a ; CPU:$D04D PRG:104D 0A
|
|
asl a ; CPU:$D04E PRG:104E 0A
|
|
asl a ; CPU:$D04F PRG:104F 0A
|
|
asl a ; CPU:$D050 PRG:1050 0A
|
|
clc ; CPU:$D051 PRG:1051 18
|
|
adc $45 ; CPU:$D052 PRG:1052 65 45
|
|
adc #$17 ; CPU:$D054 PRG:1054 69 17
|
|
sta $3B ; CPU:$D056 PRG:1056 85 3B
|
|
ldy $46 ; CPU:$D058 PRG:1058 A4 46
|
|
lda $D186,y ; CPU:$D05A PRG:105A B9 86 D1
|
|
sta $3C ; CPU:$D05D PRG:105D 85 3C
|
|
lda $D154,y ; CPU:$D05F PRG:105F B9 54 D1
|
|
jsr Stage_WriteZp3F_D5F2 ; CPU:$D062 PRG:1062 20 F2 D5
|
|
lda $46 ; CPU:$D065 PRG:1065 A5 46
|
|
cmp #$20 ; CPU:$D067 PRG:1067 C9 20
|
|
bcs Object_ReturnToCaller_D08B ; CPU:$D069 PRG:1069 B0 20
|
|
lda $5C ; CPU:$D06B PRG:106B A5 5C
|
|
bne Object_ReturnToCaller_D08B ; CPU:$D06D PRG:106D D0 1C
|
|
lda $7A ; CPU:$D06F PRG:106F A5 7A
|
|
bne Object_ReturnToCaller_D08B ; CPU:$D071 PRG:1071 D0 18
|
|
lda $42 ; CPU:$D073 PRG:1073 A5 42
|
|
cmp $28 ; CPU:$D075 PRG:1075 C5 28
|
|
bne Object_ReturnToCaller_D08B ; CPU:$D077 PRG:1077 D0 12
|
|
lda $44 ; CPU:$D079 PRG:1079 A5 44
|
|
cmp $2A ; CPU:$D07B PRG:107B C5 2A
|
|
bne Object_ReturnToCaller_D08B ; CPU:$D07D PRG:107D D0 0C
|
|
lda #$05 ; CPU:$D07F PRG:107F A9 05
|
|
sta $DF ; CPU:$D081 PRG:1081 85 DF
|
|
lda #$01 ; CPU:$D083 PRG:1083 A9 01
|
|
sta $5C ; CPU:$D085 PRG:1085 85 5C
|
|
lda #$0C ; CPU:$D087 PRG:1087 A9 0C
|
|
sta $2C ; CPU:$D089 PRG:1089 85 2C
|
|
; Routine: Object_ReturnToCaller_D08B
|
|
; Global: Reachable code entry at CPU $D08B traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_ReturnToCaller_D08B:
|
|
rts ; CPU:$D08B PRG:108B 60
|
|
; Routine: Object_WriteZp3D_D08C
|
|
; Global: Reachable code entry at CPU $D08C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_WriteZp3D_D08C:
|
|
txa ; CPU:$D08C PRG:108C 8A
|
|
pha ; CPU:$D08D PRG:108D 48
|
|
lda #$00 ; CPU:$D08E PRG:108E A9 00
|
|
sta $3D ; CPU:$D090 PRG:1090 85 3D
|
|
ldy #$00 ; CPU:$D092 PRG:1092 A0 00
|
|
sty $50 ; CPU:$D094 PRG:1094 84 50
|
|
lda $42 ; CPU:$D096 PRG:1096 A5 42
|
|
asl a ; CPU:$D098 PRG:1098 0A
|
|
asl a ; CPU:$D099 PRG:1099 0A
|
|
asl a ; CPU:$D09A PRG:109A 0A
|
|
asl a ; CPU:$D09B PRG:109B 0A
|
|
rol $50 ; CPU:$D09C PRG:109C 26 50
|
|
clc ; CPU:$D09E PRG:109E 18
|
|
adc $43 ; CPU:$D09F PRG:109F 65 43
|
|
sta $4F ; CPU:$D0A1 PRG:10A1 85 4F
|
|
lda $50 ; CPU:$D0A3 PRG:10A3 A5 50
|
|
adc #$00 ; CPU:$D0A5 PRG:10A5 69 00
|
|
sta $50 ; CPU:$D0A7 PRG:10A7 85 50
|
|
lda $4F ; CPU:$D0A9 PRG:10A9 A5 4F
|
|
sec ; CPU:$D0AB PRG:10AB 38
|
|
sbc #$08 ; CPU:$D0AC PRG:10AC E9 08
|
|
sta $4F ; CPU:$D0AE PRG:10AE 85 4F
|
|
lda $50 ; CPU:$D0B0 PRG:10B0 A5 50
|
|
sbc #$00 ; CPU:$D0B2 PRG:10B2 E9 00
|
|
sta $50 ; CPU:$D0B4 PRG:10B4 85 50
|
|
lda $4F ; CPU:$D0B6 PRG:10B6 A5 4F
|
|
sec ; CPU:$D0B8 PRG:10B8 38
|
|
sbc $0E ; CPU:$D0B9 PRG:10B9 E5 0E
|
|
sta $4F ; CPU:$D0BB PRG:10BB 85 4F
|
|
lda $50 ; CPU:$D0BD PRG:10BD A5 50
|
|
sbc #$00 ; CPU:$D0BF PRG:10BF E9 00
|
|
bne Object_RestoreAccumulator_D0F7 ; CPU:$D0C1 PRG:10C1 D0 34
|
|
lda $4F ; CPU:$D0C3 PRG:10C3 A5 4F
|
|
cmp #$F8 ; CPU:$D0C5 PRG:10C5 C9 F8
|
|
bcs Object_RestoreAccumulator_D0F7 ; CPU:$D0C7 PRG:10C7 B0 2E
|
|
sta $3A ; CPU:$D0C9 PRG:10C9 85 3A
|
|
lda $44 ; CPU:$D0CB PRG:10CB A5 44
|
|
asl a ; CPU:$D0CD PRG:10CD 0A
|
|
asl a ; CPU:$D0CE PRG:10CE 0A
|
|
asl a ; CPU:$D0CF PRG:10CF 0A
|
|
asl a ; CPU:$D0D0 PRG:10D0 0A
|
|
clc ; CPU:$D0D1 PRG:10D1 18
|
|
adc $45 ; CPU:$D0D2 PRG:10D2 65 45
|
|
adc #$1B ; CPU:$D0D4 PRG:10D4 69 1B
|
|
sta $3B ; CPU:$D0D6 PRG:10D6 85 3B
|
|
lda $4B ; CPU:$D0D8 PRG:10D8 A5 4B
|
|
clc ; CPU:$D0DA PRG:10DA 18
|
|
adc $4A ; CPU:$D0DB PRG:10DB 65 4A
|
|
cmp #$10 ; CPU:$D0DD PRG:10DD C9 10
|
|
bcc Object_WriteObjectWorkX_D0E3 ; CPU:$D0DF PRG:10DF 90 02
|
|
lda #$10 ; CPU:$D0E1 PRG:10E1 A9 10
|
|
; Routine: Object_WriteObjectWorkX_D0E3
|
|
; Global: Reachable code entry at CPU $D0E3 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_WriteObjectWorkX_D0E3:
|
|
sta $24 ; CPU:$D0E3 PRG:10E3 85 24
|
|
asl a ; CPU:$D0E5 PRG:10E5 0A
|
|
clc ; CPU:$D0E6 PRG:10E6 18
|
|
adc $24 ; CPU:$D0E7 PRG:10E7 65 24
|
|
tax ; CPU:$D0E9 PRG:10E9 AA
|
|
ldy $6B ; CPU:$D0EA PRG:10EA A4 6B
|
|
jsr Object_ReadRamD121_D0FA ; CPU:$D0EC PRG:10EC 20 FA D0
|
|
jsr Object_ReadRamD121_D0FA ; CPU:$D0EF PRG:10EF 20 FA D0
|
|
jsr Object_ReadRamD121_D0FA ; CPU:$D0F2 PRG:10F2 20 FA D0
|
|
sty $6B ; CPU:$D0F5 PRG:10F5 84 6B
|
|
; Routine: Object_RestoreAccumulator_D0F7
|
|
; Global: Reachable code entry at CPU $D0F7 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_RestoreAccumulator_D0F7:
|
|
pla ; CPU:$D0F7 PRG:10F7 68
|
|
tax ; CPU:$D0F8 PRG:10F8 AA
|
|
rts ; CPU:$D0F9 PRG:10F9 60
|
|
; Routine: Object_ReadRamD121_D0FA
|
|
; Global: Reachable code entry at CPU $D0FA traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_ReadRamD121_D0FA:
|
|
lda $D121,x ; CPU:$D0FA PRG:10FA BD 21 D1
|
|
beq Object_AdvanceIndexX_D11C ; CPU:$D0FD PRG:10FD F0 1D
|
|
pha ; CPU:$D0FF PRG:10FF 48
|
|
lda $3B ; CPU:$D100 PRG:1100 A5 3B
|
|
sta $0700,y ; CPU:$D102 PRG:1102 99 00 07
|
|
iny ; CPU:$D105 PRG:1105 C8
|
|
pla ; CPU:$D106 PRG:1106 68
|
|
sta $0700,y ; CPU:$D107 PRG:1107 99 00 07
|
|
iny ; CPU:$D10A PRG:110A C8
|
|
lda #$01 ; CPU:$D10B PRG:110B A9 01
|
|
sta $0700,y ; CPU:$D10D PRG:110D 99 00 07
|
|
iny ; CPU:$D110 PRG:1110 C8
|
|
lda $3A ; CPU:$D111 PRG:1111 A5 3A
|
|
sta $0700,y ; CPU:$D113 PRG:1113 99 00 07
|
|
iny ; CPU:$D116 PRG:1116 C8
|
|
clc ; CPU:$D117 PRG:1117 18
|
|
adc #$08 ; CPU:$D118 PRG:1118 69 08
|
|
sta $3A ; CPU:$D11A PRG:111A 85 3A
|
|
; Routine: Object_AdvanceIndexX_D11C
|
|
; Global: Reachable code entry at CPU $D11C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_AdvanceIndexX_D11C:
|
|
inx ; CPU:$D11C PRG:111C E8
|
|
iny ; CPU:$D11D PRG:111D C8
|
|
dey ; CPU:$D11E PRG:111E 88
|
|
bne Object_ReturnToCaller_D123 ; CPU:$D11F PRG:111F D0 02
|
|
ldy #$FC ; CPU:$D121 PRG:1121 A0 FC
|
|
; Routine: Object_ReturnToCaller_D123
|
|
; Global: Reachable code entry at CPU $D123 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_ReturnToCaller_D123:
|
|
rts ; CPU:$D123 PRG:1123 60
|
|
|
|
; Data region: CPU $D124-$D1C7; unreachable by direct recursive trace.
|
|
ObjectMovementParameterTable:
|
|
.byte $EC, $46, $00, $ED, $46, $00, $EE, $46, $00, $EF, $46, $00, $FC, $46, $00, $FD ; CPU:$D124 PRG:1124 EC 46 00 ED 46 00 EE 46 00 EF 46 00 FC 46 00 FD
|
|
.byte $46, $00, $FE, $46, $00, $FF, $46, $00, $EC, $46, $46, $ED, $46, $46, $EE, $46 ; CPU:$D134 PRG:1134 46 00 FE 46 00 FF 46 00 EC 46 46 ED 46 46 EE 46
|
|
.byte $46, $EF, $46, $46, $FC, $46, $46, $FD, $46, $46, $FE, $46, $46, $FF, $46, $46 ; CPU:$D144 PRG:1144 46 EF 46 46 FC 46 46 FD 46 46 FE 46 46 FF 46 46
|
|
.byte $18, $19, $1A, $19, $1C, $1D, $1E, $1D, $20, $21, $22, $21, $24, $25, $26, $25 ; CPU:$D154 PRG:1154 18 19 1A 19 1C 1D 1E 1D 20 21 22 21 24 25 26 25
|
|
.byte $28, $29, $2A, $29, $2C, $2D, $2E, $2D, $30, $31, $32, $31, $34, $35, $36, $35 ; CPU:$D164 PRG:1164 28 29 2A 29 2C 2D 2E 2D 30 31 32 31 34 35 36 35
|
|
.byte $1B, $1F, $23, $27, $2B, $2F, $33, $37, $14, $15, $16, $17, $38, $39, $3A, $3B ; CPU:$D174 PRG:1174 1B 1F 23 27 2B 2F 33 37 14 15 16 17 38 39 3A 3B
|
|
.byte $3C, $3D, $01, $01, $01, $01, $03, $03, $03, $03, $02, $02, $02, $02, $01, $01 ; CPU:$D184 PRG:1184 3C 3D 01 01 01 01 03 03 03 03 02 02 02 02 01 01
|
|
.byte $01, $01, $03, $03, $03, $03, $02, $02, $02, $02, $01, $01, $01, $01, $01, $02 ; CPU:$D194 PRG:1194 01 01 03 03 03 03 02 02 02 02 01 01 01 01 01 02
|
|
.byte $01, $02, $01, $03, $02, $01, $03, $02, $01, $01, $01, $01, $01, $01, $01, $00 ; CPU:$D1A4 PRG:11A4 01 02 01 03 02 01 03 02 01 01 01 01 01 01 01 00
|
|
.byte $01, $02, $03, $01, $01, $02, $04, $08, $0A, $14, $28, $50, $64, $C8, $02, $04 ; CPU:$D1B4 PRG:11B4 01 02 03 01 01 02 04 08 0A 14 28 50 64 C8 02 04
|
|
.byte $05, $0A, $14, $28 ; CPU:$D1C4 PRG:11C4 05 0A 14 28
|
|
; Routine: Object_WriteZp4D_D1C8
|
|
; Global: Reachable code entry at CPU $D1C8 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Object_WriteZp4D_D1C8:
|
|
stx $4D ; CPU:$D1C8 PRG:11C8 86 4D
|
|
lda $0576,x ; CPU:$D1CA PRG:11CA BD 76 05
|
|
sta $41 ; CPU:$D1CD PRG:11CD 85 41
|
|
lda $0580,x ; CPU:$D1CF PRG:11CF BD 80 05
|
|
sta $42 ; CPU:$D1D2 PRG:11D2 85 42
|
|
lda $058A,x ; CPU:$D1D4 PRG:11D4 BD 8A 05
|
|
sta $43 ; CPU:$D1D7 PRG:11D7 85 43
|
|
lda $0594,x ; CPU:$D1D9 PRG:11D9 BD 94 05
|
|
sta $44 ; CPU:$D1DC PRG:11DC 85 44
|
|
lda $059E,x ; CPU:$D1DE PRG:11DE BD 9E 05
|
|
sta $45 ; CPU:$D1E1 PRG:11E1 85 45
|
|
lda $05A8,x ; CPU:$D1E3 PRG:11E3 BD A8 05
|
|
sta $46 ; CPU:$D1E6 PRG:11E6 85 46
|
|
lda $05B2,x ; CPU:$D1E8 PRG:11E8 BD B2 05
|
|
sta $47 ; CPU:$D1EB PRG:11EB 85 47
|
|
lda $05BC,x ; CPU:$D1ED PRG:11ED BD BC 05
|
|
sta $48 ; CPU:$D1F0 PRG:11F0 85 48
|
|
lda $05C6,x ; CPU:$D1F2 PRG:11F2 BD C6 05
|
|
sta $49 ; CPU:$D1F5 PRG:11F5 85 49
|
|
lda $05D0,x ; CPU:$D1F7 PRG:11F7 BD D0 05
|
|
sta $4A ; CPU:$D1FA PRG:11FA 85 4A
|
|
lda $05DA,x ; CPU:$D1FC PRG:11FC BD DA 05
|
|
sta $4B ; CPU:$D1FF PRG:11FF 85 4B
|
|
lda $05E4,x ; CPU:$D201 PRG:1201 BD E4 05
|
|
sta $4C ; CPU:$D204 PRG:1204 85 4C
|
|
rts ; CPU:$D206 PRG:1206 60
|
|
|
|
; Data region: CPU $D207-$D5F1; unreachable by direct recursive trace.
|
|
ObjectAndStageLookupTables:
|
|
.byte $A6, $4D, $A5, $41, $9D, $76, $05, $A5, $42, $9D, $80, $05, $A5, $43, $9D, $8A ; CPU:$D207 PRG:1207 A6 4D A5 41 9D 76 05 A5 42 9D 80 05 A5 43 9D 8A
|
|
.byte $05, $A5, $44, $9D, $94, $05, $A5, $45, $9D, $9E, $05, $A5, $46, $9D, $A8, $05 ; CPU:$D217 PRG:1217 05 A5 44 9D 94 05 A5 45 9D 9E 05 A5 46 9D A8 05
|
|
.byte $A5, $47, $9D, $B2, $05, $A5, $48, $9D, $BC, $05, $A5, $49, $9D, $C6, $05, $A5 ; CPU:$D227 PRG:1227 A5 47 9D B2 05 A5 48 9D BC 05 A5 49 9D C6 05 A5
|
|
.byte $4A, $9D, $D0, $05, $A5, $4B, $9D, $DA, $05, $A5, $4C, $9D, $E4, $05, $60, $20 ; CPU:$D237 PRG:1237 4A 9D D0 05 A5 4B 9D DA 05 A5 4C 9D E4 05 60 20
|
|
.byte $D3, $E7, $D2, $C8, $D2, $05, $D3, $B4, $D2, $19, $D3, $A0, $D3, $8A, $D3, $A2 ; CPU:$D247 PRG:1247 D3 E7 D2 C8 D2 05 D3 B4 D2 19 D3 A0 D3 8A D3 A2
|
|
.byte $D2, $64, $D2, $5B, $D2, $C6, $49, $D0, $42, $A9, $00, $85, $41, $60, $C6, $49 ; CPU:$D257 PRG:1257 D2 64 D2 5B D2 C6 49 D0 42 A9 00 85 41 60 C6 49
|
|
.byte $D0, $39, $A9, $0A, $85, $49, $E6, $46, $A5, $46, $C9, $2C, $D0, $2D, $A5, $4B ; CPU:$D267 PRG:1267 D0 39 A9 0A 85 49 E6 46 A5 46 C9 2C D0 2D A5 4B
|
|
.byte $18, $65, $4A, $A8, $C0, $0B, $90, $15, $C0, $10, $90, $02, $A0, $10, $B9, $B7 ; CPU:$D277 PRG:1277 18 65 4A A8 C0 0B 90 15 C0 10 90 02 A0 10 B9 B7
|
|
.byte $D1, $AA, $A9, $C8, $20, $83, $DD, $CA, $D0, $F8, $4C, $9A, $D2, $B9, $B7, $D1 ; CPU:$D287 PRG:1287 D1 AA A9 C8 20 83 DD CA D0 F8 4C 9A D2 B9 B7 D1
|
|
.byte $20, $83, $DD, $A9, $0B, $85, $41, $A9, $64, $85, $49, $60, $C6, $49, $D0, $0C ; CPU:$D297 PRG:1297 20 83 DD A9 0B 85 41 A9 64 85 49 60 C6 49 D0 0C
|
|
.byte $A9, $0A, $85, $41, $A9, $28, $85, $46, $A9, $14, $85, $49, $60, $60, $A9, $10 ; CPU:$D2A7 PRG:12A7 A9 0A 85 41 A9 28 85 46 A9 14 85 49 60 60 A9 10
|
|
.byte $A0, $13, $20, $DA, $D5, $20, $7E, $D3, $A5, $33, $29, $03, $D0, $EF, $4C, $10 ; CPU:$D2B7 PRG:12B7 A0 13 20 DA D5 20 7E D3 A5 33 29 03 D0 EF 4C 10
|
|
.byte $D3, $60, $A9, $08, $A0, $0B, $20, $DA, $D5, $20, $7E, $D3, $A5, $33, $29, $03 ; CPU:$D2C7 PRG:12C7 D3 60 A9 08 A0 0B 20 DA D5 20 7E D3 A5 33 29 03
|
|
.byte $F0, $EF, $C6, $4C, $A5, $4C, $C9, $96, $B0, $03, $20, $26, $D4, $4C, $3F, $D3 ; CPU:$D2D7 PRG:12D7 F0 EF C6 4C A5 4C C9 96 B0 03 20 26 D4 4C 3F D3
|
|
.byte $60, $A9, $04, $A0, $07, $20, $DA, $D5, $20, $7E, $D3, $A5, $33, $29, $03, $F0 ; CPU:$D2E7 PRG:12E7 60 A9 04 A0 07 20 DA D5 20 7E D3 A5 33 29 03 F0
|
|
.byte $EF, $C6, $4C, $A5, $4C, $C9, $96, $B0, $03, $20, $3D, $D4, $4C, $3F, $D3, $A9 ; CPU:$D2F7 PRG:12F7 EF C6 4C A5 4C C9 96 B0 03 20 3D D4 4C 3F D3 A9
|
|
.byte $0C, $A0, $0F, $20, $DA, $D5, $20, $7E, $D3, $C6, $4C, $A5, $4C, $C9, $C8, $4C ; CPU:$D307 PRG:1307 0C A0 0F 20 DA D5 20 7E D3 C6 4C A5 4C C9 C8 4C
|
|
.byte $37, $D3, $60, $A9, $14, $A0, $17, $4C, $25, $D3, $A9, $00, $A0, $03, $20, $DA ; CPU:$D317 PRG:1317 37 D3 60 A9 14 A0 17 4C 25 D3 A9 00 A0 03 20 DA
|
|
.byte $D5, $20, $7E, $D3, $A5, $33, $29, $01, $F0, $E8, $C6, $4C, $A5, $4C, $C9, $14 ; CPU:$D327 PRG:1327 D5 20 7E D3 A5 33 29 01 F0 E8 C6 4C A5 4C C9 14
|
|
.byte $B0, $06, $20, $3D, $D4, $20, $26, $D4, $A5, $49, $F0, $22, $C6, $49, $A5, $4A ; CPU:$D337 PRG:1337 B0 06 20 3D D4 20 26 D4 A5 49 F0 22 C6 49 A5 4A
|
|
.byte $20, $DE, $D4, $F0, $18, $C9, $03, $90, $10, $A4, $4A, $B9, $12, $D4, $85, $4A ; CPU:$D347 PRG:1347 20 DE D4 F0 18 C9 03 90 10 A4 4A B9 12 D4 85 4A
|
|
.byte $A9, $00, $85, $4C, $A9, $60, $85, $49, $60, $A9, $00, $85, $49, $60, $20, $70 ; CPU:$D357 PRG:1357 A9 00 85 4C A9 60 85 49 60 A9 00 85 49 60 20 70
|
|
.byte $D6, $48, $29, $18, $0A, $0A, $18, $69, $20, $85, $49, $68, $2A, $2A, $2A, $29 ; CPU:$D367 PRG:1367 D6 48 29 18 0A 0A 18 69 20 85 49 68 2A 2A 2A 29
|
|
.byte $03, $18, $69, $01, $85, $4A, $60, $A0, $00, $A5, $4A, $C9, $03, $90, $02, $A0 ; CPU:$D377 PRG:1377 03 18 69 01 85 4A 60 A0 00 A5 4A C9 03 90 02 A0
|
|
.byte $40, $84, $48, $60, $A9, $1C, $A0, $1F, $20, $DA, $D5, $A0, $00, $A5, $46, $C9 ; CPU:$D387 PRG:1387 40 84 48 60 A9 1C A0 1F 20 DA D5 A0 00 A5 46 C9
|
|
.byte $1D, $D0, $02, $A0, $40, $84, $48, $4C, $AB, $D3, $A9, $18, $A0, $1B, $20, $DA ; CPU:$D397 PRG:1397 1D D0 02 A0 40 84 48 4C AB D3 A9 18 A0 1B 20 DA
|
|
.byte $D5, $20, $7E, $D3, $A5, $4C, $F0, $05, $C6, $4C, $D0, $07, $60, $20, $3D, $D4 ; CPU:$D3A7 PRG:13A7 D5 20 7E D3 A5 4C F0 05 C6 4C D0 07 60 20 3D D4
|
|
.byte $20, $26, $D4, $A5, $4A, $0A, $05, $4B, $A8, $B9, $17, $D4, $85, $53, $A8, $B9 ; CPU:$D3B7 PRG:13B7 20 26 D4 A5 4A 0A 05 4B A8 B9 17 D4 85 53 A8 B9
|
|
.byte $21, $D4, $85, $52, $20, $54, $D4, $25, $52, $F0, $0E, $A5, $53, $85, $4A, $A9 ; CPU:$D3C7 PRG:13C7 21 D4 85 52 20 54 D4 25 52 F0 0E A5 53 85 4A A9
|
|
.byte $01, $45, $4B, $85, $4B, $A9, $00, $85, $49, $E6, $49, $A5, $49, $C9, $1F, $90 ; CPU:$D3D7 PRG:13D7 01 45 4B 85 4B A9 00 85 49 E6 49 A5 49 C9 1F 90
|
|
.byte $06, $A9, $01, $45, $4B, $85, $4B, $A5, $4A, $20, $DE, $D4, $F0, $10, $C9, $03 ; CPU:$D3E7 PRG:13E7 06 A9 01 45 4B 85 4B A5 4A 20 DE D4 F0 10 C9 03
|
|
.byte $B0, $0D, $E6, $4A, $A5, $4A, $C9, $05, $D0, $04, $A9, $01, $85, $4A, $60, $A9 ; CPU:$D3F7 PRG:13F7 B0 0D E6 4A A5 4A C9 05 D0 04 A9 01 85 4A 60 A9
|
|
.byte $60, $85, $4C, $A4, $4A, $B9, $12, $D4, $85, $4A, $60, $00, $03, $04, $01, $02 ; CPU:$D407 PRG:1407 60 85 4C A4 4A B9 12 D4 85 4A 60 00 03 04 01 02
|
|
.byte $01, $04, $04, $02, $01, $03, $02, $04, $03, $01, $00, $01, $02, $04, $08, $A5 ; CPU:$D417 PRG:1417 01 04 04 02 01 03 02 04 03 01 00 01 02 04 08 A5
|
|
.byte $5C, $D0, $12, $A5, $44, $C5, $2A, $D0, $0C, $A5, $42, $C5, $28, $A9, $01, $90 ; CPU:$D427 PRG:1427 5C D0 12 A5 44 C5 2A D0 0C A5 42 C5 28 A9 01 90
|
|
.byte $02, $A9, $03, $85, $4A, $60, $A5, $5C, $D0, $FB, $A5, $42, $C5, $28, $D0, $0C ; CPU:$D437 PRG:1437 02 A9 03 85 4A 60 A5 5C D0 FB A5 42 C5 28 D0 0C
|
|
.byte $A5, $44, $C5, $2A, $A9, $04, $90, $02, $A9, $02, $85, $4A, $60, $A9, $00, $85 ; CPU:$D447 PRG:1447 A5 44 C5 2A A9 04 90 02 A9 02 85 4A 60 A9 00 85
|
|
.byte $51, $A5, $43, $C9, $08, $D0, $04, $A5, $45, $C9, $08, $D0, $59, $A4, $44, $B9 ; CPU:$D457 PRG:1457 51 A5 43 C9 08 D0 04 A5 45 C9 08 D0 59 A4 44 B9
|
|
.byte $A3, $E2, $85, $34, $B9, $B0, $E2, $85, $35, $A4, $42, $C8, $20, $C0, $D4, $D0 ; CPU:$D467 PRG:1467 A3 E2 85 34 B9 B0 E2 85 35 A4 42 C8 20 C0 D4 D0
|
|
.byte $04, $A9, $01, $85, $51, $88, $88, $20, $C0, $D4, $D0, $06, $A9, $04, $05, $51 ; CPU:$D477 PRG:1477 04 A9 01 85 51 88 88 20 C0 D4 D0 06 A9 04 05 51
|
|
.byte $85, $51, $A4, $44, $88, $B9, $A3, $E2, $85, $34, $B9, $B0, $E2, $85, $35, $A4 ; CPU:$D487 PRG:1487 85 51 A4 44 88 B9 A3 E2 85 34 B9 B0 E2 85 35 A4
|
|
.byte $42, $20, $C0, $D4, $D0, $06, $A9, $02, $05, $51, $85, $51, $A4, $44, $C8, $B9 ; CPU:$D497 PRG:1497 42 20 C0 D4 D0 06 A9 02 05 51 85 51 A4 44 C8 B9
|
|
.byte $A3, $E2, $85, $34, $B9, $B0, $E2, $85, $35, $A4, $42, $20, $C0, $D4, $D0, $06 ; CPU:$D4A7 PRG:14A7 A3 E2 85 34 B9 B0 E2 85 35 A4 42 20 C0 D4 D0 06
|
|
.byte $A9, $08, $05, $51, $85, $51, $A5, $51, $60, $B1, $34, $F0, $FB, $C9, $08, $F0 ; CPU:$D4B7 PRG:14B7 A9 08 05 51 85 51 A5 51 60 B1 34 F0 FB C9 08 F0
|
|
.byte $F7, $C9, $06, $F0, $F3, $C9, $02, $F0, $01, $60, $A5, $41, $C9, $05, $F0, $E8 ; CPU:$D4C7 PRG:14C7 F7 C9 06 F0 F3 C9 02 F0 01 60 A5 41 C9 05 F0 E8
|
|
.byte $C9, $06, $F0, $E4, $C9, $08, $60, $A2, $00, $86, $4E, $AA, $C9, $01, $D0, $03 ; CPU:$D4D7 PRG:14D7 C9 06 F0 E4 C9 08 60 A2 00 86 4E AA C9 01 D0 03
|
|
.byte $20, $8D, $D5, $8A, $C9, $03, $D0, $03, $20, $62, $D5, $8A, $C9, $02, $D0, $03 ; CPU:$D4E7 PRG:14E7 20 8D D5 8A C9 03 D0 03 20 62 D5 8A C9 02 D0 03
|
|
.byte $20, $37, $D5, $8A, $C9, $04, $D0, $03, $20, $05, $D5, $A5, $4E, $60, $A5, $45 ; CPU:$D4F7 PRG:14F7 20 37 D5 8A C9 04 D0 03 20 05 D5 A5 4E 60 A5 45
|
|
.byte $C9, $08, $B0, $03, $E6, $45, $60, $A4, $44, $C8, $B9, $A3, $E2, $85, $34, $B9 ; CPU:$D507 PRG:1507 C9 08 B0 03 E6 45 60 A4 44 C8 B9 A3 E2 85 34 B9
|
|
.byte $B0, $E2, $85, $35, $A4, $42, $20, $C0, $D4, $D0, $12, $20, $BC, $D5, $E6, $45 ; CPU:$D517 PRG:1517 B0 E2 85 35 A4 42 20 C0 D4 D0 12 20 BC D5 E6 45
|
|
.byte $A5, $45, $C9, $10, $D0, $06, $A9, $00, $85, $45, $E6, $44, $60, $85, $4E, $60 ; CPU:$D527 PRG:1527 A5 45 C9 10 D0 06 A9 00 85 45 E6 44 60 85 4E 60
|
|
.byte $A5, $45, $C9, $09, $90, $03, $C6, $45, $60, $A4, $44, $88, $B9, $A3, $E2, $85 ; CPU:$D537 PRG:1537 A5 45 C9 09 90 03 C6 45 60 A4 44 88 B9 A3 E2 85
|
|
.byte $34, $B9, $B0, $E2, $85, $35, $A4, $42, $20, $C0, $D4, $D0, $E0, $20, $BC, $D5 ; CPU:$D547 PRG:1547 34 B9 B0 E2 85 35 A4 42 20 C0 D4 D0 E0 20 BC D5
|
|
.byte $C6, $45, $10, $06, $A9, $0F, $85, $45, $C6, $44, $60, $A5, $43, $C9, $09, $90 ; CPU:$D557 PRG:1557 C6 45 10 06 A9 0F 85 45 C6 44 60 A5 43 C9 09 90
|
|
.byte $03, $C6, $43, $60, $A4, $44, $B9, $A3, $E2, $85, $34, $B9, $B0, $E2, $85, $35 ; CPU:$D567 PRG:1567 03 C6 43 60 A4 44 B9 A3 E2 85 34 B9 B0 E2 85 35
|
|
.byte $A4, $42, $88, $20, $C0, $D4, $D0, $B5, $20, $CB, $D5, $C6, $43, $10, $06, $A9 ; CPU:$D577 PRG:1577 A4 42 88 20 C0 D4 D0 B5 20 CB D5 C6 43 10 06 A9
|
|
.byte $0F, $85, $43, $C6, $42, $60, $A5, $43, $C9, $08, $B0, $03, $E6, $43, $60, $A4 ; CPU:$D587 PRG:1587 0F 85 43 C6 42 60 A5 43 C9 08 B0 03 E6 43 60 A4
|
|
.byte $44, $B9, $A3, $E2, $85, $34, $B9, $B0, $E2, $85, $35, $A4, $42, $C8, $20, $C0 ; CPU:$D597 PRG:1597 44 B9 A3 E2 85 34 B9 B0 E2 85 35 A4 42 C8 20 C0
|
|
.byte $D4, $D0, $8A, $20, $CB, $D5, $E6, $43, $A5, $43, $C9, $10, $D0, $06, $A9, $00 ; CPU:$D5A7 PRG:15A7 D4 D0 8A 20 CB D5 E6 43 A5 43 C9 10 D0 06 A9 00
|
|
.byte $85, $43, $E6, $42, $60, $A5, $43, $C9, $08, $90, $05, $F0, $06, $C6, $43, $60 ; CPU:$D5B7 PRG:15B7 85 43 E6 42 60 A5 43 C9 08 90 05 F0 06 C6 43 60
|
|
.byte $E6, $43, $60, $60, $A5, $45, $C9, $08, $90, $05, $F0, $06, $C6, $45, $60, $E6 ; CPU:$D5C7 PRG:15C7 E6 43 60 60 A5 45 C9 08 90 05 F0 06 C6 45 60 E6
|
|
.byte $45, $60, $60, $48, $A5, $33, $29, $07, $D0, $0F, $68, $E6, $46, $C5, $46, $90 ; CPU:$D5D7 PRG:15D7 45 60 60 48 A5 33 29 07 D0 0F 68 E6 46 C5 46 90
|
|
.byte $03, $85, $46, $60, $C4, $46, $90, $F9, $60, $68, $60 ; CPU:$D5E7 PRG:15E7 03 85 46 60 C4 46 90 F9 60 68 60
|
|
; Routine: Stage_WriteZp3F_D5F2
|
|
; Global: Reachable code entry at CPU $D5F2 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_WriteZp3F_D5F2:
|
|
stx $3F ; CPU:$D5F2 PRG:15F2 86 3F
|
|
sty $40 ; CPU:$D5F4 PRG:15F4 84 40
|
|
asl a ; CPU:$D5F6 PRG:15F6 0A
|
|
pha ; CPU:$D5F7 PRG:15F7 48
|
|
and #$0E ; CPU:$D5F8 PRG:15F8 29 0E
|
|
sta $3E ; CPU:$D5FA PRG:15FA 85 3E
|
|
pla ; CPU:$D5FC PRG:15FC 68
|
|
asl a ; CPU:$D5FD PRG:15FD 0A
|
|
and #$E0 ; CPU:$D5FE PRG:15FE 29 E0
|
|
ora $3E ; CPU:$D600 PRG:1600 05 3E
|
|
sta $3E ; CPU:$D602 PRG:1602 85 3E
|
|
lda $39 ; CPU:$D604 PRG:1604 A5 39
|
|
inc $39 ; CPU:$D606 PRG:1606 E6 39
|
|
clc ; CPU:$D608 PRG:1608 18
|
|
adc $DB ; CPU:$D609 PRG:1609 65 DB
|
|
cmp #$0C ; CPU:$D60B PRG:160B C9 0C
|
|
bcc Stage_ReadZp3D_D611 ; CPU:$D60D PRG:160D 90 02
|
|
sbc #$0A ; CPU:$D60F PRG:160F E9 0A
|
|
; Routine: Stage_ReadZp3D_D611
|
|
; Global: Reachable code entry at CPU $D611 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_ReadZp3D_D611:
|
|
asl a ; CPU:$D611 PRG:1611 0A
|
|
asl a ; CPU:$D612 PRG:1612 0A
|
|
asl a ; CPU:$D613 PRG:1613 0A
|
|
asl a ; CPU:$D614 PRG:1614 0A
|
|
tay ; CPU:$D615 PRG:1615 A8
|
|
lda $3D ; CPU:$D616 PRG:1616 A5 3D
|
|
bne Stage_IncrementZp3E_D622 ; CPU:$D618 PRG:1618 D0 08
|
|
jsr Stage_ReadPositionHi_D631 ; CPU:$D61A PRG:161A 20 31 D6
|
|
inc $3E ; CPU:$D61D PRG:161D E6 3E
|
|
jmp Stage_ReadZp3F_D629 ; CPU:$D61F PRG:161F 4C 29 D6
|
|
; Routine: Stage_IncrementZp3E_D622
|
|
; Global: Reachable code entry at CPU $D622 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_IncrementZp3E_D622:
|
|
inc $3E ; CPU:$D622 PRG:1622 E6 3E
|
|
jsr Stage_ReadPositionHi_D631 ; CPU:$D624 PRG:1624 20 31 D6
|
|
dec $3E ; CPU:$D627 PRG:1627 C6 3E
|
|
; Routine: Stage_ReadZp3F_D629
|
|
; Global: Reachable code entry at CPU $D629 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_ReadZp3F_D629:
|
|
jsr Stage_ReadPositionHi_D631 ; CPU:$D629 PRG:1629 20 31 D6
|
|
ldx $3F ; CPU:$D62C PRG:162C A6 3F
|
|
ldy $40 ; CPU:$D62E PRG:162E A4 40
|
|
rts ; CPU:$D630 PRG:1630 60
|
|
; Routine: Stage_ReadPositionHi_D631
|
|
; Global: Reachable code entry at CPU $D631 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_ReadPositionHi_D631:
|
|
lda $3B ; CPU:$D631 PRG:1631 A5 3B
|
|
sta $0700,y ; CPU:$D633 PRG:1633 99 00 07
|
|
lda $3E ; CPU:$D636 PRG:1636 A5 3E
|
|
pha ; CPU:$D638 PRG:1638 48
|
|
sta $0701,y ; CPU:$D639 PRG:1639 99 01 07
|
|
lda $3C ; CPU:$D63C PRG:163C A5 3C
|
|
ora $3D ; CPU:$D63E PRG:163E 05 3D
|
|
sta $0702,y ; CPU:$D640 PRG:1640 99 02 07
|
|
lda $3A ; CPU:$D643 PRG:1643 A5 3A
|
|
sta $0703,y ; CPU:$D645 PRG:1645 99 03 07
|
|
lda $3B ; CPU:$D648 PRG:1648 A5 3B
|
|
clc ; CPU:$D64A PRG:164A 18
|
|
adc #$08 ; CPU:$D64B PRG:164B 69 08
|
|
sta $0704,y ; CPU:$D64D PRG:164D 99 04 07
|
|
pla ; CPU:$D650 PRG:1650 68
|
|
clc ; CPU:$D651 PRG:1651 18
|
|
adc #$10 ; CPU:$D652 PRG:1652 69 10
|
|
sta $0705,y ; CPU:$D654 PRG:1654 99 05 07
|
|
lda $3C ; CPU:$D657 PRG:1657 A5 3C
|
|
ora $3D ; CPU:$D659 PRG:1659 05 3D
|
|
sta $0706,y ; CPU:$D65B PRG:165B 99 06 07
|
|
lda $3A ; CPU:$D65E PRG:165E A5 3A
|
|
sta $0707,y ; CPU:$D660 PRG:1660 99 07 07
|
|
tya ; CPU:$D663 PRG:1663 98
|
|
clc ; CPU:$D664 PRG:1664 18
|
|
adc #$08 ; CPU:$D665 PRG:1665 69 08
|
|
tay ; CPU:$D667 PRG:1667 A8
|
|
lda $3A ; CPU:$D668 PRG:1668 A5 3A
|
|
clc ; CPU:$D66A PRG:166A 18
|
|
adc #$08 ; CPU:$D66B PRG:166B 69 08
|
|
sta $3A ; CPU:$D66D PRG:166D 85 3A
|
|
rts ; CPU:$D66F PRG:166F 60
|
|
; Routine: AdvanceRandomState
|
|
; Global: Reachable code entry at CPU $D670 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
AdvanceRandomState:
|
|
lda RandomState0 ; CPU:$D670 PRG:1670 A5 54
|
|
rol a ; CPU:$D672 PRG:1672 2A
|
|
rol a ; CPU:$D673 PRG:1673 2A
|
|
eor #$41 ; CPU:$D674 PRG:1674 49 41
|
|
rol a ; CPU:$D676 PRG:1676 2A
|
|
rol a ; CPU:$D677 PRG:1677 2A
|
|
eor #$93 ; CPU:$D678 PRG:1678 49 93
|
|
adc RandomState1 ; CPU:$D67A PRG:167A 65 55
|
|
sta RandomState0 ; CPU:$D67C PRG:167C 85 54
|
|
rol a ; CPU:$D67E PRG:167E 2A
|
|
rol a ; CPU:$D67F PRG:167F 2A
|
|
eor #$12 ; CPU:$D680 PRG:1680 49 12
|
|
rol a ; CPU:$D682 PRG:1682 2A
|
|
rol a ; CPU:$D683 PRG:1683 2A
|
|
adc RandomState2 ; CPU:$D684 PRG:1684 65 56
|
|
sta RandomState1 ; CPU:$D686 PRG:1686 85 55
|
|
adc RandomState0 ; CPU:$D688 PRG:1688 65 54
|
|
inc RandomState2 ; CPU:$D68A PRG:168A E6 56
|
|
bne Stage_ToggleRandomState3_D697 ; CPU:$D68C PRG:168C D0 09
|
|
pha ; CPU:$D68E PRG:168E 48
|
|
lda RandomState3 ; CPU:$D68F PRG:168F A5 57
|
|
clc ; CPU:$D691 PRG:1691 18
|
|
adc #$1D ; CPU:$D692 PRG:1692 69 1D
|
|
sta RandomState3 ; CPU:$D694 PRG:1694 85 57
|
|
pla ; CPU:$D696 PRG:1696 68
|
|
; Routine: Stage_ToggleRandomState3_D697
|
|
; Global: Reachable code entry at CPU $D697 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_ToggleRandomState3_D697:
|
|
eor $57 ; CPU:$D697 PRG:1697 45 57
|
|
rts ; CPU:$D699 PRG:1699 60
|
|
; Routine: Stage_ReadZp58_D69A
|
|
; Global: Reachable code entry at CPU $D69A traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_ReadZp58_D69A:
|
|
lda $58 ; CPU:$D69A PRG:169A A5 58
|
|
cmp #$1A ; CPU:$D69C PRG:169C C9 1A
|
|
bcc Stage_HandleControl_D6A8 ; CPU:$D69E PRG:169E 90 08
|
|
sbc #$19 ; CPU:$D6A0 PRG:16A0 E9 19
|
|
ldx #$02 ; CPU:$D6A2 PRG:16A2 A2 02
|
|
ldy #$D8 ; CPU:$D6A4 PRG:16A4 A0 D8
|
|
bne Stage_WriteZp97_D6AC ; CPU:$D6A6 PRG:16A6 D0 04
|
|
; Routine: Stage_HandleControl_D6A8
|
|
; Global: Reachable code entry at CPU $D6A8 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_HandleControl_D6A8:
|
|
ldx #$08 ; CPU:$D6A8 PRG:16A8 A2 08
|
|
ldy #$D7 ; CPU:$D6AA PRG:16AA A0 D7
|
|
; Routine: Stage_WriteZp97_D6AC
|
|
; Global: Reachable code entry at CPU $D6AC traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_WriteZp97_D6AC:
|
|
stx $97 ; CPU:$D6AC PRG:16AC 86 97
|
|
sty $98 ; CPU:$D6AE PRG:16AE 84 98
|
|
sec ; CPU:$D6B0 PRG:16B0 38
|
|
sbc #$01 ; CPU:$D6B1 PRG:16B1 E9 01
|
|
asl a ; CPU:$D6B3 PRG:16B3 0A
|
|
sta $24 ; CPU:$D6B4 PRG:16B4 85 24
|
|
asl a ; CPU:$D6B6 PRG:16B6 0A
|
|
asl a ; CPU:$D6B7 PRG:16B7 0A
|
|
clc ; CPU:$D6B8 PRG:16B8 18
|
|
adc $24 ; CPU:$D6B9 PRG:16B9 65 24
|
|
tay ; CPU:$D6BB PRG:16BB A8
|
|
ldx #$09 ; CPU:$D6BC PRG:16BC A2 09
|
|
; Routine: Stage_ReadZp97_D6BE
|
|
; Global: Reachable code entry at CPU $D6BE traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_ReadZp97_D6BE:
|
|
lda ($97),y ; CPU:$D6BE PRG:16BE B1 97
|
|
sta $0576,x ; CPU:$D6C0 PRG:16C0 9D 76 05
|
|
beq Stage_AdvanceIndexY_D703 ; CPU:$D6C3 PRG:16C3 F0 3E
|
|
sec ; CPU:$D6C5 PRG:16C5 38
|
|
sbc #$01 ; CPU:$D6C6 PRG:16C6 E9 01
|
|
asl a ; CPU:$D6C8 PRG:16C8 0A
|
|
asl a ; CPU:$D6C9 PRG:16C9 0A
|
|
sta $05A8,x ; CPU:$D6CA PRG:16CA 9D A8 05
|
|
lda #$08 ; CPU:$D6CD PRG:16CD A9 08
|
|
sta $058A,x ; CPU:$D6CF PRG:16CF 9D 8A 05
|
|
sta $059E,x ; CPU:$D6D2 PRG:16D2 9D 9E 05
|
|
jsr AdvanceRandomState ; CPU:$D6D5 PRG:16D5 20 70 D6
|
|
and #$03 ; CPU:$D6D8 PRG:16D8 29 03
|
|
clc ; CPU:$D6DA PRG:16DA 18
|
|
adc #$01 ; CPU:$D6DB PRG:16DB 69 01
|
|
sta $05D0,x ; CPU:$D6DD PRG:16DD 9D D0 05
|
|
sty $5A ; CPU:$D6E0 PRG:16E0 84 5A
|
|
; Routine: Stage_ReadObjectWorkX_D6E2
|
|
; Global: Reachable code entry at CPU $D6E2 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_ReadObjectWorkX_D6E2:
|
|
jsr Gameplay_WriteObjectWorkX_CACF ; CPU:$D6E2 PRG:16E2 20 CF CA
|
|
lda $24 ; CPU:$D6E5 PRG:16E5 A5 24
|
|
cmp #$05 ; CPU:$D6E7 PRG:16E7 C9 05
|
|
bcc Stage_ReadObjectWorkX_D6E2 ; CPU:$D6E9 PRG:16E9 90 F7
|
|
sta $0580,x ; CPU:$D6EB PRG:16EB 9D 80 05
|
|
lda $25 ; CPU:$D6EE PRG:16EE A5 25
|
|
sta $0594,x ; CPU:$D6F0 PRG:16F0 9D 94 05
|
|
lda #$00 ; CPU:$D6F3 PRG:16F3 A9 00
|
|
sta $05B2,x ; CPU:$D6F5 PRG:16F5 9D B2 05
|
|
sta $05DA,x ; CPU:$D6F8 PRG:16F8 9D DA 05
|
|
sta $05C6,x ; CPU:$D6FB PRG:16FB 9D C6 05
|
|
sta $05E4,x ; CPU:$D6FE PRG:16FE 9D E4 05
|
|
ldy $5A ; CPU:$D701 PRG:1701 A4 5A
|
|
; Routine: Stage_AdvanceIndexY_D703
|
|
; Global: Reachable code entry at CPU $D703 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_AdvanceIndexY_D703:
|
|
iny ; CPU:$D703 PRG:1703 C8
|
|
dex ; CPU:$D704 PRG:1704 CA
|
|
bpl Stage_ReadZp97_D6BE ; CPU:$D705 PRG:1705 10 B7
|
|
rts ; CPU:$D707 PRG:1707 60
|
|
|
|
; Data region: CPU $D708-$D8FB; unreachable by direct recursive trace.
|
|
GameplayParameterTables:
|
|
.byte $01, $01, $01, $01, $01, $01, $00, $00, $00, $00, $01, $01, $01, $02, $02, $02 ; CPU:$D708 PRG:1708 01 01 01 01 01 01 00 00 00 00 01 01 01 02 02 02
|
|
.byte $00, $00, $00, $00, $01, $01, $02, $02, $03, $03, $00, $00, $00, $00, $01, $02 ; CPU:$D718 PRG:1718 00 00 00 00 01 01 02 02 03 03 00 00 00 00 01 02
|
|
.byte $03, $03, $04, $04, $00, $00, $00, $00, $02, $02, $02, $02, $03, $03, $03, $00 ; CPU:$D728 PRG:1728 03 03 04 04 00 00 00 00 02 02 02 02 03 03 03 00
|
|
.byte $00, $00, $02, $02, $03, $03, $03, $04, $04, $00, $00, $00, $02, $02, $03, $03 ; CPU:$D738 PRG:1738 00 00 02 02 03 03 03 04 04 00 00 00 02 02 03 03
|
|
.byte $03, $05, $05, $00, $00, $00, $02, $03, $03, $04, $04, $04, $04, $00, $00, $00 ; CPU:$D748 PRG:1748 03 05 05 00 00 00 02 03 03 04 04 04 04 00 00 00
|
|
.byte $02, $03, $04, $04, $04, $04, $06, $00, $00, $00, $02, $03, $04, $05, $06, $06 ; CPU:$D758 PRG:1758 02 03 04 04 04 04 06 00 00 00 02 03 04 05 06 06
|
|
.byte $06, $00, $00, $00, $02, $03, $03, $04, $04, $04, $05, $06, $00, $00, $02, $03 ; CPU:$D768 PRG:1768 06 00 00 00 02 03 03 04 04 04 05 06 00 00 02 03
|
|
.byte $04, $05, $06, $06, $06, $06, $00, $00, $03, $03, $03, $04, $04, $04, $06, $06 ; CPU:$D778 PRG:1778 04 05 06 06 06 06 00 00 03 03 03 04 04 04 06 06
|
|
.byte $00, $00, $05, $05, $05, $05, $05, $05, $05, $07, $00, $00, $03, $04, $04, $04 ; CPU:$D788 PRG:1788 00 00 05 05 05 05 05 05 05 07 00 00 03 04 04 04
|
|
.byte $06, $06, $06, $07, $00, $00, $04, $04, $04, $06, $06, $06, $06, $07, $00, $00 ; CPU:$D798 PRG:1798 06 06 06 07 00 00 04 04 04 06 06 06 06 07 00 00
|
|
.byte $03, $03, $03, $03, $03, $06, $06, $07, $00, $00, $01, $01, $01, $02, $02, $02 ; CPU:$D7A8 PRG:17A8 03 03 03 03 03 06 06 07 00 00 01 01 01 02 02 02
|
|
.byte $07, $07, $00, $00, $01, $02, $03, $03, $03, $05, $07, $07, $00, $00, $02, $03 ; CPU:$D7B8 PRG:17B8 07 07 00 00 01 02 03 03 03 05 07 07 00 00 02 03
|
|
.byte $04, $05, $06, $06, $07, $07, $00, $00, $05, $05, $05, $06, $06, $06, $06, $07 ; CPU:$D7C8 PRG:17C8 04 05 06 06 07 07 00 00 05 05 05 06 06 06 06 07
|
|
.byte $07, $00, $03, $03, $03, $03, $04, $04, $04, $06, $07, $00, $03, $03, $04, $04 ; CPU:$D7D8 PRG:17D8 07 00 03 03 03 03 04 04 04 06 07 00 03 03 04 04
|
|
.byte $05, $05, $06, $06, $07, $00, $03, $04, $05, $06, $06, $05, $06, $06, $07, $00 ; CPU:$D7E8 PRG:17E8 05 05 06 06 07 00 03 04 05 06 06 05 06 06 07 00
|
|
.byte $02, $02, $03, $04, $05, $05, $06, $06, $07, $00, $01, $02, $03, $04, $05, $05 ; CPU:$D7F8 PRG:17F8 02 02 03 04 05 05 06 06 07 00 01 02 03 04 05 05
|
|
.byte $06, $06, $07, $00, $01, $02, $06, $06, $06, $05, $06, $06, $07, $00, $02, $03 ; CPU:$D808 PRG:1808 06 06 07 00 01 02 06 06 06 05 06 06 07 00 02 03
|
|
.byte $03, $03, $04, $04, $04, $06, $07, $00, $05, $05, $05, $05, $05, $06, $07, $06 ; CPU:$D818 PRG:1818 03 03 04 04 04 06 07 00 05 05 05 05 05 06 07 06
|
|
.byte $07, $00, $03, $03, $03, $04, $04, $05, $05, $06, $07, $00, $02, $02, $03, $03 ; CPU:$D828 PRG:1828 07 00 03 03 03 04 04 05 05 06 07 00 02 02 03 03
|
|
.byte $04, $04, $05, $05, $06, $06, $02, $03, $04, $04, $04, $06, $06, $06, $06, $07 ; CPU:$D838 PRG:1838 04 04 05 05 06 06 02 03 04 04 04 06 06 06 06 07
|
|
.byte $03, $03, $04, $04, $05, $06, $06, $07, $06, $07, $03, $03, $04, $04, $04, $06 ; CPU:$D848 PRG:1848 03 03 04 04 05 06 06 07 06 07 03 03 04 04 04 06
|
|
.byte $06, $07, $06, $07, $03, $03, $04, $05, $00, $06, $06, $07, $06, $07, $03, $03 ; CPU:$D858 PRG:1858 06 07 06 07 03 03 04 05 00 06 06 07 06 07 03 03
|
|
.byte $04, $04, $06, $06, $07, $06, $07, $07, $03, $03, $04, $05, $06, $06, $07, $06 ; CPU:$D868 PRG:1868 04 04 06 06 07 06 07 07 03 03 04 05 06 06 07 06
|
|
.byte $07, $07, $03, $03, $04, $04, $06, $06, $07, $06, $07, $07, $03, $04, $05, $05 ; CPU:$D878 PRG:1878 07 07 03 03 04 04 06 06 07 06 07 07 03 04 05 05
|
|
.byte $06, $07, $06, $07, $07, $07, $03, $04, $04, $06, $06, $07, $06, $07, $07, $07 ; CPU:$D888 PRG:1888 06 07 06 07 07 07 03 04 04 06 06 07 06 07 07 07
|
|
.byte $03, $04, $05, $06, $06, $06, $07, $07, $07, $07, $04, $05, $06, $06, $07, $06 ; CPU:$D898 PRG:1898 03 04 05 06 06 06 07 07 07 07 04 05 06 06 07 06
|
|
.byte $07, $07, $07, $07, $04, $05, $06, $07, $06, $07, $07, $07, $07, $07, $04, $05 ; CPU:$D8A8 PRG:18A8 07 07 07 07 04 05 06 07 06 07 07 07 07 07 04 05
|
|
.byte $06, $07, $06, $07, $07, $07, $07, $07, $05, $06, $05, $06, $07, $07, $07, $07 ; CPU:$D8B8 PRG:18B8 06 07 06 07 07 07 07 07 05 06 05 06 07 07 07 07
|
|
.byte $07, $07, $05, $06, $05, $06, $07, $07, $07, $07, $07, $07, $06, $05, $05, $06 ; CPU:$D8C8 PRG:18C8 07 07 05 06 05 06 07 07 07 07 07 07 06 05 05 06
|
|
.byte $07, $07, $07, $07, $07, $07, $06, $05, $06, $07, $07, $07, $07, $07, $07, $08 ; CPU:$D8D8 PRG:18D8 07 07 07 07 07 07 06 05 06 07 07 07 07 07 07 08
|
|
.byte $05, $05, $06, $07, $07, $07, $07, $07, $07, $08, $05, $05, $06, $07, $07, $07 ; CPU:$D8E8 PRG:18E8 05 05 06 07 07 07 07 07 07 08 05 05 06 07 07 07
|
|
.byte $07, $07, $08, $08 ; CPU:$D8F8 PRG:18F8 07 07 08 08
|
|
; Routine: Stage_WriteObjectWorkX_D8FC
|
|
; Global: Reachable code entry at CPU $D8FC traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_WriteObjectWorkX_D8FC:
|
|
stx $24 ; CPU:$D8FC PRG:18FC 86 24
|
|
sty $25 ; CPU:$D8FE PRG:18FE 84 25
|
|
pha ; CPU:$D900 PRG:1900 48
|
|
; Routine: Stage_ReadZp14_D901
|
|
; Global: Reachable code entry at CPU $D901 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_ReadZp14_D901:
|
|
lda $14 ; CPU:$D901 PRG:1901 A5 14
|
|
sec ; CPU:$D903 PRG:1903 38
|
|
sbc $15 ; CPU:$D904 PRG:1904 E5 15
|
|
cmp #$08 ; CPU:$D906 PRG:1906 C9 08
|
|
beq Stage_ReadZp14_D901 ; CPU:$D908 PRG:1908 F0 F7
|
|
pla ; CPU:$D90A PRG:190A 68
|
|
jsr Stage_WriteZp1A_D924 ; CPU:$D90B PRG:190B 20 24 D9
|
|
ldy $15 ; CPU:$D90E PRG:190E A4 15
|
|
ldx #$00 ; CPU:$D910 PRG:1910 A2 00
|
|
; Routine: Stage_ReadZp17_D912
|
|
; Global: Reachable code entry at CPU $D912 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_ReadZp17_D912:
|
|
lda $17,x ; CPU:$D912 PRG:1912 B5 17
|
|
sta $0600,y ; CPU:$D914 PRG:1914 99 00 06
|
|
iny ; CPU:$D917 PRG:1917 C8
|
|
inx ; CPU:$D918 PRG:1918 E8
|
|
cpx #$08 ; CPU:$D919 PRG:1919 E0 08
|
|
bne Stage_ReadZp17_D912 ; CPU:$D91B PRG:191B D0 F5
|
|
sty $15 ; CPU:$D91D PRG:191D 84 15
|
|
ldx $24 ; CPU:$D91F PRG:191F A6 24
|
|
ldy $25 ; CPU:$D921 PRG:1921 A4 25
|
|
rts ; CPU:$D923 PRG:1923 60
|
|
; Routine: Stage_WriteZp1A_D924
|
|
; Global: Reachable code entry at CPU $D924 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_WriteZp1A_D924:
|
|
tay ; CPU:$D924 PRG:1924 A8
|
|
asl a ; CPU:$D925 PRG:1925 0A
|
|
asl a ; CPU:$D926 PRG:1926 0A
|
|
sta $1A ; CPU:$D927 PRG:1927 85 1A
|
|
lda $D994,y ; CPU:$D929 PRG:1929 B9 94 D9
|
|
sta $1E ; CPU:$D92C PRG:192C 85 1E
|
|
ldy #$00 ; CPU:$D92E PRG:192E A0 00
|
|
lda $1F ; CPU:$D930 PRG:1930 A5 1F
|
|
cmp #$10 ; CPU:$D932 PRG:1932 C9 10
|
|
bcc Stage_WriteZp17_D93A ; CPU:$D934 PRG:1934 90 04
|
|
ldy #$04 ; CPU:$D936 PRG:1936 A0 04
|
|
sbc #$10 ; CPU:$D938 PRG:1938 E9 10
|
|
; Routine: Stage_WriteZp17_D93A
|
|
; Global: Reachable code entry at CPU $D93A traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_WriteZp17_D93A:
|
|
sty $17 ; CPU:$D93A PRG:193A 84 17
|
|
asl a ; CPU:$D93C PRG:193C 0A
|
|
sta $21 ; CPU:$D93D PRG:193D 85 21
|
|
lda $20 ; CPU:$D93F PRG:193F A5 20
|
|
clc ; CPU:$D941 PRG:1941 18
|
|
adc #$02 ; CPU:$D942 PRG:1942 69 02
|
|
asl a ; CPU:$D944 PRG:1944 0A
|
|
sta $22 ; CPU:$D945 PRG:1945 85 22
|
|
and #$FC ; CPU:$D947 PRG:1947 29 FC
|
|
asl a ; CPU:$D949 PRG:1949 0A
|
|
sta $1B ; CPU:$D94A PRG:194A 85 1B
|
|
lda $21 ; CPU:$D94C PRG:194C A5 21
|
|
lsr a ; CPU:$D94E PRG:194E 4A
|
|
lsr a ; CPU:$D94F PRG:194F 4A
|
|
clc ; CPU:$D950 PRG:1950 18
|
|
adc $1B ; CPU:$D951 PRG:1951 65 1B
|
|
clc ; CPU:$D953 PRG:1953 18
|
|
adc #$C0 ; CPU:$D954 PRG:1954 69 C0
|
|
sta $1B ; CPU:$D956 PRG:1956 85 1B
|
|
lda #$23 ; CPU:$D958 PRG:1958 A9 23
|
|
sta $1C ; CPU:$D95A PRG:195A 85 1C
|
|
lda #$02 ; CPU:$D95C PRG:195C A9 02
|
|
and $22 ; CPU:$D95E PRG:195E 25 22
|
|
sta $23 ; CPU:$D960 PRG:1960 85 23
|
|
lda $21 ; CPU:$D962 PRG:1962 A5 21
|
|
and #$03 ; CPU:$D964 PRG:1964 29 03
|
|
lsr a ; CPU:$D966 PRG:1966 4A
|
|
clc ; CPU:$D967 PRG:1967 18
|
|
adc $23 ; CPU:$D968 PRG:1968 65 23
|
|
asl a ; CPU:$D96A PRG:196A 0A
|
|
pha ; CPU:$D96B PRG:196B 48
|
|
lda #$FC ; CPU:$D96C PRG:196C A9 FC
|
|
sta $1D ; CPU:$D96E PRG:196E 85 1D
|
|
pla ; CPU:$D970 PRG:1970 68
|
|
tax ; CPU:$D971 PRG:1971 AA
|
|
beq Stage_WriteZp19_D97C ; CPU:$D972 PRG:1972 F0 08
|
|
; Routine: Stage_ShiftLeftZp1E_D974
|
|
; Global: Reachable code entry at CPU $D974 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_ShiftLeftZp1E_D974:
|
|
asl $1E ; CPU:$D974 PRG:1974 06 1E
|
|
sec ; CPU:$D976 PRG:1976 38
|
|
rol $1D ; CPU:$D977 PRG:1977 26 1D
|
|
dex ; CPU:$D979 PRG:1979 CA
|
|
bne Stage_ShiftLeftZp1E_D974 ; CPU:$D97A PRG:197A D0 F8
|
|
; Routine: Stage_WriteZp19_D97C
|
|
; Global: Reachable code entry at CPU $D97C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_WriteZp19_D97C:
|
|
lda #$01 ; CPU:$D97C PRG:197C A9 01
|
|
sta $19 ; CPU:$D97E PRG:197E 85 19
|
|
lda $22 ; CPU:$D980 PRG:1980 A5 22
|
|
ldx #$05 ; CPU:$D982 PRG:1982 A2 05
|
|
; Routine: Stage_RotateLeftZp19_D984
|
|
; Global: Reachable code entry at CPU $D984 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_RotateLeftZp19_D984:
|
|
asl a ; CPU:$D984 PRG:1984 0A
|
|
rol $19 ; CPU:$D985 PRG:1985 26 19
|
|
dex ; CPU:$D987 PRG:1987 CA
|
|
bne Stage_RotateLeftZp19_D984 ; CPU:$D988 PRG:1988 D0 FA
|
|
clc ; CPU:$D98A PRG:198A 18
|
|
adc $21 ; CPU:$D98B PRG:198B 65 21
|
|
sta $18 ; CPU:$D98D PRG:198D 85 18
|
|
bcc Stage_ReturnToCaller_D993 ; CPU:$D98F PRG:198F 90 02
|
|
inc $19 ; CPU:$D991 PRG:1991 E6 19
|
|
; Routine: Stage_ReturnToCaller_D993
|
|
; Global: Reachable code entry at CPU $D993 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Stage_ReturnToCaller_D993:
|
|
rts ; CPU:$D993 PRG:1993 60
|
|
|
|
; Data region: CPU $D994-$DA8D; unreachable by direct recursive trace.
|
|
StageLayoutPointerData:
|
|
.byte $00, $00, $00, $01, $01, $01, $01, $01, $00, $00, $00, $01, $01, $01, $01, $01 ; CPU:$D994 PRG:1994 00 00 00 01 01 01 01 01 00 00 00 01 01 01 01 01
|
|
.byte $01, $01, $01, $01, $01, $01, $01, $01, $01, $01, $01, $01, $01, $01, $01, $01 ; CPU:$D9A4 PRG:19A4 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
|
|
.byte $01, $01, $01, $01, $01, $01, $01, $01, $03, $02, $02, $02, $02, $02, $02, $02 ; CPU:$D9B4 PRG:19B4 01 01 01 01 01 01 01 01 03 02 02 02 02 02 02 02
|
|
.byte $02, $03, $5F, $5F, $5F, $5F, $64, $65, $66, $67, $68, $69, $6A, $6B, $6C, $6D ; CPU:$D9C4 PRG:19C4 02 03 5F 5F 5F 5F 64 65 66 67 68 69 6A 6B 6C 6D
|
|
.byte $6E, $6F, $70, $71, $72, $73, $74, $75, $76, $77, $78, $79, $7A, $7B, $7C, $7D ; CPU:$D9D4 PRG:19D4 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D
|
|
.byte $7E, $7F, $80, $81, $82, $83, $84, $85, $86, $87, $88, $89, $8A, $8B, $8C, $8D ; CPU:$D9E4 PRG:19E4 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D
|
|
.byte $8E, $8F, $90, $91, $92, $93, $94, $95, $96, $97, $98, $99, $9A, $9B, $20, $20 ; CPU:$D9F4 PRG:19F4 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 20 20
|
|
.byte $21, $21, $22, $23, $22, $23, $24, $24, $25, $25, $26, $27, $26, $27, $28, $28 ; CPU:$DA04 PRG:1A04 21 21 22 23 22 23 24 24 25 25 26 27 26 27 28 28
|
|
.byte $29, $29, $2A, $2B, $2A, $2B, $2C, $2C, $2D, $2D, $2E, $2F, $2E, $2F, $20, $9D ; CPU:$DA14 PRG:1A14 29 29 2A 2B 2A 2B 2C 2C 2D 2D 2E 2F 2E 2F 20 9D
|
|
.byte $21, $9F, $9C, $9D, $22, $23, $9C, $20, $9E, $21, $22, $23, $9E, $9F, $24, $A1 ; CPU:$DA24 PRG:1A24 21 9F 9C 9D 22 23 9C 20 9E 21 22 23 9E 9F 24 A1
|
|
.byte $25, $A3, $A0, $A1, $26, $27, $A0, $24, $A2, $25, $26, $27, $A2, $A3, $28, $A5 ; CPU:$DA34 PRG:1A34 25 A3 A0 A1 26 27 A0 24 A2 25 26 27 A2 A3 28 A5
|
|
.byte $29, $A7, $A4, $A5, $2A, $2B, $A4, $28, $A6, $29, $2A, $2B, $A6, $A7, $2C, $A9 ; CPU:$DA44 PRG:1A44 29 A7 A4 A5 2A 2B A4 28 A6 29 2A 2B A6 A7 2C A9
|
|
.byte $2D, $AB, $A8, $A9, $2E, $2F, $A8, $2C, $AA, $2D, $2E, $2F, $AA, $AB, $68, $69 ; CPU:$DA54 PRG:1A54 2D AB A8 A9 2E 2F A8 2C AA 2D 2E 2F AA AB 68 69
|
|
.byte $6A, $6B, $3C, $3D, $3E, $3F, $00, $01, $10, $11, $02, $03, $12, $13, $04, $05 ; CPU:$DA64 PRG:1A64 6A 6B 3C 3D 3E 3F 00 01 10 11 02 03 12 13 04 05
|
|
.byte $14, $15, $06, $07, $16, $17, $08, $09, $18, $19, $0A, $0B, $1A, $1B, $0C, $0D ; CPU:$DA74 PRG:1A74 14 15 06 07 16 17 08 09 18 19 0A 0B 1A 1B 0C 0D
|
|
.byte $1C, $1D, $0E, $0F, $1E, $1F, $68, $69, $6A, $6B ; CPU:$DA84 PRG:1A84 1C 1D 0E 0F 1E 1F 68 69 6A 6B
|
|
; Routine: RunMenuSelectionScreen
|
|
; Global: Reachable code entry at CPU $DA8E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
RunMenuSelectionScreen:
|
|
jsr DisableRendering ; CPU:$DA8E PRG:1A8E 20 57 C2
|
|
jsr Ppu_HandleControl_C2B9 ; CPU:$DA91 PRG:1A91 20 B9 C2
|
|
jsr UploadMenuPalette ; CPU:$DA94 PRG:1A94 20 27 DF
|
|
lda #$00 ; CPU:$DA97 PRG:1A97 A9 00
|
|
sta $60 ; CPU:$DA99 PRG:1A99 85 60
|
|
sta $72 ; CPU:$DA9B PRG:1A9B 85 72
|
|
sta $B5 ; CPU:$DA9D PRG:1A9D 85 B5
|
|
ldy #$9F ; CPU:$DA9F PRG:1A9F A0 9F
|
|
lda #$20 ; CPU:$DAA1 PRG:1AA1 A9 20
|
|
ldx #$E7 ; CPU:$DAA3 PRG:1AA3 A2 E7
|
|
jsr Menu_CallHelper_DC41 ; CPU:$DAA5 PRG:1AA5 20 41 DC
|
|
jsr Ppu_CallHelper_C23B ; CPU:$DAA8 PRG:1AA8 20 3B C2
|
|
lda #$06 ; CPU:$DAAB PRG:1AAB A9 06
|
|
sta $1F ; CPU:$DAAD PRG:1AAD 85 1F
|
|
lda #$3A ; CPU:$DAAF PRG:1AAF A9 3A
|
|
sta $20 ; CPU:$DAB1 PRG:1AB1 85 20
|
|
ldy #$00 ; CPU:$DAB3 PRG:1AB3 A0 00
|
|
; Routine: Menu_TransferVramDataPath_DAB5
|
|
; Global: Reachable code entry at CPU $DAB5 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DAB5:
|
|
jsr WaitForVBlankTransition ; CPU:$DAB5 PRG:1AB5 20 8B C2
|
|
lda #$22 ; CPU:$DAB8 PRG:1AB8 A9 22
|
|
ldx $1F ; CPU:$DABA PRG:1ABA A6 1F
|
|
jsr SetPpuAddress ; CPU:$DABC PRG:1ABC 20 96 C1
|
|
lda $20 ; CPU:$DABF PRG:1ABF A5 20
|
|
sta PPUDATA ; CPU:$DAC1 PRG:1AC1 8D 07 20
|
|
jsr CommitPpuStateAndScroll ; CPU:$DAC4 PRG:1AC4 20 96 C2
|
|
ldx #$0A ; CPU:$DAC7 PRG:1AC7 A2 0A
|
|
; Routine: Menu_TransferVramDataPath_DAC9
|
|
; Global: Reachable code entry at CPU $DAC9 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DAC9:
|
|
jsr WaitForVBlankTransition ; CPU:$DAC9 PRG:1AC9 20 8B C2
|
|
lda ControllerState1 ; CPU:$DACC PRG:1ACC A5 12
|
|
and #$8F ; CPU:$DACE PRG:1ACE 29 8F
|
|
bne Menu_UpdateAudioChannelPath_DAF8 ; CPU:$DAD0 PRG:1AD0 D0 26
|
|
dex ; CPU:$DAD2 PRG:1AD2 CA
|
|
bne Menu_TransferVramDataPath_DAC9 ; CPU:$DAD3 PRG:1AD3 D0 F4
|
|
jsr WaitForVBlankTransition ; CPU:$DAD5 PRG:1AD5 20 8B C2
|
|
lda #$22 ; CPU:$DAD8 PRG:1AD8 A9 22
|
|
ldx $1F ; CPU:$DADA PRG:1ADA A6 1F
|
|
jsr SetPpuAddress ; CPU:$DADC PRG:1ADC 20 96 C1
|
|
lda #$3B ; CPU:$DADF PRG:1ADF A9 3B
|
|
sta PPUDATA ; CPU:$DAE1 PRG:1AE1 8D 07 20
|
|
jsr CommitPpuStateAndScroll ; CPU:$DAE4 PRG:1AE4 20 96 C2
|
|
ldx #$0A ; CPU:$DAE7 PRG:1AE7 A2 0A
|
|
; Routine: Menu_CallHelper_DAE9
|
|
; Global: Reachable code entry at CPU $DAE9 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_CallHelper_DAE9:
|
|
jsr WaitForVBlankTransition ; CPU:$DAE9 PRG:1AE9 20 8B C2
|
|
lda ControllerState1 ; CPU:$DAEC PRG:1AEC A5 12
|
|
and #$8F ; CPU:$DAEE PRG:1AEE 29 8F
|
|
bne Menu_UpdateAudioChannelPath_DAF8 ; CPU:$DAF0 PRG:1AF0 D0 06
|
|
dex ; CPU:$DAF2 PRG:1AF2 CA
|
|
bne Menu_CallHelper_DAE9 ; CPU:$DAF3 PRG:1AF3 D0 F4
|
|
jmp Menu_TransferVramDataPath_DAB5 ; CPU:$DAF5 PRG:1AF5 4C B5 DA
|
|
; Routine: Menu_UpdateAudioChannelPath_DAF8
|
|
; Global: Reachable code entry at CPU $DAF8 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_UpdateAudioChannelPath_DAF8:
|
|
bmi Menu_TransferVramDataPath_DB43 ; CPU:$DAF8 PRG:1AF8 30 49
|
|
pha ; CPU:$DAFA PRG:1AFA 48
|
|
lda #$12 ; CPU:$DAFB PRG:1AFB A9 12
|
|
sta APUPULSE1TIMERHI ; CPU:$DAFD PRG:1AFD 8D 03 40
|
|
pla ; CPU:$DB00 PRG:1B00 68
|
|
cmp #$01 ; CPU:$DB01 PRG:1B01 C9 01
|
|
beq Menu_ReadWorkValue_DB24 ; CPU:$DB03 PRG:1B03 F0 1F
|
|
lda $20 ; CPU:$DB05 PRG:1B05 A5 20
|
|
cmp #$3A ; CPU:$DB07 PRG:1B07 C9 3A
|
|
bne Menu_ReadWorkValue_DB0F ; CPU:$DB09 PRG:1B09 D0 04
|
|
lda #$51 ; CPU:$DB0B PRG:1B0B A9 51
|
|
sta $20 ; CPU:$DB0D PRG:1B0D 85 20
|
|
; Routine: Menu_ReadWorkValue_DB0F
|
|
; Global: Reachable code entry at CPU $DB0F traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_ReadWorkValue_DB0F:
|
|
lda $20 ; CPU:$DB0F PRG:1B0F A5 20
|
|
cmp #$41 ; CPU:$DB11 PRG:1B11 C9 41
|
|
beq Menu_WriteWorkValue_DB1A ; CPU:$DB13 PRG:1B13 F0 05
|
|
dec $20 ; CPU:$DB15 PRG:1B15 C6 20
|
|
jmp Menu_CallHelper_DB1E ; CPU:$DB17 PRG:1B17 4C 1E DB
|
|
; Routine: Menu_WriteWorkValue_DB1A
|
|
; Global: Reachable code entry at CPU $DB1A traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_WriteWorkValue_DB1A:
|
|
lda #$50 ; CPU:$DB1A PRG:1B1A A9 50
|
|
sta $20 ; CPU:$DB1C PRG:1B1C 85 20
|
|
; Routine: Menu_CallHelper_DB1E
|
|
; Global: Reachable code entry at CPU $DB1E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_CallHelper_DB1E:
|
|
jsr WaitForFrameBoundary ; CPU:$DB1E PRG:1B1E 20 07 C3
|
|
jmp Menu_TransferVramDataPath_DAB5 ; CPU:$DB21 PRG:1B21 4C B5 DA
|
|
; Routine: Menu_ReadWorkValue_DB24
|
|
; Global: Reachable code entry at CPU $DB24 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_ReadWorkValue_DB24:
|
|
lda $20 ; CPU:$DB24 PRG:1B24 A5 20
|
|
cmp #$3A ; CPU:$DB26 PRG:1B26 C9 3A
|
|
bne Menu_ReadWorkValue_DB2E ; CPU:$DB28 PRG:1B28 D0 04
|
|
lda #$40 ; CPU:$DB2A PRG:1B2A A9 40
|
|
sta $20 ; CPU:$DB2C PRG:1B2C 85 20
|
|
; Routine: Menu_ReadWorkValue_DB2E
|
|
; Global: Reachable code entry at CPU $DB2E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_ReadWorkValue_DB2E:
|
|
lda $20 ; CPU:$DB2E PRG:1B2E A5 20
|
|
cmp #$50 ; CPU:$DB30 PRG:1B30 C9 50
|
|
beq Menu_WriteWorkValue_DB39 ; CPU:$DB32 PRG:1B32 F0 05
|
|
inc $20 ; CPU:$DB34 PRG:1B34 E6 20
|
|
jmp Menu_CallHelper_DB3D ; CPU:$DB36 PRG:1B36 4C 3D DB
|
|
; Routine: Menu_WriteWorkValue_DB39
|
|
; Global: Reachable code entry at CPU $DB39 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_WriteWorkValue_DB39:
|
|
lda #$41 ; CPU:$DB39 PRG:1B39 A9 41
|
|
sta $20 ; CPU:$DB3B PRG:1B3B 85 20
|
|
; Routine: Menu_CallHelper_DB3D
|
|
; Global: Reachable code entry at CPU $DB3D traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_CallHelper_DB3D:
|
|
jsr WaitForFrameBoundary ; CPU:$DB3D PRG:1B3D 20 07 C3
|
|
; Routine: Menu_Dispatch_DB40
|
|
; Global: Reachable code entry at CPU $DB40 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_Dispatch_DB40:
|
|
jmp Menu_TransferVramDataPath_DAB5 ; CPU:$DB40 PRG:1B40 4C B5 DA
|
|
; Routine: Menu_TransferVramDataPath_DB43
|
|
; Global: Reachable code entry at CPU $DB43 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DB43:
|
|
lda #$11 ; CPU:$DB43 PRG:1B43 A9 11
|
|
sta APUPULSE1TIMERHI ; CPU:$DB45 PRG:1B45 8D 03 40
|
|
lda $20 ; CPU:$DB48 PRG:1B48 A5 20
|
|
cmp #$3A ; CPU:$DB4A PRG:1B4A C9 3A
|
|
beq Menu_Dispatch_DB40 ; CPU:$DB4C PRG:1B4C F0 F2
|
|
and #$0F ; CPU:$DB4E PRG:1B4E 29 0F
|
|
tax ; CPU:$DB50 PRG:1B50 AA
|
|
lda $DFA0,x ; CPU:$DB51 PRG:1B51 BD A0 DF
|
|
sta $007F,y ; CPU:$DB54 PRG:1B54 99 7F 00
|
|
jsr WaitForVBlankTransition ; CPU:$DB57 PRG:1B57 20 8B C2
|
|
lda #$22 ; CPU:$DB5A PRG:1B5A A9 22
|
|
ldx $1F ; CPU:$DB5C PRG:1B5C A6 1F
|
|
jsr SetPpuAddress ; CPU:$DB5E PRG:1B5E 20 96 C1
|
|
lda $20 ; CPU:$DB61 PRG:1B61 A5 20
|
|
sta PPUDATA ; CPU:$DB63 PRG:1B63 8D 07 20
|
|
jsr CommitPpuStateAndScroll ; CPU:$DB66 PRG:1B66 20 96 C2
|
|
lda #$3A ; CPU:$DB69 PRG:1B69 A9 3A
|
|
sta $20 ; CPU:$DB6B PRG:1B6B 85 20
|
|
inc $1F ; CPU:$DB6D PRG:1B6D E6 1F
|
|
iny ; CPU:$DB6F PRG:1B6F C8
|
|
cpy #$14 ; CPU:$DB70 PRG:1B70 C0 14
|
|
beq Menu_HandleControl_DB7A ; CPU:$DB72 PRG:1B72 F0 06
|
|
jsr WaitForFrameBoundary ; CPU:$DB74 PRG:1B74 20 07 C3
|
|
jmp Menu_TransferVramDataPath_DAB5 ; CPU:$DB77 PRG:1B77 4C B5 DA
|
|
; Routine: Menu_HandleControl_DB7A
|
|
; Global: Reachable code entry at CPU $DB7A traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_HandleControl_DB7A:
|
|
ldx #$00 ; CPU:$DB7A PRG:1B7A A2 00
|
|
stx RandomState0 ; CPU:$DB7C PRG:1B7C 86 54
|
|
; Routine: Menu_ReadZp7F_DB7E
|
|
; Global: Reachable code entry at CPU $DB7E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_ReadZp7F_DB7E:
|
|
lda $7F,x ; CPU:$DB7E PRG:1B7E B5 7F
|
|
pha ; CPU:$DB80 PRG:1B80 48
|
|
clc ; CPU:$DB81 PRG:1B81 18
|
|
adc #$07 ; CPU:$DB82 PRG:1B82 69 07
|
|
clc ; CPU:$DB84 PRG:1B84 18
|
|
adc RandomState0 ; CPU:$DB85 PRG:1B85 65 54
|
|
and #$0F ; CPU:$DB87 PRG:1B87 29 0F
|
|
sta $7F,x ; CPU:$DB89 PRG:1B89 95 7F
|
|
pla ; CPU:$DB8B PRG:1B8B 68
|
|
sta RandomState0 ; CPU:$DB8C PRG:1B8C 85 54
|
|
inx ; CPU:$DB8E PRG:1B8E E8
|
|
cpx #$14 ; CPU:$DB8F PRG:1B8F E0 14
|
|
bne Menu_ReadZp7F_DB7E ; CPU:$DB91 PRG:1B91 D0 EB
|
|
ldx #$00 ; CPU:$DB93 PRG:1B93 A2 00
|
|
; Routine: Menu_HandleControl_DB95
|
|
; Global: Reachable code entry at CPU $DB95 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_HandleControl_DB95:
|
|
ldy #$04 ; CPU:$DB95 PRG:1B95 A0 04
|
|
lda #$00 ; CPU:$DB97 PRG:1B97 A9 00
|
|
; Routine: Menu_AddToZp7F_DB99
|
|
; Global: Reachable code entry at CPU $DB99 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_AddToZp7F_DB99:
|
|
clc ; CPU:$DB99 PRG:1B99 18
|
|
adc $7F,x ; CPU:$DB9A PRG:1B9A 75 7F
|
|
inx ; CPU:$DB9C PRG:1B9C E8
|
|
dey ; CPU:$DB9D PRG:1B9D 88
|
|
bne Menu_AddToZp7F_DB99 ; CPU:$DB9E PRG:1B9E D0 F9
|
|
and #$0F ; CPU:$DBA0 PRG:1BA0 29 0F
|
|
cmp $7F,x ; CPU:$DBA2 PRG:1BA2 D5 7F
|
|
bne Menu_Dispatch_DBCC ; CPU:$DBA4 PRG:1BA4 D0 26
|
|
inx ; CPU:$DBA6 PRG:1BA6 E8
|
|
cpx #$0F ; CPU:$DBA7 PRG:1BA7 E0 0F
|
|
bne Menu_HandleControl_DB95 ; CPU:$DBA9 PRG:1BA9 D0 EA
|
|
lda $83 ; CPU:$DBAB PRG:1BAB A5 83
|
|
asl a ; CPU:$DBAD PRG:1BAD 0A
|
|
sta $1F ; CPU:$DBAE PRG:1BAE 85 1F
|
|
lda $88 ; CPU:$DBB0 PRG:1BB0 A5 88
|
|
asl a ; CPU:$DBB2 PRG:1BB2 0A
|
|
clc ; CPU:$DBB3 PRG:1BB3 18
|
|
adc $1F ; CPU:$DBB4 PRG:1BB4 65 1F
|
|
sta $1F ; CPU:$DBB6 PRG:1BB6 85 1F
|
|
lda $8D ; CPU:$DBB8 PRG:1BB8 A5 8D
|
|
asl a ; CPU:$DBBA PRG:1BBA 0A
|
|
clc ; CPU:$DBBB PRG:1BBB 18
|
|
adc $1F ; CPU:$DBBC PRG:1BBC 65 1F
|
|
ldx #$04 ; CPU:$DBBE PRG:1BBE A2 04
|
|
; Routine: Menu_AddToZp8D_DBC0
|
|
; Global: Reachable code entry at CPU $DBC0 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_AddToZp8D_DBC0:
|
|
clc ; CPU:$DBC0 PRG:1BC0 18
|
|
adc $8D,x ; CPU:$DBC1 PRG:1BC1 75 8D
|
|
dex ; CPU:$DBC3 PRG:1BC3 CA
|
|
bne Menu_AddToZp8D_DBC0 ; CPU:$DBC4 PRG:1BC4 D0 FA
|
|
and #$0F ; CPU:$DBC6 PRG:1BC6 29 0F
|
|
cmp $92 ; CPU:$DBC8 PRG:1BC8 C5 92
|
|
beq Menu_HandleControl_DBCF ; CPU:$DBCA PRG:1BCA F0 03
|
|
; Routine: Menu_Dispatch_DBCC
|
|
; Global: Reachable code entry at CPU $DBCC traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_Dispatch_DBCC:
|
|
jmp RunMenuSelectionScreen ; CPU:$DBCC PRG:1BCC 4C 8E DA
|
|
; Routine: Menu_HandleControl_DBCF
|
|
; Global: Reachable code entry at CPU $DBCF traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_HandleControl_DBCF:
|
|
ldx #$00 ; CPU:$DBCF PRG:1BCF A2 00
|
|
ldy #$00 ; CPU:$DBD1 PRG:1BD1 A0 00
|
|
; Routine: Menu_ReadRam007F_DBD3
|
|
; Global: Reachable code entry at CPU $DBD3 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_ReadRam007F_DBD3:
|
|
jsr Gameplay_ReadRamE360_E353 ; CPU:$DBD3 PRG:1BD3 20 53 E3
|
|
lda $007F,y ; CPU:$DBD6 PRG:1BD6 B9 7F 00
|
|
sty $25 ; CPU:$DBD9 PRG:1BD9 84 25
|
|
ldy #$00 ; CPU:$DBDB PRG:1BDB A0 00
|
|
sta ($34),y ; CPU:$DBDD PRG:1BDD 91 34
|
|
ldy $25 ; CPU:$DBDF PRG:1BDF A4 25
|
|
iny ; CPU:$DBE1 PRG:1BE1 C8
|
|
cpy #$14 ; CPU:$DBE2 PRG:1BE2 C0 14
|
|
bne Menu_ReadRam007F_DBD3 ; CPU:$DBE4 PRG:1BE4 D0 ED
|
|
lda $DC ; CPU:$DBE6 PRG:1BE6 A5 DC
|
|
asl a ; CPU:$DBE8 PRG:1BE8 0A
|
|
asl a ; CPU:$DBE9 PRG:1BE9 0A
|
|
asl a ; CPU:$DBEA PRG:1BEA 0A
|
|
asl a ; CPU:$DBEB PRG:1BEB 0A
|
|
sta $73 ; CPU:$DBEC PRG:1BEC 85 73
|
|
lda $DE ; CPU:$DBEE PRG:1BEE A5 DE
|
|
asl a ; CPU:$DBF0 PRG:1BF0 0A
|
|
asl a ; CPU:$DBF1 PRG:1BF1 0A
|
|
asl a ; CPU:$DBF2 PRG:1BF2 0A
|
|
asl a ; CPU:$DBF3 PRG:1BF3 0A
|
|
ora $DD ; CPU:$DBF4 PRG:1BF4 05 DD
|
|
sta $58 ; CPU:$DBF6 PRG:1BF6 85 58
|
|
rts ; CPU:$DBF8 PRG:1BF8 60
|
|
; Routine: Menu_WriteWorkValue_DBF9
|
|
; Global: Reachable code entry at CPU $DBF9 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_WriteWorkValue_DBF9:
|
|
jsr DisableRendering ; CPU:$DBF9 PRG:1BF9 20 57 C2
|
|
jsr Ppu_HandleControl_C2B9 ; CPU:$DBFC PRG:1BFC 20 B9 C2
|
|
jsr UploadMenuPalette ; CPU:$DBFF PRG:1BFF 20 27 DF
|
|
lda #$06 ; CPU:$DC02 PRG:1C02 A9 06
|
|
jsr Menu_SaveAccumulator_DD04 ; CPU:$DC04 PRG:1C04 20 04 DD
|
|
ldy #$00 ; CPU:$DC07 PRG:1C07 A0 00
|
|
jsr Menu_ReadRamDC53_DC39 ; CPU:$DC09 PRG:1C09 20 39 DC
|
|
jsr Menu_ReadRamDC53_DC39 ; CPU:$DC0C PRG:1C0C 20 39 DC
|
|
jsr Menu_ReadRamDC53_DC39 ; CPU:$DC0F PRG:1C0F 20 39 DC
|
|
jsr Menu_ReadRamDC53_DC39 ; CPU:$DC12 PRG:1C12 20 39 DC
|
|
jsr Menu_ReadRamDC53_DC39 ; CPU:$DC15 PRG:1C15 20 39 DC
|
|
jsr Menu_ReadRamDC53_DC39 ; CPU:$DC18 PRG:1C18 20 39 DC
|
|
jsr Menu_ReadRamDC53_DC39 ; CPU:$DC1B PRG:1C1B 20 39 DC
|
|
lda #$0A ; CPU:$DC1E PRG:1C1E A9 0A
|
|
sta $20 ; CPU:$DC20 PRG:1C20 85 20
|
|
lda #$00 ; CPU:$DC22 PRG:1C22 A9 00
|
|
sta $1F ; CPU:$DC24 PRG:1C24 85 1F
|
|
; Routine: Menu_IncrementWorkIndex_DC26
|
|
; Global: Reachable code entry at CPU $DC26 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_IncrementWorkIndex_DC26:
|
|
lda #$31 ; CPU:$DC26 PRG:1C26 A9 31
|
|
jsr Gameplay_WriteObjectWorkY_CB4E ; CPU:$DC28 PRG:1C28 20 4E CB
|
|
inc $1F ; CPU:$DC2B PRG:1C2B E6 1F
|
|
lda $1F ; CPU:$DC2D PRG:1C2D A5 1F
|
|
cmp #$10 ; CPU:$DC2F PRG:1C2F C9 10
|
|
bne Menu_IncrementWorkIndex_DC26 ; CPU:$DC31 PRG:1C31 D0 F3
|
|
jsr EnableNmiInPpuControl ; CPU:$DC33 PRG:1C33 20 B0 C2
|
|
jmp Ppu_CallHelper_C23B ; CPU:$DC36 PRG:1C36 4C 3B C2
|
|
; Routine: Menu_ReadRamDC53_DC39
|
|
; Global: Reachable code entry at CPU $DC39 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_ReadRamDC53_DC39:
|
|
lda $DC53,y ; CPU:$DC39 PRG:1C39 B9 53 DC
|
|
iny ; CPU:$DC3C PRG:1C3C C8
|
|
ldx $DC53,y ; CPU:$DC3D PRG:1C3D BE 53 DC
|
|
iny ; CPU:$DC40 PRG:1C40 C8
|
|
; Routine: Menu_CallHelper_DC41
|
|
; Global: Reachable code entry at CPU $DC41 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_CallHelper_DC41:
|
|
jsr SetPpuAddress ; CPU:$DC41 PRG:1C41 20 96 C1
|
|
; Routine: Menu_TransferVramDataPath_DC44
|
|
; Global: Reachable code entry at CPU $DC44 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DC44:
|
|
lda $DC53,y ; CPU:$DC44 PRG:1C44 B9 53 DC
|
|
iny ; CPU:$DC47 PRG:1C47 C8
|
|
cmp #$00 ; CPU:$DC48 PRG:1C48 C9 00
|
|
beq Menu_ReturnToCaller_DC52 ; CPU:$DC4A PRG:1C4A F0 06
|
|
sta PPUDATA ; CPU:$DC4C PRG:1C4C 8D 07 20
|
|
jmp Menu_TransferVramDataPath_DC44 ; CPU:$DC4F PRG:1C4F 4C 44 DC
|
|
; Routine: Menu_ReturnToCaller_DC52
|
|
; Global: Reachable code entry at CPU $DC52 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_ReturnToCaller_DC52:
|
|
rts ; CPU:$DC52 PRG:1C52 60
|
|
|
|
; Data region: CPU $DC53-$DD03; unreachable by direct recursive trace.
|
|
MenuScreenConstructionData:
|
|
.byte $20, $88, $43, $4F, $4E, $47, $52, $41, $54, $55, $4C, $41, $54, $49, $4F, $4E ; CPU:$DC53 PRG:1C53 20 88 43 4F 4E 47 52 41 54 55 4C 41 54 49 4F 4E
|
|
.byte $53, $00, $20, $E4, $59, $4F, $55, $3A, $48, $41, $56, $45, $3A, $53, $55, $43 ; CPU:$DC63 PRG:1C63 53 00 20 E4 59 4F 55 3A 48 41 56 45 3A 53 55 43
|
|
.byte $43, $45, $45, $44, $45, $44, $3A, $49, $4E, $00, $21, $22, $48, $45, $4C, $50 ; CPU:$DC73 PRG:1C73 43 45 45 44 45 44 3A 49 4E 00 21 22 48 45 4C 50
|
|
.byte $49, $4E, $47, $3A, $42, $4F, $4D, $42, $45, $52, $4D, $41, $4E, $3A, $54, $4F ; CPU:$DC83 PRG:1C83 49 4E 47 3A 42 4F 4D 42 45 52 4D 41 4E 3A 54 4F
|
|
.byte $3A, $42, $45, $43, $4F, $4D, $45, $00, $21, $62, $41, $3A, $48, $55, $4D, $41 ; CPU:$DC93 PRG:1C93 3A 42 45 43 4F 4D 45 00 21 62 41 3A 48 55 4D 41
|
|
.byte $4E, $3A, $42, $45, $49, $4E, $47, $00, $21, $A4, $4D, $41, $59, $42, $45, $3A ; CPU:$DCA3 PRG:1CA3 4E 3A 42 45 49 4E 47 00 21 A4 4D 41 59 42 45 3A
|
|
.byte $59, $4F, $55, $3A, $43, $41, $4E, $3A, $52, $45, $43, $4F, $47, $4E, $49, $5A ; CPU:$DCB3 PRG:1CB3 59 4F 55 3A 43 41 4E 3A 52 45 43 4F 47 4E 49 5A
|
|
.byte $45, $3A, $48, $49, $4D, $00, $21, $E2, $49, $4E, $3A, $41, $4E, $4F, $54, $48 ; CPU:$DCC3 PRG:1CC3 45 3A 48 49 4D 00 21 E2 49 4E 3A 41 4E 4F 54 48
|
|
.byte $45, $52, $3A, $48, $55, $44, $53, $4F, $4E, $3A, $53, $4F, $46, $54, $3A, $47 ; CPU:$DCD3 PRG:1CD3 45 52 3A 48 55 44 53 4F 4E 3A 53 4F 46 54 3A 47
|
|
.byte $41, $4D, $45, $00, $22, $4B, $47, $4F, $4F, $44, $3A, $42, $59, $45, $00, $45 ; CPU:$DCE3 PRG:1CE3 41 4D 45 00 22 4B 47 4F 4F 44 3A 42 59 45 00 45
|
|
.byte $4E, $54, $45, $52, $3A, $53, $45, $43, $52, $45, $54, $3A, $43, $4F, $44, $45 ; CPU:$DCF3 PRG:1CF3 4E 54 45 52 3A 53 45 43 52 45 54 3A 43 4F 44 45
|
|
.byte $00 ; CPU:$DD03 PRG:1D03 00
|
|
; Routine: Menu_SaveAccumulator_DD04
|
|
; Global: Reachable code entry at CPU $DD04 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_SaveAccumulator_DD04:
|
|
pha ; CPU:$DD04 PRG:1D04 48
|
|
jsr WaitForVBlankTransition ; CPU:$DD05 PRG:1D05 20 8B C2
|
|
lda #$3F ; CPU:$DD08 PRG:1D08 A9 3F
|
|
ldx #$1C ; CPU:$DD0A PRG:1D0A A2 1C
|
|
jsr SetPpuAddress ; CPU:$DD0C PRG:1D0C 20 96 C1
|
|
pla ; CPU:$DD0F PRG:1D0F 68
|
|
asl a ; CPU:$DD10 PRG:1D10 0A
|
|
asl a ; CPU:$DD11 PRG:1D11 0A
|
|
tax ; CPU:$DD12 PRG:1D12 AA
|
|
ldy #$04 ; CPU:$DD13 PRG:1D13 A0 04
|
|
; Routine: Menu_TransferVramDataPath_DD15
|
|
; Global: Reachable code entry at CPU $DD15 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DD15:
|
|
lda $DD22,x ; CPU:$DD15 PRG:1D15 BD 22 DD
|
|
sta PPUDATA ; CPU:$DD18 PRG:1D18 8D 07 20
|
|
inx ; CPU:$DD1B PRG:1D1B E8
|
|
dey ; CPU:$DD1C PRG:1D1C 88
|
|
bne Menu_TransferVramDataPath_DD15 ; CPU:$DD1D PRG:1D1D D0 F6
|
|
jmp Ppu_SetVramAddress_C2D6 ; CPU:$DD1F PRG:1D1F 4C D6 C2
|
|
|
|
; Data region: CPU $DD22-$DD3D; unreachable by direct recursive trace.
|
|
StatusScreenAddressTable:
|
|
.byte $0F, $00, $00, $00, $0F, $00, $00, $00, $0F, $00, $00, $00, $0F, $00, $00, $00 ; CPU:$DD22 PRG:1D22 0F 00 00 00 0F 00 00 00 0F 00 00 00 0F 00 00 00
|
|
.byte $0F, $00, $00, $00, $0F, $00, $00, $00, $0F, $15, $36, $21 ; CPU:$DD32 PRG:1D32 0F 00 00 00 0F 00 00 00 0F 15 36 21
|
|
; Routine: Menu_CallHelper_DD3E
|
|
; Global: Reachable code entry at CPU $DD3E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_CallHelper_DD3E:
|
|
jsr DisableRendering ; CPU:$DD3E PRG:1D3E 20 57 C2
|
|
jsr Ppu_HandleControl_C2B9 ; CPU:$DD41 PRG:1D41 20 B9 C2
|
|
jsr UploadMenuPalette ; CPU:$DD44 PRG:1D44 20 27 DF
|
|
lda #$21 ; CPU:$DD47 PRG:1D47 A9 21
|
|
ldx #$EA ; CPU:$DD49 PRG:1D49 A2 EA
|
|
jsr SetPpuAddress ; CPU:$DD4B PRG:1D4B 20 96 C1
|
|
ldx #$08 ; CPU:$DD4E PRG:1D4E A2 08
|
|
; Routine: Menu_TransferVramDataPath_DD50
|
|
; Global: Reachable code entry at CPU $DD50 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DD50:
|
|
lda $DD62,x ; CPU:$DD50 PRG:1D50 BD 62 DD
|
|
sta PPUDATA ; CPU:$DD53 PRG:1D53 8D 07 20
|
|
dex ; CPU:$DD56 PRG:1D56 CA
|
|
bpl Menu_TransferVramDataPath_DD50 ; CPU:$DD57 PRG:1D57 10 F7
|
|
jsr Gameplay_ReadObjectMode_E2BD ; CPU:$DD59 PRG:1D59 20 BD E2
|
|
jsr EnableNmiInPpuControl ; CPU:$DD5C PRG:1D5C 20 B0 C2
|
|
jmp Ppu_CallHelper_C23B ; CPU:$DD5F PRG:1D5F 4C 3B C2
|
|
|
|
; Data region: CPU $DD62-$DD6A; unreachable by direct recursive trace.
|
|
StatusDigitTileTable:
|
|
.byte $52, $45, $56, $4F, $3A, $45, $4D, $41, $47 ; CPU:$DD62 PRG:1D62 52 45 56 4F 3A 45 4D 41 47
|
|
; Routine: Menu_WriteObjectWorkX_DD6B
|
|
; Global: Reachable code entry at CPU $DD6B traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_WriteObjectWorkX_DD6B:
|
|
stx $24 ; CPU:$DD6B PRG:1D6B 86 24
|
|
sty $25 ; CPU:$DD6D PRG:1D6D 84 25
|
|
ldx $59 ; CPU:$DD6F PRG:1D6F A6 59
|
|
bne Menu_ReadObjectWorkX_DDC2 ; CPU:$DD71 PRG:1D71 D0 4F
|
|
ldx #$03 ; CPU:$DD73 PRG:1D73 A2 03
|
|
bne Menu_AddToZp61_DD8D ; CPU:$DD75 PRG:1D75 D0 16
|
|
; Routine: Menu_WriteObjectWorkX_DD77
|
|
; Global: Reachable code entry at CPU $DD77 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_WriteObjectWorkX_DD77:
|
|
stx $24 ; CPU:$DD77 PRG:1D77 86 24
|
|
sty $25 ; CPU:$DD79 PRG:1D79 84 25
|
|
ldx $59 ; CPU:$DD7B PRG:1D7B A6 59
|
|
bne Menu_ReadObjectWorkX_DDC2 ; CPU:$DD7D PRG:1D7D D0 43
|
|
ldx #$04 ; CPU:$DD7F PRG:1D7F A2 04
|
|
bne Menu_AddToZp61_DD8D ; CPU:$DD81 PRG:1D81 D0 0A
|
|
; Routine: Menu_WriteObjectWorkX_DD83
|
|
; Global: Reachable code entry at CPU $DD83 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_WriteObjectWorkX_DD83:
|
|
stx $24 ; CPU:$DD83 PRG:1D83 86 24
|
|
sty $25 ; CPU:$DD85 PRG:1D85 84 25
|
|
ldx $59 ; CPU:$DD87 PRG:1D87 A6 59
|
|
bne Menu_ReadObjectWorkX_DDC2 ; CPU:$DD89 PRG:1D89 D0 37
|
|
ldx #$06 ; CPU:$DD8B PRG:1D8B A2 06
|
|
; Routine: Menu_AddToZp61_DD8D
|
|
; Global: Reachable code entry at CPU $DD8D traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_AddToZp61_DD8D:
|
|
ldy #$00 ; CPU:$DD8D PRG:1D8D A0 00
|
|
clc ; CPU:$DD8F PRG:1D8F 18
|
|
adc $61,x ; CPU:$DD90 PRG:1D90 75 61
|
|
; Routine: Menu_WriteZp61_DD92
|
|
; Global: Reachable code entry at CPU $DD92 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_WriteZp61_DD92:
|
|
sta $61,x ; CPU:$DD92 PRG:1D92 95 61
|
|
lda $61,x ; CPU:$DD94 PRG:1D94 B5 61
|
|
sec ; CPU:$DD96 PRG:1D96 38
|
|
sbc #$0A ; CPU:$DD97 PRG:1D97 E9 0A
|
|
bcc Menu_WriteZp61_DD9E ; CPU:$DD99 PRG:1D99 90 03
|
|
iny ; CPU:$DD9B PRG:1D9B C8
|
|
bne Menu_WriteZp61_DD92 ; CPU:$DD9C PRG:1D9C D0 F4
|
|
; Routine: Menu_WriteZp61_DD9E
|
|
; Global: Reachable code entry at CPU $DD9E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_WriteZp61_DD9E:
|
|
cpy #$00 ; CPU:$DD9E PRG:1D9E C0 00
|
|
beq Menu_HandleControl_DDAA ; CPU:$DDA0 PRG:1DA0 F0 08
|
|
tya ; CPU:$DDA2 PRG:1DA2 98
|
|
dex ; CPU:$DDA3 PRG:1DA3 CA
|
|
bpl Menu_AddToZp61_DD8D ; CPU:$DDA4 PRG:1DA4 10 E7
|
|
lda #$09 ; CPU:$DDA6 PRG:1DA6 A9 09
|
|
sta $61 ; CPU:$DDA8 PRG:1DA8 85 61
|
|
; Routine: Menu_HandleControl_DDAA
|
|
; Global: Reachable code entry at CPU $DDAA traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_HandleControl_DDAA:
|
|
ldx #$00 ; CPU:$DDAA PRG:1DAA A2 00
|
|
; Routine: Menu_ReadZp61_DDAC
|
|
; Global: Reachable code entry at CPU $DDAC traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_ReadZp61_DDAC:
|
|
lda $61,x ; CPU:$DDAC PRG:1DAC B5 61
|
|
cmp $01,x ; CPU:$DDAE PRG:1DAE D5 01
|
|
bcc Menu_ReadObjectWorkX_DDC2 ; CPU:$DDB0 PRG:1DB0 90 10
|
|
bne Menu_HandleControl_DDB9 ; CPU:$DDB2 PRG:1DB2 D0 05
|
|
inx ; CPU:$DDB4 PRG:1DB4 E8
|
|
cpx #$08 ; CPU:$DDB5 PRG:1DB5 E0 08
|
|
bne Menu_ReadZp61_DDAC ; CPU:$DDB7 PRG:1DB7 D0 F3
|
|
; Routine: Menu_HandleControl_DDB9
|
|
; Global: Reachable code entry at CPU $DDB9 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_HandleControl_DDB9:
|
|
ldx #$06 ; CPU:$DDB9 PRG:1DB9 A2 06
|
|
; Routine: Menu_ReadZp61_DDBB
|
|
; Global: Reachable code entry at CPU $DDBB traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_ReadZp61_DDBB:
|
|
lda $61,x ; CPU:$DDBB PRG:1DBB B5 61
|
|
sta $01,x ; CPU:$DDBD PRG:1DBD 95 01
|
|
dex ; CPU:$DDBF PRG:1DBF CA
|
|
bpl Menu_ReadZp61_DDBB ; CPU:$DDC0 PRG:1DC0 10 F9
|
|
; Routine: Menu_ReadObjectWorkX_DDC2
|
|
; Global: Reachable code entry at CPU $DDC2 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_ReadObjectWorkX_DDC2:
|
|
ldx $24 ; CPU:$DDC2 PRG:1DC2 A6 24
|
|
ldy $25 ; CPU:$DDC4 PRG:1DC4 A4 25
|
|
rts ; CPU:$DDC6 PRG:1DC6 60
|
|
; Routine: Menu_HandleControl_DDC7
|
|
; Global: Reachable code entry at CPU $DDC7 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_HandleControl_DDC7:
|
|
lda #$20 ; CPU:$DDC7 PRG:1DC7 A9 20
|
|
ldx #$00 ; CPU:$DDC9 PRG:1DC9 A2 00
|
|
jsr SetPpuAddress ; CPU:$DDCB PRG:1DCB 20 96 C1
|
|
ldx #$80 ; CPU:$DDCE PRG:1DCE A2 80
|
|
lda #$3A ; CPU:$DDD0 PRG:1DD0 A9 3A
|
|
; Routine: Menu_TransferVramDataPath_DDD2
|
|
; Global: Reachable code entry at CPU $DDD2 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DDD2:
|
|
sta PPUDATA ; CPU:$DDD2 PRG:1DD2 8D 07 20
|
|
dex ; CPU:$DDD5 PRG:1DD5 CA
|
|
bne Menu_TransferVramDataPath_DDD2 ; CPU:$DDD6 PRG:1DD6 D0 FA
|
|
lda #$20 ; CPU:$DDD8 PRG:1DD8 A9 20
|
|
ldx #$41 ; CPU:$DDDA PRG:1DDA A2 41
|
|
jsr SetPpuAddress ; CPU:$DDDC PRG:1DDC 20 96 C1
|
|
ldx #$03 ; CPU:$DDDF PRG:1DDF A2 03
|
|
; Routine: Menu_TransferVramDataPath_DDE1
|
|
; Global: Reachable code entry at CPU $DDE1 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DDE1:
|
|
lda $DE15,x ; CPU:$DDE1 PRG:1DE1 BD 15 DE
|
|
sta PPUDATA ; CPU:$DDE4 PRG:1DE4 8D 07 20
|
|
dex ; CPU:$DDE7 PRG:1DE7 CA
|
|
bpl Menu_TransferVramDataPath_DDE1 ; CPU:$DDE8 PRG:1DE8 10 F7
|
|
lda #$3A ; CPU:$DDEA PRG:1DEA A9 3A
|
|
sta PPUDATA ; CPU:$DDEC PRG:1DEC 8D 07 20
|
|
lda #$20 ; CPU:$DDEF PRG:1DEF A9 20
|
|
ldx #$52 ; CPU:$DDF1 PRG:1DF1 A2 52
|
|
jsr SetPpuAddress ; CPU:$DDF3 PRG:1DF3 20 96 C1
|
|
lda #$30 ; CPU:$DDF6 PRG:1DF6 A9 30
|
|
sta PPUDATA ; CPU:$DDF8 PRG:1DF8 8D 07 20
|
|
sta PPUDATA ; CPU:$DDFB PRG:1DFB 8D 07 20
|
|
lda #$20 ; CPU:$DDFE PRG:1DFE A9 20
|
|
ldx #$58 ; CPU:$DE00 PRG:1E00 A2 58
|
|
jsr SetPpuAddress ; CPU:$DE02 PRG:1E02 20 96 C1
|
|
ldx #$03 ; CPU:$DE05 PRG:1E05 A2 03
|
|
; Routine: Menu_TransferVramDataPath_DE07
|
|
; Global: Reachable code entry at CPU $DE07 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DE07:
|
|
lda $DE19,x ; CPU:$DE07 PRG:1E07 BD 19 DE
|
|
sta PPUDATA ; CPU:$DE0A PRG:1E0A 8D 07 20
|
|
dex ; CPU:$DE0D PRG:1E0D CA
|
|
bpl Menu_TransferVramDataPath_DE07 ; CPU:$DE0E PRG:1E0E 10 F7
|
|
lda $68 ; CPU:$DE10 PRG:1E10 A5 68
|
|
jmp Menu_HandleControl_DF5D ; CPU:$DE12 PRG:1E12 4C 5D DF
|
|
|
|
; Data region: CPU $DE15-$DE1C; unreachable by direct recursive trace.
|
|
StatusScreenTextPointerTable:
|
|
.byte $45, $4D, $49, $54, $54, $46, $45, $4C ; CPU:$DE15 PRG:1E15 45 4D 49 54 54 46 45 4C
|
|
; Routine: Menu_WriteZp0E_DE1D
|
|
; Global: Reachable code entry at CPU $DE1D traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_WriteZp0E_DE1D:
|
|
jsr DisableRendering ; CPU:$DE1D PRG:1E1D 20 57 C2
|
|
jsr Ppu_HandleControl_C2B9 ; CPU:$DE20 PRG:1E20 20 B9 C2
|
|
lda #$00 ; CPU:$DE23 PRG:1E23 A9 00
|
|
sta $0E ; CPU:$DE25 PRG:1E25 85 0E
|
|
jsr UploadMenuPalette ; CPU:$DE27 PRG:1E27 20 27 DF
|
|
lda #$21 ; CPU:$DE2A PRG:1E2A A9 21
|
|
ldx #$EA ; CPU:$DE2C PRG:1E2C A2 EA
|
|
jsr SetPpuAddress ; CPU:$DE2E PRG:1E2E 20 96 C1
|
|
ldx #$04 ; CPU:$DE31 PRG:1E31 A2 04
|
|
; Routine: Menu_TransferVramDataPath_DE33
|
|
; Global: Reachable code entry at CPU $DE33 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DE33:
|
|
lda $DE4E,x ; CPU:$DE33 PRG:1E33 BD 4E DE
|
|
sta PPUDATA ; CPU:$DE36 PRG:1E36 8D 07 20
|
|
dex ; CPU:$DE39 PRG:1E39 CA
|
|
bpl Menu_TransferVramDataPath_DE33 ; CPU:$DE3A PRG:1E3A 10 F7
|
|
lda #$21 ; CPU:$DE3C PRG:1E3C A9 21
|
|
ldx #$F0 ; CPU:$DE3E PRG:1E3E A2 F0
|
|
jsr SetPpuAddress ; CPU:$DE40 PRG:1E40 20 96 C1
|
|
lda $58 ; CPU:$DE43 PRG:1E43 A5 58
|
|
jsr Menu_HandleControl_DF5D ; CPU:$DE45 PRG:1E45 20 5D DF
|
|
jsr EnableNmiInPpuControl ; CPU:$DE48 PRG:1E48 20 B0 C2
|
|
jmp Ppu_CallHelper_C23B ; CPU:$DE4B PRG:1E4B 4C 3B C2
|
|
|
|
; Data region: CPU $DE4E-$DE52; unreachable by direct recursive trace.
|
|
StatusScreenValueAddressTable:
|
|
.byte $45, $47, $41, $54, $53 ; CPU:$DE4E PRG:1E4E 45 47 41 54 53
|
|
; Routine: Menu_WriteZp0E_DE53
|
|
; Global: Reachable code entry at CPU $DE53 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_WriteZp0E_DE53:
|
|
jsr DisableRendering ; CPU:$DE53 PRG:1E53 20 57 C2
|
|
jsr Ppu_HandleControl_C2B9 ; CPU:$DE56 PRG:1E56 20 B9 C2
|
|
lda #$00 ; CPU:$DE59 PRG:1E59 A9 00
|
|
sta $0E ; CPU:$DE5B PRG:1E5B 85 0E
|
|
jsr UploadMenuPalette ; CPU:$DE5D PRG:1E5D 20 27 DF
|
|
lda #$21 ; CPU:$DE60 PRG:1E60 A9 21
|
|
ldx #$EA ; CPU:$DE62 PRG:1E62 A2 EA
|
|
jsr SetPpuAddress ; CPU:$DE64 PRG:1E64 20 96 C1
|
|
ldx #$0A ; CPU:$DE67 PRG:1E67 A2 0A
|
|
; Routine: Menu_TransferVramDataPath_DE69
|
|
; Global: Reachable code entry at CPU $DE69 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DE69:
|
|
lda $DE78,x ; CPU:$DE69 PRG:1E69 BD 78 DE
|
|
sta PPUDATA ; CPU:$DE6C PRG:1E6C 8D 07 20
|
|
dex ; CPU:$DE6F PRG:1E6F CA
|
|
bpl Menu_TransferVramDataPath_DE69 ; CPU:$DE70 PRG:1E70 10 F7
|
|
jsr EnableNmiInPpuControl ; CPU:$DE72 PRG:1E72 20 B0 C2
|
|
jmp Ppu_CallHelper_C23B ; CPU:$DE75 PRG:1E75 4C 3B C2
|
|
|
|
; Data region: CPU $DE78-$DE82; unreachable by direct recursive trace.
|
|
StatusScreenPaletteAddressTable:
|
|
.byte $45, $47, $41, $54, $53, $3A, $53, $55, $4E, $4F, $42 ; CPU:$DE78 PRG:1E78 45 47 41 54 53 3A 53 55 4E 4F 42
|
|
; Routine: ComposeStatusScreen
|
|
; Global: Reachable code entry at CPU $DE83 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
ComposeStatusScreen:
|
|
jsr DisableRendering ; CPU:$DE83 PRG:1E83 20 57 C2
|
|
jsr Ppu_HandleControl_C215 ; CPU:$DE86 PRG:1E86 20 15 C2
|
|
jsr WaitForVBlankTransition ; CPU:$DE89 PRG:1E89 20 8B C2
|
|
lda #$3F ; CPU:$DE8C PRG:1E8C A9 3F
|
|
ldx #$00 ; CPU:$DE8E PRG:1E8E A2 00
|
|
jsr SetPpuAddress ; CPU:$DE90 PRG:1E90 20 96 C1
|
|
ldx #$00 ; CPU:$DE93 PRG:1E93 A2 00
|
|
; Routine: Menu_TransferVramDataPath_DE95
|
|
; Global: Reachable code entry at CPU $DE95 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DE95:
|
|
lda $DF90,x ; CPU:$DE95 PRG:1E95 BD 90 DF
|
|
sta PPUDATA ; CPU:$DE98 PRG:1E98 8D 07 20
|
|
inx ; CPU:$DE9B PRG:1E9B E8
|
|
cpx #$10 ; CPU:$DE9C PRG:1E9C E0 10
|
|
bne Menu_TransferVramDataPath_DE95 ; CPU:$DE9E PRG:1E9E D0 F5
|
|
jsr Ppu_SetVramAddress_C2D6 ; CPU:$DEA0 PRG:1EA0 20 D6 C2
|
|
jsr RenderEncodedTextRecords ; CPU:$DEA3 PRG:1EA3 20 C0 E1
|
|
lda #$20 ; CPU:$DEA6 PRG:1EA6 A9 20
|
|
ldx #$00 ; CPU:$DEA8 PRG:1EA8 A2 00
|
|
jsr SetPpuAddress ; CPU:$DEAA PRG:1EAA 20 96 C1
|
|
ldx #$40 ; CPU:$DEAD PRG:1EAD A2 40
|
|
lda #$B0 ; CPU:$DEAF PRG:1EAF A9 B0
|
|
; Routine: Menu_TransferVramDataPath_DEB1
|
|
; Global: Reachable code entry at CPU $DEB1 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DEB1:
|
|
sta PPUDATA ; CPU:$DEB1 PRG:1EB1 8D 07 20
|
|
dex ; CPU:$DEB4 PRG:1EB4 CA
|
|
bne Menu_TransferVramDataPath_DEB1 ; CPU:$DEB5 PRG:1EB5 D0 FA
|
|
ldx #$00 ; CPU:$DEB7 PRG:1EB7 A2 00
|
|
; Routine: Menu_TransferVramDataPath_DEB9
|
|
; Global: Reachable code entry at CPU $DEB9 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DEB9:
|
|
lda $DFB0,x ; CPU:$DEB9 PRG:1EB9 BD B0 DF
|
|
sta PPUDATA ; CPU:$DEBC PRG:1EBC 8D 07 20
|
|
inx ; CPU:$DEBF PRG:1EBF E8
|
|
bne Menu_TransferVramDataPath_DEB9 ; CPU:$DEC0 PRG:1EC0 D0 F7
|
|
; Routine: Menu_TransferVramDataPath_DEC2
|
|
; Global: Reachable code entry at CPU $DEC2 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DEC2:
|
|
lda $E0B0,x ; CPU:$DEC2 PRG:1EC2 BD B0 E0
|
|
sta PPUDATA ; CPU:$DEC5 PRG:1EC5 8D 07 20
|
|
inx ; CPU:$DEC8 PRG:1EC8 E8
|
|
bne Menu_TransferVramDataPath_DEC2 ; CPU:$DEC9 PRG:1EC9 D0 F7
|
|
lda #$22 ; CPU:$DECB PRG:1ECB A9 22
|
|
ldx #$AE ; CPU:$DECD PRG:1ECD A2 AE
|
|
jsr SetPpuAddress ; CPU:$DECF PRG:1ECF 20 96 C1
|
|
ldx #$00 ; CPU:$DED2 PRG:1ED2 A2 00
|
|
; Routine: Menu_TransferVramDataPath_DED4
|
|
; Global: Reachable code entry at CPU $DED4 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DED4:
|
|
lda $01,x ; CPU:$DED4 PRG:1ED4 B5 01
|
|
bne Menu_TransferVramDataPath_DEE4 ; CPU:$DED6 PRG:1ED6 D0 0C
|
|
lda #$3A ; CPU:$DED8 PRG:1ED8 A9 3A
|
|
sta PPUDATA ; CPU:$DEDA PRG:1EDA 8D 07 20
|
|
inx ; CPU:$DEDD PRG:1EDD E8
|
|
cpx #$07 ; CPU:$DEDE PRG:1EDE E0 07
|
|
bne Menu_TransferVramDataPath_DED4 ; CPU:$DEE0 PRG:1EE0 D0 F2
|
|
beq Menu_TransferVramDataPath_DEF1 ; CPU:$DEE2 PRG:1EE2 F0 0D
|
|
; Routine: Menu_TransferVramDataPath_DEE4
|
|
; Global: Reachable code entry at CPU $DEE4 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DEE4:
|
|
lda $01,x ; CPU:$DEE4 PRG:1EE4 B5 01
|
|
clc ; CPU:$DEE6 PRG:1EE6 18
|
|
adc #$30 ; CPU:$DEE7 PRG:1EE7 69 30
|
|
sta PPUDATA ; CPU:$DEE9 PRG:1EE9 8D 07 20
|
|
inx ; CPU:$DEEC PRG:1EEC E8
|
|
cpx #$07 ; CPU:$DEED PRG:1EED E0 07
|
|
bne Menu_TransferVramDataPath_DEE4 ; CPU:$DEEF PRG:1EEF D0 F3
|
|
; Routine: Menu_TransferVramDataPath_DEF1
|
|
; Global: Reachable code entry at CPU $DEF1 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DEF1:
|
|
lda #$30 ; CPU:$DEF1 PRG:1EF1 A9 30
|
|
sta PPUDATA ; CPU:$DEF3 PRG:1EF3 8D 07 20
|
|
sta PPUDATA ; CPU:$DEF6 PRG:1EF6 8D 07 20
|
|
lda #$23 ; CPU:$DEF9 PRG:1EF9 A9 23
|
|
ldx #$C0 ; CPU:$DEFB PRG:1EFB A2 C0
|
|
jsr SetPpuAddress ; CPU:$DEFD PRG:1EFD 20 96 C1
|
|
ldx #$20 ; CPU:$DF00 PRG:1F00 A2 20
|
|
lda #$00 ; CPU:$DF02 PRG:1F02 A9 00
|
|
; Routine: Menu_TransferVramDataPath_DF04
|
|
; Global: Reachable code entry at CPU $DF04 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DF04:
|
|
sta PPUDATA ; CPU:$DF04 PRG:1F04 8D 07 20
|
|
dex ; CPU:$DF07 PRG:1F07 CA
|
|
bne Menu_TransferVramDataPath_DF04 ; CPU:$DF08 PRG:1F08 D0 FA
|
|
ldx #$08 ; CPU:$DF0A PRG:1F0A A2 08
|
|
lda #$50 ; CPU:$DF0C PRG:1F0C A9 50
|
|
; Routine: Menu_TransferVramDataPath_DF0E
|
|
; Global: Reachable code entry at CPU $DF0E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DF0E:
|
|
sta PPUDATA ; CPU:$DF0E PRG:1F0E 8D 07 20
|
|
dex ; CPU:$DF11 PRG:1F11 CA
|
|
bne Menu_TransferVramDataPath_DF0E ; CPU:$DF12 PRG:1F12 D0 FA
|
|
ldx #$18 ; CPU:$DF14 PRG:1F14 A2 18
|
|
lda #$55 ; CPU:$DF16 PRG:1F16 A9 55
|
|
; Routine: Menu_TransferVramDataPath_DF18
|
|
; Global: Reachable code entry at CPU $DF18 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DF18:
|
|
sta PPUDATA ; CPU:$DF18 PRG:1F18 8D 07 20
|
|
dex ; CPU:$DF1B PRG:1F1B CA
|
|
bne Menu_TransferVramDataPath_DF18 ; CPU:$DF1C PRG:1F1C D0 FA
|
|
jsr CommitPpuStateAndScroll ; CPU:$DF1E PRG:1F1E 20 96 C2
|
|
jsr EnableNmiInPpuControl ; CPU:$DF21 PRG:1F21 20 B0 C2
|
|
jmp Ppu_CallHelper_C23B ; CPU:$DF24 PRG:1F24 4C 3B C2
|
|
; Routine: UploadMenuPalette
|
|
; Global: Reachable code entry at CPU $DF27 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
UploadMenuPalette:
|
|
lda #$00 ; CPU:$DF27 PRG:1F27 A9 00
|
|
sta $0E ; CPU:$DF29 PRG:1F29 85 0E
|
|
jsr WaitForVBlankTransition ; CPU:$DF2B PRG:1F2B 20 8B C2
|
|
lda #$3F ; CPU:$DF2E PRG:1F2E A9 3F
|
|
ldx #$00 ; CPU:$DF30 PRG:1F30 A2 00
|
|
jsr SetPpuAddress ; CPU:$DF32 PRG:1F32 20 96 C1
|
|
ldx #$00 ; CPU:$DF35 PRG:1F35 A2 00
|
|
; Routine: Menu_TransferVramDataPath_DF37
|
|
; Global: Reachable code entry at CPU $DF37 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DF37:
|
|
lda $DF8C,x ; CPU:$DF37 PRG:1F37 BD 8C DF
|
|
sta PPUDATA ; CPU:$DF3A PRG:1F3A 8D 07 20
|
|
inx ; CPU:$DF3D PRG:1F3D E8
|
|
cpx #$10 ; CPU:$DF3E PRG:1F3E E0 10
|
|
bne Menu_TransferVramDataPath_DF37 ; CPU:$DF40 PRG:1F40 D0 F5
|
|
jsr Ppu_SetVramAddress_C2D6 ; CPU:$DF42 PRG:1F42 20 D6 C2
|
|
jmp Ppu_HandleControl_C215 ; CPU:$DF45 PRG:1F45 4C 15 C2
|
|
; Routine: Menu_HandleControl_DF48
|
|
; Global: Reachable code entry at CPU $DF48 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_HandleControl_DF48:
|
|
ldy #$30 ; CPU:$DF48 PRG:1F48 A0 30
|
|
sec ; CPU:$DF4A PRG:1F4A 38
|
|
; Routine: Menu_HandleControl_DF4B
|
|
; Global: Reachable code entry at CPU $DF4B traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_HandleControl_DF4B:
|
|
sbc #$64 ; CPU:$DF4B PRG:1F4B E9 64
|
|
bcc Menu_TransferVramDataPath_DF52 ; CPU:$DF4D PRG:1F4D 90 03
|
|
iny ; CPU:$DF4F PRG:1F4F C8
|
|
bne Menu_HandleControl_DF4B ; CPU:$DF50 PRG:1F50 D0 F9
|
|
; Routine: Menu_TransferVramDataPath_DF52
|
|
; Global: Reachable code entry at CPU $DF52 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DF52:
|
|
adc #$64 ; CPU:$DF52 PRG:1F52 69 64
|
|
cpy #$30 ; CPU:$DF54 PRG:1F54 C0 30
|
|
bne Menu_TransferVramDataPath_DF76 ; CPU:$DF56 PRG:1F56 D0 1E
|
|
ldy #$3A ; CPU:$DF58 PRG:1F58 A0 3A
|
|
sty PPUDATA ; CPU:$DF5A PRG:1F5A 8C 07 20
|
|
; Routine: Menu_HandleControl_DF5D
|
|
; Global: Reachable code entry at CPU $DF5D traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_HandleControl_DF5D:
|
|
ldy #$30 ; CPU:$DF5D PRG:1F5D A0 30
|
|
sec ; CPU:$DF5F PRG:1F5F 38
|
|
; Routine: Menu_HandleControl_DF60
|
|
; Global: Reachable code entry at CPU $DF60 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_HandleControl_DF60:
|
|
sbc #$0A ; CPU:$DF60 PRG:1F60 E9 0A
|
|
bcc Menu_HandleControl_DF67 ; CPU:$DF62 PRG:1F62 90 03
|
|
iny ; CPU:$DF64 PRG:1F64 C8
|
|
bne Menu_HandleControl_DF60 ; CPU:$DF65 PRG:1F65 D0 F9
|
|
; Routine: Menu_HandleControl_DF67
|
|
; Global: Reachable code entry at CPU $DF67 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_HandleControl_DF67:
|
|
adc #$3A ; CPU:$DF67 PRG:1F67 69 3A
|
|
cpy #$30 ; CPU:$DF69 PRG:1F69 C0 30
|
|
bne Menu_TransferVramDataPath_DF6F ; CPU:$DF6B PRG:1F6B D0 02
|
|
ldy #$3A ; CPU:$DF6D PRG:1F6D A0 3A
|
|
; Routine: Menu_TransferVramDataPath_DF6F
|
|
; Global: Reachable code entry at CPU $DF6F traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DF6F:
|
|
sty PPUDATA ; CPU:$DF6F PRG:1F6F 8C 07 20
|
|
sta PPUDATA ; CPU:$DF72 PRG:1F72 8D 07 20
|
|
rts ; CPU:$DF75 PRG:1F75 60
|
|
; Routine: Menu_TransferVramDataPath_DF76
|
|
; Global: Reachable code entry at CPU $DF76 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DF76:
|
|
sty PPUDATA ; CPU:$DF76 PRG:1F76 8C 07 20
|
|
ldy #$30 ; CPU:$DF79 PRG:1F79 A0 30
|
|
sec ; CPU:$DF7B PRG:1F7B 38
|
|
; Routine: Menu_HandleControl_DF7C
|
|
; Global: Reachable code entry at CPU $DF7C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_HandleControl_DF7C:
|
|
sbc #$0A ; CPU:$DF7C PRG:1F7C E9 0A
|
|
bcc Menu_TransferVramDataPath_DF83 ; CPU:$DF7E PRG:1F7E 90 03
|
|
iny ; CPU:$DF80 PRG:1F80 C8
|
|
bne Menu_HandleControl_DF7C ; CPU:$DF81 PRG:1F81 D0 F9
|
|
; Routine: Menu_TransferVramDataPath_DF83
|
|
; Global: Reachable code entry at CPU $DF83 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Menu_TransferVramDataPath_DF83:
|
|
adc #$3A ; CPU:$DF83 PRG:1F83 69 3A
|
|
sty PPUDATA ; CPU:$DF85 PRG:1F85 8C 07 20
|
|
sta PPUDATA ; CPU:$DF88 PRG:1F88 8D 07 20
|
|
rts ; CPU:$DF8B PRG:1F8B 60
|
|
|
|
; Data region: CPU $DF8C-$E1BF; unreachable by direct recursive trace.
|
|
MenuPaletteAndScreenData:
|
|
.byte $0F, $00, $0F, $30, $0F, $05, $30, $28, $0F, $00, $0F, $30, $0F, $06, $26, $37 ; CPU:$DF8C PRG:1F8C 0F 00 0F 30 0F 05 30 28 0F 00 0F 30 0F 06 26 37
|
|
.byte $0F, $0F, $0F, $0F, $05, $00, $09, $04, $0D, $07, $02, $06, $0A, $0F, $0C, $03 ; CPU:$DF9C PRG:1F9C 0F 0F 0F 0F 05 00 09 04 0D 07 02 06 0A 0F 0C 03
|
|
.byte $08, $0B, $0E, $01, $B0, $B0, $DF, $C0, $C1, $C1, $C2, $C0, $C1, $C1, $C1, $C2 ; CPU:$DFAC PRG:1FAC 08 0B 0E 01 B0 B0 DF C0 C1 C1 C2 C0 C1 C1 C1 C2
|
|
.byte $C0, $B6, $E9, $B8, $C2, $C0, $C1, $C1, $C2, $C0, $C1, $C1, $C2, $C0, $C1, $C1 ; CPU:$DFBC PRG:1FBC C0 B6 E9 B8 C2 C0 C1 C1 C2 C0 C1 C1 C2 C0 C1 C1
|
|
.byte $C2, $E9, $F8, $B0, $B0, $B0, $DF, $C1, $D9, $D3, $B3, $C1, $D9, $CB, $D3, $B3 ; CPU:$DFCC PRG:1FCC C2 E9 F8 B0 B0 B0 DF C1 D9 D3 B3 C1 D9 CB D3 B3
|
|
.byte $C1, $C5, $C6, $C1, $B3, $C1, $D9, $D3, $B3, $C1, $D9, $CB, $CB, $C1, $D9, $D3 ; CPU:$DFDC PRG:1FDC C1 C5 C6 C1 B3 C1 D9 D3 B3 C1 D9 CB CB C1 D9 D3
|
|
.byte $B3, $EE, $F8, $B0, $B0, $B0, $DF, $C1, $D0, $D1, $D2, $C1, $CF, $E9, $C4, $B3 ; CPU:$DFEC PRG:1FEC B3 EE F8 B0 B0 B0 DF C1 D0 D1 D2 C1 CF E9 C4 B3
|
|
.byte $C1, $D5, $D6, $D7, $B3, $C1, $D0, $D1, $D2, $C1, $D0, $DC, $E9, $C1, $D0, $D1 ; CPU:$DFFC PRG:1FFC C1 D5 D6 D7 B3 C1 D0 D1 D2 C1 D0 DC E9 C1 D0 D1
|
|
.byte $D2, $EB, $F8, $B0, $B0, $B0, $DF, $C1, $E0, $E1, $E2, $C1, $CF, $E9, $C4, $B3 ; CPU:$E00C PRG:200C D2 EB F8 B0 B0 B0 DF C1 E0 E1 E2 C1 CF E9 C4 B3
|
|
.byte $C1, $B7, $E6, $E7, $B3, $C1, $E0, $E1, $E2, $C1, $E0, $F5, $EC, $C1, $E0, $E1 ; CPU:$E01C PRG:201C C1 B7 E6 E7 B3 C1 E0 E1 E2 C1 E0 F5 EC C1 E0 E1
|
|
.byte $E2, $EF, $F8, $B0, $B0, $B0, $DF, $C1, $E8, $DA, $B3, $C1, $CF, $E9, $C4, $B3 ; CPU:$E02C PRG:202C E2 EF F8 B0 B0 B0 DF C1 E8 DA B3 C1 CF E9 C4 B3
|
|
.byte $C1, $CF, $E5, $F0, $B3, $C1, $E8, $DA, $B3, $C1, $E8, $DB, $ED, $C1, $E8, $DA ; CPU:$E03C PRG:203C C1 CF E5 F0 B3 C1 E8 DA B3 C1 E8 DB ED C1 E8 DA
|
|
.byte $B3, $EB, $F8, $B0, $B0, $B0, $DF, $C1, $B5, $E3, $B3, $C1, $B5, $E9, $E3, $B3 ; CPU:$E04C PRG:204C B3 EB F8 B0 B0 B0 DF C1 B5 E3 B3 C1 B5 E9 E3 B3
|
|
.byte $C1, $CF, $E9, $C4, $B3, $C1, $B5, $E3, $B3, $C1, $B5, $E9, $E9, $C1, $CF, $C4 ; CPU:$E05C PRG:205C C1 CF E9 C4 B3 C1 B5 E3 B3 C1 B5 E9 E9 C1 CF C4
|
|
.byte $B3, $EB, $F8, $B0, $B0, $B0, $DF, $B1, $C1, $F1, $C3, $C7, $C1, $C1, $F1, $C3 ; CPU:$E06C PRG:206C B3 EB F8 B0 B0 B0 DF B1 C1 F1 C3 C7 C1 C1 F1 C3
|
|
.byte $B4, $CF, $E9, $B2, $C3, $C7, $C1, $F1, $C3, $C7, $C1, $C1, $C3, $B4, $CF, $B2 ; CPU:$E07C PRG:207C B4 CF E9 B2 C3 C7 C1 F1 C3 C7 C1 C1 C3 B4 CF B2
|
|
.byte $C3, $EB, $F8, $B0, $B0, $B0, $DF, $CA, $CB, $CB, $CB, $CE, $CB, $CB, $CB, $CB ; CPU:$E08C PRG:208C C3 EB F8 B0 B0 B0 DF CA CB CB CB CE CB CB CB CB
|
|
.byte $CE, $D8, $E9, $E9, $EA, $CE, $CB, $CB, $CB, $CE, $CB, $CB, $CB, $CE, $D8, $E9 ; CPU:$E09C PRG:209C CE D8 E9 E9 EA CE CB CB CB CE CB CB CB CE D8 E9
|
|
.byte $EA, $CD, $F8, $B0, $B0, $B0, $DF, $E9, $E9, $E9, $E9, $E9, $E9, $E9, $C0, $B6 ; CPU:$E0AC PRG:20AC EA CD F8 B0 B0 B0 DF E9 E9 E9 E9 E9 E9 E9 C0 B6
|
|
.byte $E9, $B8, $C2, $C0, $C1, $C1, $C2, $C0, $BC, $E4, $C2, $E9, $E9, $E9, $E9, $E9 ; CPU:$E0BC PRG:20BC E9 B8 C2 C0 C1 C1 C2 C0 BC E4 C2 E9 E9 E9 E9 E9
|
|
.byte $E9, $E9, $F8, $B0, $B0, $B0, $DF, $E9, $E9, $E9, $E9, $E9, $E9, $E9, $C1, $C5 ; CPU:$E0CC PRG:20CC E9 E9 F8 B0 B0 B0 DF E9 E9 E9 E9 E9 E9 E9 C1 C5
|
|
.byte $C6, $C1, $B3, $C1, $D9, $D3, $B3, $C1, $BD, $C4, $B3, $EE, $FB, $FC, $E9, $E9 ; CPU:$E0DC PRG:20DC C6 C1 B3 C1 D9 D3 B3 C1 BD C4 B3 EE FB FC E9 E9
|
|
.byte $E9, $E9, $F8, $B0, $B0, $B0, $DF, $E9, $E9, $E9, $E9, $E9, $E9, $E9, $C1, $D5 ; CPU:$E0EC PRG:20EC E9 E9 F8 B0 B0 B0 DF E9 E9 E9 E9 E9 E9 E9 C1 D5
|
|
.byte $D6, $D7, $B3, $C1, $D0, $D1, $B3, $C1, $BE, $F2, $B3, $EB, $E9, $E9, $E9, $E9 ; CPU:$E0FC PRG:20FC D6 D7 B3 C1 D0 D1 B3 C1 BE F2 B3 EB E9 E9 E9 E9
|
|
.byte $E9, $E9, $F8, $B0, $B0, $B0, $DF, $E9, $E9, $E9, $E9, $E9, $E9, $E9, $C1, $B7 ; CPU:$E10C PRG:210C E9 E9 F8 B0 B0 B0 DF E9 E9 E9 E9 E9 E9 E9 C1 B7
|
|
.byte $E6, $E7, $B3, $C1, $E0, $E1, $B3, $C1, $B9, $BF, $B3, $EB, $E9, $E9, $E9, $E9 ; CPU:$E11C PRG:211C E6 E7 B3 C1 E0 E1 B3 C1 B9 BF B3 EB E9 E9 E9 E9
|
|
.byte $E9, $E9, $F8, $B0, $B0, $B0, $DF, $E9, $E9, $E9, $E9, $E9, $E9, $E9, $C1, $CF ; CPU:$E12C PRG:212C E9 E9 F8 B0 B0 B0 DF E9 E9 E9 E9 E9 E9 E9 C1 CF
|
|
.byte $E5, $F0, $B3, $C1, $E8, $DA, $B3, $C1, $BB, $C8, $B3, $EB, $E9, $E9, $E9, $E9 ; CPU:$E13C PRG:213C E5 F0 B3 C1 E8 DA B3 C1 BB C8 B3 EB E9 E9 E9 E9
|
|
.byte $E9, $E9, $F8, $B0, $B0, $B0, $DF, $E9, $E9, $E9, $E9, $E9, $E9, $E9, $C1, $CF ; CPU:$E14C PRG:214C E9 E9 F8 B0 B0 B0 DF E9 E9 E9 E9 E9 E9 E9 C1 CF
|
|
.byte $E9, $C4, $B3, $C1, $CF, $C4, $B3, $C1, $C9, $C1, $B3, $EB, $E9, $E9, $E9, $E9 ; CPU:$E15C PRG:215C E9 C4 B3 C1 CF C4 B3 C1 C9 C1 B3 EB E9 E9 E9 E9
|
|
.byte $E9, $E9, $F8, $B0, $B0, $B0, $DF, $E9, $E9, $E9, $E9, $E9, $E9, $E9, $D4, $CF ; CPU:$E16C PRG:216C E9 E9 F8 B0 B0 B0 DF E9 E9 E9 E9 E9 E9 E9 D4 CF
|
|
.byte $E9, $B2, $C3, $B4, $CF, $B2, $C3, $B4, $CF, $BA, $C3, $EB, $E9, $E9, $E9, $E9 ; CPU:$E17C PRG:217C E9 B2 C3 B4 CF B2 C3 B4 CF BA C3 EB E9 E9 E9 E9
|
|
.byte $E9, $E9, $F8, $B0, $B0, $B0, $DF, $E9, $E9, $E9, $E9, $E9, $E9, $E9, $CA, $D8 ; CPU:$E18C PRG:218C E9 E9 F8 B0 B0 B0 DF E9 E9 E9 E9 E9 E9 E9 CA D8
|
|
.byte $E9, $E9, $EA, $CE, $D8, $E9, $EA, $CE, $D8, $F3, $CB, $CD, $E9, $E9, $E9, $E9 ; CPU:$E19C PRG:219C E9 E9 EA CE D8 E9 EA CE D8 F3 CB CD E9 E9 E9 E9
|
|
.byte $E9, $E9, $F8, $B0, $B0, $B0, $F4, $F9, $F9, $F9, $F9, $F9, $F9, $F9, $F9, $F9 ; CPU:$E1AC PRG:21AC E9 E9 F8 B0 B0 B0 F4 F9 F9 F9 F9 F9 F9 F9 F9 F9
|
|
.byte $F9, $F9, $F9, $F9 ; CPU:$E1BC PRG:21BC F9 F9 F9 F9
|
|
; Routine: RenderEncodedTextRecords
|
|
; Global: Reachable code entry at CPU $E1C0 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
RenderEncodedTextRecords:
|
|
ldy #$00 ; CPU:$E1C0 PRG:21C0 A0 00
|
|
ldx #$05 ; CPU:$E1C2 PRG:21C2 A2 05
|
|
; Routine: Gameplay_SetVramAddressPath_E1C4
|
|
; Global: Reachable code entry at CPU $E1C4 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_SetVramAddressPath_E1C4:
|
|
jsr Gameplay_ReadRamE1E5_E1E0 ; CPU:$E1C4 PRG:21C4 20 E0 E1
|
|
sta PPUADDR ; CPU:$E1C7 PRG:21C7 8D 06 20
|
|
jsr Gameplay_ReadRamE1E5_E1E0 ; CPU:$E1CA PRG:21CA 20 E0 E1
|
|
sta PPUADDR ; CPU:$E1CD PRG:21CD 8D 06 20
|
|
; Routine: Gameplay_TransferVramDataPath_E1D0
|
|
; Global: Reachable code entry at CPU $E1D0 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_TransferVramDataPath_E1D0:
|
|
jsr Gameplay_ReadRamE1E5_E1E0 ; CPU:$E1D0 PRG:21D0 20 E0 E1
|
|
cmp #$FF ; CPU:$E1D3 PRG:21D3 C9 FF
|
|
beq Gameplay_RetreatIndexX_E1DC ; CPU:$E1D5 PRG:21D5 F0 05
|
|
sta PPUDATA ; CPU:$E1D7 PRG:21D7 8D 07 20
|
|
bne Gameplay_TransferVramDataPath_E1D0 ; CPU:$E1DA PRG:21DA D0 F4
|
|
; Routine: Gameplay_RetreatIndexX_E1DC
|
|
; Global: Reachable code entry at CPU $E1DC traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_RetreatIndexX_E1DC:
|
|
dex ; CPU:$E1DC PRG:21DC CA
|
|
bne Gameplay_SetVramAddressPath_E1C4 ; CPU:$E1DD PRG:21DD D0 E5
|
|
rts ; CPU:$E1DF PRG:21DF 60
|
|
; Routine: Gameplay_ReadRamE1E5_E1E0
|
|
; Global: Reachable code entry at CPU $E1E0 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadRamE1E5_E1E0:
|
|
lda $E1E5,y ; CPU:$E1E0 PRG:21E0 B9 E5 E1
|
|
iny ; CPU:$E1E3 PRG:21E3 C8
|
|
rts ; CPU:$E1E4 PRG:21E4 60
|
|
|
|
; Data region: CPU $E1E5-$E2BC; unreachable by direct recursive trace.
|
|
TitleAndCopyrightText:
|
|
.byte $22, $69, $53, $54, $41, $52, $54, $B0, $B0, $B0, $43, $4F, $4E, $54, $49, $4E ; CPU:$E1E5 PRG:21E5 22 69 53 54 41 52 54 B0 B0 B0 43 4F 4E 54 49 4E
|
|
.byte $55, $45, $FF, $22, $AA, $54, $4F, $50, $FF, $22, $E3, $54, $4D, $B0, $41, $4E ; CPU:$E1F5 PRG:21F5 55 45 FF 22 AA 54 4F 50 FF 22 E3 54 4D B0 41 4E
|
|
.byte $44, $B0, $FE, $B0, $31, $39, $38, $37, $B0, $48, $55, $44, $53, $4F, $4E, $B0 ; CPU:$E205 PRG:2205 44 B0 FE B0 31 39 38 37 B0 48 55 44 53 4F 4E B0
|
|
.byte $53, $4F, $46, $54, $FF, $23, $2A, $4C, $49, $43, $45, $4E, $53, $45, $44, $B0 ; CPU:$E215 PRG:2215 53 4F 46 54 FF 23 2A 4C 49 43 45 4E 53 45 44 B0
|
|
.byte $42, $59, $FF, $23, $64, $4E, $49, $4E, $54, $45, $4E, $44, $4F, $B0, $4F, $46 ; CPU:$E225 PRG:2225 42 59 FF 23 64 4E 49 4E 54 45 4E 44 4F B0 4F 46
|
|
.byte $B0, $41, $4D, $45, $52, $49, $43, $41, $B0, $49, $4E, $43, $FD, $FF, $01, $01 ; CPU:$E235 PRG:2235 B0 41 4D 45 52 49 43 41 B0 49 4E 43 FD FF 01 01
|
|
.byte $01, $01, $01, $01, $01, $01, $01, $01, $01, $01, $01, $01, $01, $01, $01, $01 ; CPU:$E245 PRG:2245 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
|
|
.byte $01, $01, $01, $01, $01, $01, $01, $01, $01, $01, $01, $01, $01, $01, $01, $00 ; CPU:$E255 PRG:2255 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 00
|
|
.byte $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; CPU:$E265 PRG:2265 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
.byte $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $01, $01, $01, $00 ; CPU:$E275 PRG:2275 00 00 00 00 00 00 00 00 00 00 00 00 01 01 01 00
|
|
.byte $01, $00, $01, $00, $01, $00, $01, $00, $01, $00, $01, $00, $01, $00, $01, $00 ; CPU:$E285 PRG:2285 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
|
.byte $01, $00, $01, $00, $01, $00, $01, $00, $01, $00, $01, $00, $01, $01, $00, $20 ; CPU:$E295 PRG:2295 01 00 01 00 01 00 01 00 01 00 01 00 01 01 00 20
|
|
.byte $40, $60, $80, $A0, $C0, $E0, $00, $20, $40, $60, $80, $02, $02, $02, $02, $02 ; CPU:$E2A5 PRG:22A5 40 60 80 A0 C0 E0 00 20 40 60 80 02 02 02 02 02
|
|
.byte $02, $02, $02, $03, $03, $03, $03, $03 ; CPU:$E2B5 PRG:22B5 02 02 02 03 03 03 03 03
|
|
; Routine: Gameplay_ReadObjectMode_E2BD
|
|
; Global: Reachable code entry at CPU $E2BD traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadObjectMode_E2BD:
|
|
lda $73 ; CPU:$E2BD PRG:22BD A5 73
|
|
lsr a ; CPU:$E2BF PRG:22BF 4A
|
|
lsr a ; CPU:$E2C0 PRG:22C0 4A
|
|
lsr a ; CPU:$E2C1 PRG:22C1 4A
|
|
lsr a ; CPU:$E2C2 PRG:22C2 4A
|
|
sta $DC ; CPU:$E2C3 PRG:22C3 85 DC
|
|
lda $58 ; CPU:$E2C5 PRG:22C5 A5 58
|
|
and #$0F ; CPU:$E2C7 PRG:22C7 29 0F
|
|
sta $DD ; CPU:$E2C9 PRG:22C9 85 DD
|
|
lda $58 ; CPU:$E2CB PRG:22CB A5 58
|
|
lsr a ; CPU:$E2CD PRG:22CD 4A
|
|
lsr a ; CPU:$E2CE PRG:22CE 4A
|
|
lsr a ; CPU:$E2CF PRG:22CF 4A
|
|
lsr a ; CPU:$E2D0 PRG:22D0 4A
|
|
sta $DE ; CPU:$E2D1 PRG:22D1 85 DE
|
|
ldy #$00 ; CPU:$E2D3 PRG:22D3 A0 00
|
|
ldx #$00 ; CPU:$E2D5 PRG:22D5 A2 00
|
|
lda #$03 ; CPU:$E2D7 PRG:22D7 A9 03
|
|
sta $1F ; CPU:$E2D9 PRG:22D9 85 1F
|
|
; Routine: Gameplay_ReadObjectWorkX_E2DB
|
|
; Global: Reachable code entry at CPU $E2DB traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadObjectWorkX_E2DB:
|
|
jsr Gameplay_WriteWorkValue_E33C ; CPU:$E2DB PRG:22DB 20 3C E3
|
|
jsr Gameplay_ReadRamE360_E353 ; CPU:$E2DE PRG:22DE 20 53 E3
|
|
lda $24 ; CPU:$E2E1 PRG:22E1 A5 24
|
|
sta ($34),y ; CPU:$E2E3 PRG:22E3 91 34
|
|
dec $1F ; CPU:$E2E5 PRG:22E5 C6 1F
|
|
bne Gameplay_ReadObjectWorkX_E2DB ; CPU:$E2E7 PRG:22E7 D0 F2
|
|
jsr Gameplay_WriteWorkValue_E33C ; CPU:$E2E9 PRG:22E9 20 3C E3
|
|
lda $99 ; CPU:$E2EC PRG:22EC A5 99
|
|
asl a ; CPU:$E2EE PRG:22EE 0A
|
|
clc ; CPU:$E2EF PRG:22EF 18
|
|
adc $24 ; CPU:$E2F0 PRG:22F0 65 24
|
|
sta $24 ; CPU:$E2F2 PRG:22F2 85 24
|
|
lda $9A ; CPU:$E2F4 PRG:22F4 A5 9A
|
|
asl a ; CPU:$E2F6 PRG:22F6 0A
|
|
clc ; CPU:$E2F7 PRG:22F7 18
|
|
adc $24 ; CPU:$E2F8 PRG:22F8 65 24
|
|
sta $24 ; CPU:$E2FA PRG:22FA 85 24
|
|
lda $9B ; CPU:$E2FC PRG:22FC A5 9B
|
|
asl a ; CPU:$E2FE PRG:22FE 0A
|
|
clc ; CPU:$E2FF PRG:22FF 18
|
|
adc $24 ; CPU:$E300 PRG:2300 65 24
|
|
sta $95 ; CPU:$E302 PRG:2302 85 95
|
|
ldy #$00 ; CPU:$E304 PRG:2304 A0 00
|
|
sty RandomState0 ; CPU:$E306 PRG:2306 84 54
|
|
ldx #$00 ; CPU:$E308 PRG:2308 A2 00
|
|
; Routine: Gameplay_ReadTransferPointer_E30A
|
|
; Global: Reachable code entry at CPU $E30A traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadTransferPointer_E30A:
|
|
jsr Gameplay_ReadRamE360_E353 ; CPU:$E30A PRG:230A 20 53 E3
|
|
lda ($34),y ; CPU:$E30D PRG:230D B1 34
|
|
and #$0F ; CPU:$E30F PRG:230F 29 0F
|
|
sec ; CPU:$E311 PRG:2311 38
|
|
sbc RandomState0 ; CPU:$E312 PRG:2312 E5 54
|
|
sec ; CPU:$E314 PRG:2314 38
|
|
sbc #$07 ; CPU:$E315 PRG:2315 E9 07
|
|
and #$0F ; CPU:$E317 PRG:2317 29 0F
|
|
sta $0180,x ; CPU:$E319 PRG:2319 9D 80 01
|
|
sta RandomState0 ; CPU:$E31C PRG:231C 85 54
|
|
cpx #$28 ; CPU:$E31E PRG:231E E0 28
|
|
bne Gameplay_ReadTransferPointer_E30A ; CPU:$E320 PRG:2320 D0 E8
|
|
lda #$23 ; CPU:$E322 PRG:2322 A9 23
|
|
ldx #$06 ; CPU:$E324 PRG:2324 A2 06
|
|
jsr SetPpuAddress ; CPU:$E326 PRG:2326 20 96 C1
|
|
ldx #$02 ; CPU:$E329 PRG:2329 A2 02
|
|
; Routine: Gameplay_TransferVramDataPath_E32B
|
|
; Global: Reachable code entry at CPU $E32B traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_TransferVramDataPath_E32B:
|
|
lda $0180,x ; CPU:$E32B PRG:232B BD 80 01
|
|
tay ; CPU:$E32E PRG:232E A8
|
|
lda $E388,y ; CPU:$E32F PRG:232F B9 88 E3
|
|
sta PPUDATA ; CPU:$E332 PRG:2332 8D 07 20
|
|
inx ; CPU:$E335 PRG:2335 E8
|
|
inx ; CPU:$E336 PRG:2336 E8
|
|
cpx #$2A ; CPU:$E337 PRG:2337 E0 2A
|
|
bne Gameplay_TransferVramDataPath_E32B ; CPU:$E339 PRG:2339 D0 F0
|
|
rts ; CPU:$E33B PRG:233B 60
|
|
; Routine: Gameplay_WriteWorkValue_E33C
|
|
; Global: Reachable code entry at CPU $E33C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteWorkValue_E33C:
|
|
lda #$04 ; CPU:$E33C PRG:233C A9 04
|
|
sta $20 ; CPU:$E33E PRG:233E 85 20
|
|
lda #$00 ; CPU:$E340 PRG:2340 A9 00
|
|
sta $24 ; CPU:$E342 PRG:2342 85 24
|
|
; Routine: Gameplay_ReadTransferPointer_E344
|
|
; Global: Reachable code entry at CPU $E344 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadTransferPointer_E344:
|
|
jsr Gameplay_ReadRamE360_E353 ; CPU:$E344 PRG:2344 20 53 E3
|
|
lda ($34),y ; CPU:$E347 PRG:2347 B1 34
|
|
clc ; CPU:$E349 PRG:2349 18
|
|
adc $24 ; CPU:$E34A PRG:234A 65 24
|
|
sta $24 ; CPU:$E34C PRG:234C 85 24
|
|
dec $20 ; CPU:$E34E PRG:234E C6 20
|
|
bne Gameplay_ReadTransferPointer_E344 ; CPU:$E350 PRG:2350 D0 F2
|
|
rts ; CPU:$E352 PRG:2352 60
|
|
; Routine: Gameplay_ReadRamE360_E353
|
|
; Global: Reachable code entry at CPU $E353 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadRamE360_E353:
|
|
lda $E360,x ; CPU:$E353 PRG:2353 BD 60 E3
|
|
sta $34 ; CPU:$E356 PRG:2356 85 34
|
|
inx ; CPU:$E358 PRG:2358 E8
|
|
lda $E360,x ; CPU:$E359 PRG:2359 BD 60 E3
|
|
sta $35 ; CPU:$E35C PRG:235C 85 35
|
|
inx ; CPU:$E35E PRG:235E E8
|
|
rts ; CPU:$E35F PRG:235F 60
|
|
|
|
; Data region: CPU $E360-$E397; unreachable by direct recursive trace.
|
|
GameplayScoreThresholdTable:
|
|
.byte $67, $00, $77, $00, $DD, $00, $61, $00, $99, $00, $66, $00, $DC, $00, $64, $00 ; CPU:$E360 PRG:2360 67 00 77 00 DD 00 61 00 99 00 66 00 DC 00 64 00
|
|
.byte $79, $00, $9A, $00, $74, $00, $63, $00, $75, $00, $62, $00, $9B, $00, $65, $00 ; CPU:$E370 PRG:2370 79 00 9A 00 74 00 63 00 75 00 62 00 9B 00 65 00
|
|
.byte $94, $00, $DE, $00, $76, $00, $95, $00, $41, $4F, $46, $4B, $43, $50, $47, $45 ; CPU:$E380 PRG:2380 94 00 DE 00 76 00 95 00 41 4F 46 4B 43 50 47 45
|
|
.byte $4C, $42, $48, $4D, $4A, $44, $4E, $49 ; CPU:$E390 PRG:2390 4C 42 48 4D 4A 44 4E 49
|
|
; Routine: Gameplay_ReturnToCaller_E398
|
|
; Global: Reachable code entry at CPU $E398 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReturnToCaller_E398:
|
|
rts ; CPU:$E398 PRG:2398 60
|
|
; Routine: Gameplay_ReadStageProgress_E399
|
|
; Global: Reachable code entry at CPU $E399 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadStageProgress_E399:
|
|
lda $9C ; CPU:$E399 PRG:2399 A5 9C
|
|
bne Gameplay_ReadPlayerState_E3A7 ; CPU:$E39B PRG:239B D0 0A
|
|
lda $B1 ; CPU:$E39D PRG:239D A5 B1
|
|
bne Gameplay_ReadPlayerState_E3A7 ; CPU:$E39F PRG:239F D0 06
|
|
inc $B1 ; CPU:$E3A1 PRG:23A1 E6 B1
|
|
lda #$06 ; CPU:$E3A3 PRG:23A3 A9 06
|
|
sta $DF ; CPU:$E3A5 PRG:23A5 85 DF
|
|
; Routine: Gameplay_ReadPlayerState_E3A7
|
|
; Global: Reachable code entry at CPU $E3A7 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadPlayerState_E3A7:
|
|
lda $A8 ; CPU:$E3A7 PRG:23A7 A5 A8
|
|
beq Gameplay_ReadObjectType_E3E7 ; CPU:$E3A9 PRG:23A9 F0 3C
|
|
cmp #$02 ; CPU:$E3AB PRG:23AB C9 02
|
|
beq Gameplay_ReturnToCaller_E398 ; CPU:$E3AD PRG:23AD F0 E9
|
|
lda $33 ; CPU:$E3AF PRG:23AF A5 33
|
|
and #$01 ; CPU:$E3B1 PRG:23B1 29 01
|
|
bne Gameplay_ReadZpAA_E3BD ; CPU:$E3B3 PRG:23B3 D0 08
|
|
dec $A9 ; CPU:$E3B5 PRG:23B5 C6 A9
|
|
bne Gameplay_ReadZpAA_E3BD ; CPU:$E3B7 PRG:23B7 D0 04
|
|
lda #$02 ; CPU:$E3B9 PRG:23B9 A9 02
|
|
sta $A8 ; CPU:$E3BB PRG:23BB 85 A8
|
|
; Routine: Gameplay_ReadZpAA_E3BD
|
|
; Global: Reachable code entry at CPU $E3BD traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadZpAA_E3BD:
|
|
jsr Object_ReadStageIndex_CFED ; CPU:$E3BD PRG:23BD 20 ED CF
|
|
lda $AA ; CPU:$E3C0 PRG:23C0 A5 AA
|
|
cmp $28 ; CPU:$E3C2 PRG:23C2 C5 28
|
|
bne Gameplay_ReturnToCaller_E3E6 ; CPU:$E3C4 PRG:23C4 D0 20
|
|
lda $2A ; CPU:$E3C6 PRG:23C6 A5 2A
|
|
cmp $AB ; CPU:$E3C8 PRG:23C8 C5 AB
|
|
bne Gameplay_ReturnToCaller_E3E6 ; CPU:$E3CA PRG:23CA D0 1A
|
|
lda #$04 ; CPU:$E3CC PRG:23CC A9 04
|
|
sta $DF ; CPU:$E3CE PRG:23CE 85 DF
|
|
ldx $9D ; CPU:$E3D0 PRG:23D0 A6 9D
|
|
lda $E4BC,x ; CPU:$E3D2 PRG:23D2 BD BC E4
|
|
cmp #$64 ; CPU:$E3D5 PRG:23D5 C9 64
|
|
bcc Gameplay_CallHelper_E3DF ; CPU:$E3D7 PRG:23D7 90 06
|
|
jsr Menu_WriteObjectWorkX_DD6B ; CPU:$E3D9 PRG:23D9 20 6B DD
|
|
jmp Gameplay_WritePlayerState_E3E2 ; CPU:$E3DC PRG:23DC 4C E2 E3
|
|
; Routine: Gameplay_CallHelper_E3DF
|
|
; Global: Reachable code entry at CPU $E3DF traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_CallHelper_E3DF:
|
|
jsr Menu_WriteObjectWorkX_DD77 ; CPU:$E3DF PRG:23DF 20 77 DD
|
|
; Routine: Gameplay_WritePlayerState_E3E2
|
|
; Global: Reachable code entry at CPU $E3E2 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WritePlayerState_E3E2:
|
|
lda #$02 ; CPU:$E3E2 PRG:23E2 A9 02
|
|
sta $A8 ; CPU:$E3E4 PRG:23E4 85 A8
|
|
; Routine: Gameplay_ReturnToCaller_E3E6
|
|
; Global: Reachable code entry at CPU $E3E6 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReturnToCaller_E3E6:
|
|
rts ; CPU:$E3E6 PRG:23E6 60
|
|
; Routine: Gameplay_ReadObjectType_E3E7
|
|
; Global: Reachable code entry at CPU $E3E7 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadObjectType_E3E7:
|
|
lda $28 ; CPU:$E3E7 PRG:23E7 A5 28
|
|
cmp #$01 ; CPU:$E3E9 PRG:23E9 C9 01
|
|
bne Gameplay_ReadObjectState_E401 ; CPU:$E3EB PRG:23EB D0 14
|
|
lda $2A ; CPU:$E3ED PRG:23ED A5 2A
|
|
cmp #$01 ; CPU:$E3EF PRG:23EF C9 01
|
|
bne Gameplay_IncrementRemoteControl_E3F8 ; CPU:$E3F1 PRG:23F1 D0 05
|
|
inc $A0 ; CPU:$E3F3 PRG:23F3 E6 A0
|
|
jmp Gameplay_ReadObjectType_E416 ; CPU:$E3F5 PRG:23F5 4C 16 E4
|
|
; Routine: Gameplay_IncrementRemoteControl_E3F8
|
|
; Global: Reachable code entry at CPU $E3F8 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_IncrementRemoteControl_E3F8:
|
|
cmp #$0B ; CPU:$E3F8 PRG:23F8 C9 0B
|
|
bne Gameplay_ReadObjectState_E401 ; CPU:$E3FA PRG:23FA D0 05
|
|
inc $A2 ; CPU:$E3FC PRG:23FC E6 A2
|
|
jmp Gameplay_ReadObjectType_E416 ; CPU:$E3FE PRG:23FE 4C 16 E4
|
|
; Routine: Gameplay_ReadObjectState_E401
|
|
; Global: Reachable code entry at CPU $E401 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadObjectState_E401:
|
|
cmp #$1D ; CPU:$E401 PRG:2401 C9 1D
|
|
bne Gameplay_ReadObjectType_E416 ; CPU:$E403 PRG:2403 D0 11
|
|
lda $2A ; CPU:$E405 PRG:2405 A5 2A
|
|
cmp #$01 ; CPU:$E407 PRG:2407 C9 01
|
|
bne Gameplay_IncrementWallPass_E410 ; CPU:$E409 PRG:2409 D0 05
|
|
inc $A1 ; CPU:$E40B PRG:240B E6 A1
|
|
jmp Gameplay_ReadObjectType_E416 ; CPU:$E40D PRG:240D 4C 16 E4
|
|
; Routine: Gameplay_IncrementWallPass_E410
|
|
; Global: Reachable code entry at CPU $E410 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_IncrementWallPass_E410:
|
|
cmp #$0B ; CPU:$E410 PRG:2410 C9 0B
|
|
bne Gameplay_ReadObjectType_E416 ; CPU:$E412 PRG:2412 D0 02
|
|
inc $A3 ; CPU:$E414 PRG:2414 E6 A3
|
|
; Routine: Gameplay_ReadObjectType_E416
|
|
; Global: Reachable code entry at CPU $E416 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadObjectType_E416:
|
|
lda $28 ; CPU:$E416 PRG:2416 A5 28
|
|
cmp #$01 ; CPU:$E418 PRG:2418 C9 01
|
|
beq Gameplay_ReadStageIndex_E434 ; CPU:$E41A PRG:241A F0 18
|
|
cmp #$1D ; CPU:$E41C PRG:241C C9 1D
|
|
beq Gameplay_ReadStageIndex_E434 ; CPU:$E41E PRG:241E F0 14
|
|
lda $2A ; CPU:$E420 PRG:2420 A5 2A
|
|
cmp #$01 ; CPU:$E422 PRG:2422 C9 01
|
|
beq Gameplay_ReadStageIndex_E434 ; CPU:$E424 PRG:2424 F0 0E
|
|
cmp #$0B ; CPU:$E426 PRG:2426 C9 0B
|
|
beq Gameplay_ReadStageIndex_E434 ; CPU:$E428 PRG:2428 F0 0A
|
|
lda #$00 ; CPU:$E42A PRG:242A A9 00
|
|
sta $A0 ; CPU:$E42C PRG:242C 85 A0
|
|
sta $A1 ; CPU:$E42E PRG:242E 85 A1
|
|
sta $A2 ; CPU:$E430 PRG:2430 85 A2
|
|
sta $A3 ; CPU:$E432 PRG:2432 85 A3
|
|
; Routine: Gameplay_ReadStageIndex_E434
|
|
; Global: Reachable code entry at CPU $E434 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadStageIndex_E434:
|
|
ldx $9D ; CPU:$E434 PRG:2434 A6 9D
|
|
beq Gameplay_ReadPlayerLives_E448 ; CPU:$E436 PRG:2436 F0 10
|
|
dex ; CPU:$E438 PRG:2438 CA
|
|
beq Gameplay_ReadStageProgress_E468 ; CPU:$E439 PRG:2439 F0 2D
|
|
dex ; CPU:$E43B PRG:243B CA
|
|
beq Gameplay_ReadStageProgress_E47D ; CPU:$E43C PRG:243C F0 3F
|
|
dex ; CPU:$E43E PRG:243E CA
|
|
beq Gameplay_ReadFlamePass_E486 ; CPU:$E43F PRG:243F F0 45
|
|
dex ; CPU:$E441 PRG:2441 CA
|
|
beq Gameplay_ReadBombCapacity_E48D ; CPU:$E442 PRG:2442 F0 49
|
|
dex ; CPU:$E444 PRG:2444 CA
|
|
beq Gameplay_ReadPlayerLives_E498 ; CPU:$E445 PRG:2445 F0 51
|
|
rts ; CPU:$E447 PRG:2447 60
|
|
; Routine: Gameplay_ReadPlayerLives_E448
|
|
; Global: Reachable code entry at CPU $E448 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadPlayerLives_E448:
|
|
lda $9E ; CPU:$E448 PRG:2448 A5 9E
|
|
bne Gameplay_ReturnToCaller_E467 ; CPU:$E44A PRG:244A D0 1B
|
|
lda $9F ; CPU:$E44C PRG:244C A5 9F
|
|
beq Gameplay_ReturnToCaller_E467 ; CPU:$E44E PRG:244E F0 17
|
|
; Routine: Gameplay_ReadPlayerState_E450
|
|
; Global: Reachable code entry at CPU $E450 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadPlayerState_E450:
|
|
lda $A8 ; CPU:$E450 PRG:2450 A5 A8
|
|
bne Gameplay_ReturnToCaller_E467 ; CPU:$E452 PRG:2452 D0 13
|
|
lda #$01 ; CPU:$E454 PRG:2454 A9 01
|
|
sta $A8 ; CPU:$E456 PRG:2456 85 A8
|
|
lda #$00 ; CPU:$E458 PRG:2458 A9 00
|
|
sta $A9 ; CPU:$E45A PRG:245A 85 A9
|
|
jsr Gameplay_WriteObjectWorkX_CACF ; CPU:$E45C PRG:245C 20 CF CA
|
|
lda $24 ; CPU:$E45F PRG:245F A5 24
|
|
sta $AA ; CPU:$E461 PRG:2461 85 AA
|
|
lda $25 ; CPU:$E463 PRG:2463 A5 25
|
|
sta $AB ; CPU:$E465 PRG:2465 85 AB
|
|
; Routine: Gameplay_ReturnToCaller_E467
|
|
; Global: Reachable code entry at CPU $E467 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReturnToCaller_E467:
|
|
rts ; CPU:$E467 PRG:2467 60
|
|
; Routine: Gameplay_ReadStageProgress_E468
|
|
; Global: Reachable code entry at CPU $E468 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadStageProgress_E468:
|
|
lda $9C ; CPU:$E468 PRG:2468 A5 9C
|
|
bne Gameplay_ReturnToCaller_E467 ; CPU:$E46A PRG:246A D0 FB
|
|
lda $A0 ; CPU:$E46C PRG:246C A5 A0
|
|
beq Gameplay_ReturnToCaller_E467 ; CPU:$E46E PRG:246E F0 F7
|
|
lda $A1 ; CPU:$E470 PRG:2470 A5 A1
|
|
beq Gameplay_ReturnToCaller_E467 ; CPU:$E472 PRG:2472 F0 F3
|
|
lda $A2 ; CPU:$E474 PRG:2474 A5 A2
|
|
beq Gameplay_ReturnToCaller_E467 ; CPU:$E476 PRG:2476 F0 EF
|
|
lda $A3 ; CPU:$E478 PRG:2478 A5 A3
|
|
bne Gameplay_ReadPlayerState_E450 ; CPU:$E47A PRG:247A D0 D4
|
|
rts ; CPU:$E47C PRG:247C 60
|
|
; Routine: Gameplay_ReadStageProgress_E47D
|
|
; Global: Reachable code entry at CPU $E47D traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadStageProgress_E47D:
|
|
lda $9C ; CPU:$E47D PRG:247D A5 9C
|
|
bne Gameplay_ReturnToCaller_E467 ; CPU:$E47F PRG:247F D0 E6
|
|
lda $A4 ; CPU:$E481 PRG:2481 A5 A4
|
|
beq Gameplay_ReadPlayerState_E450 ; CPU:$E483 PRG:2483 F0 CB
|
|
rts ; CPU:$E485 PRG:2485 60
|
|
; Routine: Gameplay_ReadFlamePass_E486
|
|
; Global: Reachable code entry at CPU $E486 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadFlamePass_E486:
|
|
lda $A5 ; CPU:$E486 PRG:2486 A5 A5
|
|
cmp #$F8 ; CPU:$E488 PRG:2488 C9 F8
|
|
bcs Gameplay_ReadPlayerState_E450 ; CPU:$E48A PRG:248A B0 C4
|
|
rts ; CPU:$E48C PRG:248C 60
|
|
; Routine: Gameplay_ReadBombCapacity_E48D
|
|
; Global: Reachable code entry at CPU $E48D traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadBombCapacity_E48D:
|
|
lda $9F ; CPU:$E48D PRG:248D A5 9F
|
|
beq Gameplay_ReturnToCaller_E467 ; CPU:$E48F PRG:248F F0 D6
|
|
lda $A6 ; CPU:$E491 PRG:2491 A5 A6
|
|
cmp #$F8 ; CPU:$E493 PRG:2493 C9 F8
|
|
bcs Gameplay_ReadPlayerState_E450 ; CPU:$E495 PRG:2495 B0 B9
|
|
rts ; CPU:$E497 PRG:2497 60
|
|
; Routine: Gameplay_ReadPlayerLives_E498
|
|
; Global: Reachable code entry at CPU $E498 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadPlayerLives_E498:
|
|
lda $9E ; CPU:$E498 PRG:2498 A5 9E
|
|
bne Gameplay_ReturnToCaller_E467 ; CPU:$E49A PRG:249A D0 CB
|
|
lda $58 ; CPU:$E49C PRG:249C A5 58
|
|
asl a ; CPU:$E49E PRG:249E 0A
|
|
clc ; CPU:$E49F PRG:249F 18
|
|
adc #$32 ; CPU:$E4A0 PRG:24A0 69 32
|
|
cmp $A4 ; CPU:$E4A2 PRG:24A2 C5 A4
|
|
beq Gameplay_ReadBonusTimer_E4A8 ; CPU:$E4A4 PRG:24A4 F0 02
|
|
bcs Gameplay_ReturnToCaller_E467 ; CPU:$E4A6 PRG:24A6 B0 BF
|
|
; Routine: Gameplay_ReadBonusTimer_E4A8
|
|
; Global: Reachable code entry at CPU $E4A8 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadBonusTimer_E4A8:
|
|
lda $A7 ; CPU:$E4A8 PRG:24A8 A5 A7
|
|
cmp #$03 ; CPU:$E4AA PRG:24AA C9 03
|
|
beq Gameplay_ReadPlayerState_E450 ; CPU:$E4AC PRG:24AC F0 A2
|
|
rts ; CPU:$E4AE PRG:24AE 60
|
|
; Routine: Gameplay_ReadZp58_E4AF
|
|
; Global: Reachable code entry at CPU $E4AF traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadZp58_E4AF:
|
|
lda $58 ; CPU:$E4AF PRG:24AF A5 58
|
|
and #$07 ; CPU:$E4B1 PRG:24B1 29 07
|
|
cmp #$06 ; CPU:$E4B3 PRG:24B3 C9 06
|
|
bcc Gameplay_WriteStageIndex_E4B9 ; CPU:$E4B5 PRG:24B5 90 02
|
|
and #$01 ; CPU:$E4B7 PRG:24B7 29 01
|
|
; Routine: Gameplay_WriteStageIndex_E4B9
|
|
; Global: Reachable code entry at CPU $E4B9 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteStageIndex_E4B9:
|
|
sta $9D ; CPU:$E4B9 PRG:24B9 85 9D
|
|
rts ; CPU:$E4BB PRG:24BB 60
|
|
|
|
; Data region: CPU $E4BC-$E4C1; unreachable by direct recursive trace.
|
|
GameplayPowerupMaskTable:
|
|
.byte $01, $02, $64, $32, $03, $C8 ; CPU:$E4BC PRG:24BC 01 02 64 32 03 C8
|
|
; Routine: Gameplay_WriteGameMode_E4C2
|
|
; Global: Reachable code entry at CPU $E4C2 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteGameMode_E4C2:
|
|
lda #$00 ; CPU:$E4C2 PRG:24C2 A9 00
|
|
sta $B5 ; CPU:$E4C4 PRG:24C4 85 B5
|
|
; Routine: Gameplay_ReturnToCaller_E4C6
|
|
; Global: Reachable code entry at CPU $E4C6 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReturnToCaller_E4C6:
|
|
rts ; CPU:$E4C6 PRG:24C6 60
|
|
; Routine: Gameplay_ReadZpB2_E4C7
|
|
; Global: Reachable code entry at CPU $E4C7 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadZpB2_E4C7:
|
|
lda $B2 ; CPU:$E4C7 PRG:24C7 A5 B2
|
|
bne Gameplay_ReturnToCaller_E4C6 ; CPU:$E4C9 PRG:24C9 D0 FB
|
|
lda $B5 ; CPU:$E4CB PRG:24CB A5 B5
|
|
beq Gameplay_ReturnToCaller_E4C6 ; CPU:$E4CD PRG:24CD F0 F7
|
|
bmi Gameplay_WriteSoundChannelIndex_E52A ; CPU:$E4CF PRG:24CF 30 59
|
|
cmp #$0B ; CPU:$E4D1 PRG:24D1 C9 0B
|
|
bcs Gameplay_WriteGameMode_E4C2 ; CPU:$E4D3 PRG:24D3 B0 ED
|
|
sta $B4 ; CPU:$E4D5 PRG:24D5 85 B4
|
|
ora #$80 ; CPU:$E4D7 PRG:24D7 09 80
|
|
sta $B5 ; CPU:$E4D9 PRG:24D9 85 B5
|
|
dec $B4 ; CPU:$E4DB PRG:24DB C6 B4
|
|
lda $B4 ; CPU:$E4DD PRG:24DD A5 B4
|
|
asl a ; CPU:$E4DF PRG:24DF 0A
|
|
asl a ; CPU:$E4E0 PRG:24E0 0A
|
|
asl a ; CPU:$E4E1 PRG:24E1 0A
|
|
tay ; CPU:$E4E2 PRG:24E2 A8
|
|
ldx #$00 ; CPU:$E4E3 PRG:24E3 A2 00
|
|
; Routine: Gameplay_ReadRamE87C_E4E5
|
|
; Global: Reachable code entry at CPU $E4E5 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadRamE87C_E4E5:
|
|
lda $E87C,y ; CPU:$E4E5 PRG:24E5 B9 7C E8
|
|
sta $BC,x ; CPU:$E4E8 PRG:24E8 95 BC
|
|
iny ; CPU:$E4EA PRG:24EA C8
|
|
inx ; CPU:$E4EB PRG:24EB E8
|
|
cpx #$06 ; CPU:$E4EC PRG:24EC E0 06
|
|
bne Gameplay_ReadRamE87C_E4E5 ; CPU:$E4EE PRG:24EE D0 F5
|
|
lda $E87C,y ; CPU:$E4F0 PRG:24F0 B9 7C E8
|
|
sta $D3 ; CPU:$E4F3 PRG:24F3 85 D3
|
|
lda $E87D,y ; CPU:$E4F5 PRG:24F5 B9 7D E8
|
|
sta $D4 ; CPU:$E4F8 PRG:24F8 85 D4
|
|
lda #$00 ; CPU:$E4FA PRG:24FA A9 00
|
|
sta $C4 ; CPU:$E4FC PRG:24FC 85 C4
|
|
sta $C5 ; CPU:$E4FE PRG:24FE 85 C5
|
|
sta $C6 ; CPU:$E500 PRG:2500 85 C6
|
|
sta $D5 ; CPU:$E502 PRG:2502 85 D5
|
|
sta $CD ; CPU:$E504 PRG:2504 85 CD
|
|
sta $CE ; CPU:$E506 PRG:2506 85 CE
|
|
sta $CF ; CPU:$E508 PRG:2508 85 CF
|
|
sta $D0 ; CPU:$E50A PRG:250A 85 D0
|
|
sta $D1 ; CPU:$E50C PRG:250C 85 D1
|
|
sta $D2 ; CPU:$E50E PRG:250E 85 D2
|
|
lda #$01 ; CPU:$E510 PRG:2510 A9 01
|
|
sta $B6 ; CPU:$E512 PRG:2512 85 B6
|
|
sta $B7 ; CPU:$E514 PRG:2514 85 B7
|
|
sta $B8 ; CPU:$E516 PRG:2516 85 B8
|
|
sta $B9 ; CPU:$E518 PRG:2518 85 B9
|
|
sta $BA ; CPU:$E51A PRG:251A 85 BA
|
|
sta $BB ; CPU:$E51C PRG:251C 85 BB
|
|
sta $D6 ; CPU:$E51E PRG:251E 85 D6
|
|
sta $D7 ; CPU:$E520 PRG:2520 85 D7
|
|
sta $D8 ; CPU:$E522 PRG:2522 85 D8
|
|
lda #$08 ; CPU:$E524 PRG:2524 A9 08
|
|
sta $D9 ; CPU:$E526 PRG:2526 85 D9
|
|
sta $DA ; CPU:$E528 PRG:2528 85 DA
|
|
; Routine: Gameplay_WriteSoundChannelIndex_E52A
|
|
; Global: Reachable code entry at CPU $E52A traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteSoundChannelIndex_E52A:
|
|
lda #$02 ; CPU:$E52A PRG:252A A9 02
|
|
sta $B3 ; CPU:$E52C PRG:252C 85 B3
|
|
; Routine: Gameplay_ReadSoundChannelIndex_E52E
|
|
; Global: Reachable code entry at CPU $E52E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadSoundChannelIndex_E52E:
|
|
ldx $B3 ; CPU:$E52E PRG:252E A6 B3
|
|
dec $B6,x ; CPU:$E530 PRG:2530 D6 B6
|
|
beq Gameplay_ReadZpBC_E539 ; CPU:$E532 PRG:2532 F0 05
|
|
; Routine: Gameplay_DecrementSoundChannelIndex_E534
|
|
; Global: Reachable code entry at CPU $E534 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_DecrementSoundChannelIndex_E534:
|
|
dec $B3 ; CPU:$E534 PRG:2534 C6 B3
|
|
bpl Gameplay_ReadSoundChannelIndex_E52E ; CPU:$E536 PRG:2536 10 F6
|
|
rts ; CPU:$E538 PRG:2538 60
|
|
; Routine: Gameplay_ReadZpBC_E539
|
|
; Global: Reachable code entry at CPU $E539 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadZpBC_E539:
|
|
txa ; CPU:$E539 PRG:2539 8A
|
|
asl a ; CPU:$E53A PRG:253A 0A
|
|
tax ; CPU:$E53B PRG:253B AA
|
|
lda $BC,x ; CPU:$E53C PRG:253C B5 BC
|
|
sta $C2 ; CPU:$E53E PRG:253E 85 C2
|
|
lda $BD,x ; CPU:$E540 PRG:2540 B5 BD
|
|
sta $C3 ; CPU:$E542 PRG:2542 85 C3
|
|
ora $C2 ; CPU:$E544 PRG:2544 05 C2
|
|
beq Gameplay_DecrementSoundChannelIndex_E534 ; CPU:$E546 PRG:2546 F0 EC
|
|
jsr Gameplay_ReadSoundChannelIndex_E54E ; CPU:$E548 PRG:2548 20 4E E5
|
|
jmp Gameplay_DecrementSoundChannelIndex_E534 ; CPU:$E54B PRG:254B 4C 34 E5
|
|
; Routine: Gameplay_ReadSoundChannelIndex_E54E
|
|
; Global: Reachable code entry at CPU $E54E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadSoundChannelIndex_E54E:
|
|
ldx $B3 ; CPU:$E54E PRG:254E A6 B3
|
|
ldy $C4,x ; CPU:$E550 PRG:2550 B4 C4
|
|
lda ($C2),y ; CPU:$E552 PRG:2552 B1 C2
|
|
sta $B4 ; CPU:$E554 PRG:2554 85 B4
|
|
inc $C4,x ; CPU:$E556 PRG:2556 F6 C4
|
|
lda $B4 ; CPU:$E558 PRG:2558 A5 B4
|
|
bmi Gameplay_ReadSoundTempo_E5C7 ; CPU:$E55A PRG:255A 30 6B
|
|
lda $B9,x ; CPU:$E55C PRG:255C B5 B9
|
|
sta $B6,x ; CPU:$E55E PRG:255E 95 B6
|
|
cpx #$02 ; CPU:$E560 PRG:2560 E0 02
|
|
beq Gameplay_HandleControl_E56E ; CPU:$E562 PRG:2562 F0 0A
|
|
lsr a ; CPU:$E564 PRG:2564 4A
|
|
lsr a ; CPU:$E565 PRG:2565 4A
|
|
cmp #$10 ; CPU:$E566 PRG:2566 C9 10
|
|
bcc Gameplay_WriteZpD6_E573 ; CPU:$E568 PRG:2568 90 09
|
|
lda #$0F ; CPU:$E56A PRG:256A A9 0F
|
|
bne Gameplay_WriteZpD6_E573 ; CPU:$E56C PRG:256C D0 05
|
|
; Routine: Gameplay_HandleControl_E56E
|
|
; Global: Reachable code entry at CPU $E56E traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_HandleControl_E56E:
|
|
asl a ; CPU:$E56E PRG:256E 0A
|
|
bpl Gameplay_WriteZpD6_E573 ; CPU:$E56F PRG:256F 10 02
|
|
lda #$7F ; CPU:$E571 PRG:2571 A9 7F
|
|
; Routine: Gameplay_WriteZpD6_E573
|
|
; Global: Reachable code entry at CPU $E573 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_WriteZpD6_E573:
|
|
sta $D6,x ; CPU:$E573 PRG:2573 95 D6
|
|
lda $D0,x ; CPU:$E575 PRG:2575 B5 D0
|
|
beq Gameplay_ReadSoundDelay0_E57B ; CPU:$E577 PRG:2577 F0 02
|
|
lsr $D6,x ; CPU:$E579 PRG:2579 56 D6
|
|
; Routine: Gameplay_ReadSoundDelay0_E57B
|
|
; Global: Reachable code entry at CPU $E57B traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadSoundDelay0_E57B:
|
|
ldy $E1,x ; CPU:$E57B PRG:257B B4 E1
|
|
bne Gameplay_ReturnToCaller_E5C6 ; CPU:$E57D PRG:257D D0 47
|
|
lda $B4 ; CPU:$E57F PRG:257F A5 B4
|
|
cmp #$00 ; CPU:$E581 PRG:2581 C9 00
|
|
beq Gameplay_ReturnToCaller_E5C6 ; CPU:$E583 PRG:2583 F0 41
|
|
txa ; CPU:$E585 PRG:2585 8A
|
|
asl a ; CPU:$E586 PRG:2586 0A
|
|
asl a ; CPU:$E587 PRG:2587 0A
|
|
tay ; CPU:$E588 PRG:2588 A8
|
|
lda $CD,x ; CPU:$E589 PRG:2589 B5 CD
|
|
beq Gameplay_ReadZpD6_E59D ; CPU:$E58B PRG:258B F0 10
|
|
bpl Gameplay_HandleControl_E593 ; CPU:$E58D PRG:258D 10 04
|
|
inc $CD,x ; CPU:$E58F PRG:258F F6 CD
|
|
beq Gameplay_ReadZpD6_E59D ; CPU:$E591 PRG:2591 F0 0A
|
|
; Routine: Gameplay_HandleControl_E593
|
|
; Global: Reachable code entry at CPU $E593 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_HandleControl_E593:
|
|
lda #$9F ; CPU:$E593 PRG:2593 A9 9F
|
|
cpx #$02 ; CPU:$E595 PRG:2595 E0 02
|
|
bne Gameplay_UpdateAudioChannelPath_E5A1 ; CPU:$E597 PRG:2597 D0 08
|
|
lda #$7F ; CPU:$E599 PRG:2599 A9 7F
|
|
bne Gameplay_UpdateAudioChannelPath_E5A1 ; CPU:$E59B PRG:259B D0 04
|
|
; Routine: Gameplay_ReadZpD6_E59D
|
|
; Global: Reachable code entry at CPU $E59D traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadZpD6_E59D:
|
|
lda $D6,x ; CPU:$E59D PRG:259D B5 D6
|
|
ora $D3,x ; CPU:$E59F PRG:259F 15 D3
|
|
; Routine: Gameplay_UpdateAudioChannelPath_E5A1
|
|
; Global: Reachable code entry at CPU $E5A1 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_UpdateAudioChannelPath_E5A1:
|
|
sta APUPULSE1CTRL,y ; CPU:$E5A1 PRG:25A1 99 00 40
|
|
lda $CD,x ; CPU:$E5A4 PRG:25A4 B5 CD
|
|
cmp #$02 ; CPU:$E5A6 PRG:25A6 C9 02
|
|
bne Gameplay_UpdateAudioChannelPath_E5AB ; CPU:$E5A8 PRG:25A8 D0 01
|
|
rts ; CPU:$E5AA PRG:25AA 60
|
|
; Routine: Gameplay_UpdateAudioChannelPath_E5AB
|
|
; Global: Reachable code entry at CPU $E5AB traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_UpdateAudioChannelPath_E5AB:
|
|
cpx #$02 ; CPU:$E5AB PRG:25AB E0 02
|
|
bcs Gameplay_UpdateAudioChannelPath_E5B4 ; CPU:$E5AD PRG:25AD B0 05
|
|
lda $D9,x ; CPU:$E5AF PRG:25AF B5 D9
|
|
sta APUPULSE1SWEEP,y ; CPU:$E5B1 PRG:25B1 99 01 40
|
|
; Routine: Gameplay_UpdateAudioChannelPath_E5B4
|
|
; Global: Reachable code entry at CPU $E5B4 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_UpdateAudioChannelPath_E5B4:
|
|
lda $B4 ; CPU:$E5B4 PRG:25B4 A5 B4
|
|
asl a ; CPU:$E5B6 PRG:25B6 0A
|
|
tax ; CPU:$E5B7 PRG:25B7 AA
|
|
lda $E7E2,x ; CPU:$E5B8 PRG:25B8 BD E2 E7
|
|
sta APUPULSE1TIMERLO,y ; CPU:$E5BB PRG:25BB 99 02 40
|
|
lda $E7E3,x ; CPU:$E5BE PRG:25BE BD E3 E7
|
|
ora #$08 ; CPU:$E5C1 PRG:25C1 09 08
|
|
sta APUPULSE1TIMERHI,y ; CPU:$E5C3 PRG:25C3 99 03 40
|
|
; Routine: Gameplay_ReturnToCaller_E5C6
|
|
; Global: Reachable code entry at CPU $E5C6 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReturnToCaller_E5C6:
|
|
rts ; CPU:$E5C6 PRG:25C6 60
|
|
; Routine: Gameplay_ReadSoundTempo_E5C7
|
|
; Global: Reachable code entry at CPU $E5C7 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_ReadSoundTempo_E5C7:
|
|
and #$F0 ; CPU:$E5C7 PRG:25C7 29 F0
|
|
cmp #$F0 ; CPU:$E5C9 PRG:25C9 C9 F0
|
|
beq Gameplay_SubtractFromSoundTempo_E5D6 ; CPU:$E5CB PRG:25CB F0 09
|
|
lda $B4 ; CPU:$E5CD PRG:25CD A5 B4
|
|
and #$7F ; CPU:$E5CF PRG:25CF 29 7F
|
|
sta $B9,x ; CPU:$E5D1 PRG:25D1 95 B9
|
|
jmp Gameplay_ReadSoundChannelIndex_E54E ; CPU:$E5D3 PRG:25D3 4C 4E E5
|
|
; Routine: Gameplay_SubtractFromSoundTempo_E5D6
|
|
; Global: Reachable code entry at CPU $E5D6 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Gameplay_SubtractFromSoundTempo_E5D6:
|
|
sec ; CPU:$E5D6 PRG:25D6 38
|
|
lda #$FF ; CPU:$E5D7 PRG:25D7 A9 FF
|
|
sbc $B4 ; CPU:$E5D9 PRG:25D9 E5 B4
|
|
asl a ; CPU:$E5DB PRG:25DB 0A
|
|
tay ; CPU:$E5DC PRG:25DC A8
|
|
lda $E5E7,y ; CPU:$E5DD PRG:25DD B9 E7 E5
|
|
pha ; CPU:$E5E0 PRG:25E0 48
|
|
lda $E5E6,y ; CPU:$E5E1 PRG:25E1 B9 E6 E5
|
|
pha ; CPU:$E5E4 PRG:25E4 48
|
|
rts ; CPU:$E5E5 PRG:25E5 60
|
|
|
|
; Data region: CPU $E5E6-$E641; unreachable by direct recursive trace.
|
|
GameplayAndSoundDataTables:
|
|
.byte $F5, $E5, $FA, $E5, $01, $E6, $0F, $E6, $1A, $E6, $2C, $E6, $33, $E6, $3A, $E6 ; CPU:$E5E6 PRG:25E6 F5 E5 FA E5 01 E6 0F E6 1A E6 2C E6 33 E6 3A E6
|
|
.byte $A9, $00, $85, $B5, $60, $A9, $00, $95, $C4, $4C, $4E, $E5, $B4, $C4, $B1, $C2 ; CPU:$E5F6 PRG:25F6 A9 00 85 B5 60 A9 00 95 C4 4C 4E E5 B4 C4 B1 C2
|
|
.byte $95, $CA, $C8, $94, $C4, $94, $C7, $4C, $4E, $E5, $D6, $CA, $F0, $04, $B5, $C7 ; CPU:$E606 PRG:2606 95 CA C8 94 C4 94 C7 4C 4E E5 D6 CA F0 04 B5 C7
|
|
.byte $95, $C4, $4C, $4E, $E5, $B5, $CD, $F0, $07, $A9, $02, $95, $CD, $4C, $4E, $E5 ; CPU:$E616 PRG:2616 95 C4 4C 4E E5 B5 CD F0 07 A9 02 95 CD 4C 4E E5
|
|
.byte $A9, $01, $95, $CD, $4C, $4E, $E5, $A9, $FF, $95, $CD, $4C, $4E, $E5, $A9, $FF ; CPU:$E626 PRG:2626 A9 01 95 CD 4C 4E E5 A9 FF 95 CD 4C 4E E5 A9 FF
|
|
.byte $95, $D0, $4C, $4E, $E5, $A9, $00, $95, $D0, $4C, $4E, $E5 ; CPU:$E636 PRG:2636 95 D0 4C 4E E5 A9 00 95 D0 4C 4E E5
|
|
; Routine: InitializeApu
|
|
; Global: Reachable code entry at CPU $E642 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
InitializeApu:
|
|
lda #$00 ; CPU:$E642 PRG:2642 A9 00
|
|
sta APUDMCDIRECT ; CPU:$E644 PRG:2644 8D 11 40
|
|
sta $E1 ; CPU:$E647 PRG:2647 85 E1
|
|
sta $E2 ; CPU:$E649 PRG:2649 85 E2
|
|
sta $E3 ; CPU:$E64B PRG:264B 85 E3
|
|
sta APUPULSE1CTRL ; CPU:$E64D PRG:264D 8D 00 40
|
|
sta APUPULSE2CTRL ; CPU:$E650 PRG:2650 8D 04 40
|
|
sta APUTRIANGLECTRL ; CPU:$E653 PRG:2653 8D 08 40
|
|
sta APUNOISECTRL ; CPU:$E656 PRG:2656 8D 0C 40
|
|
lda #$0F ; CPU:$E659 PRG:2659 A9 0F
|
|
sta APUSTATUS ; CPU:$E65B PRG:265B 8D 15 40
|
|
rts ; CPU:$E65E PRG:265E 60
|
|
; Routine: SoundUpdate
|
|
; Global: Reachable code entry at CPU $E65F traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
SoundUpdate:
|
|
ldx #$02 ; CPU:$E65F PRG:265F A2 02
|
|
; Routine: Sound_ReadSoundDelay0_E661
|
|
; Global: Reachable code entry at CPU $E661 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Sound_ReadSoundDelay0_E661:
|
|
lda $E1,x ; CPU:$E661 PRG:2661 B5 E1
|
|
beq Sound_ReadSoundCommandState_E667 ; CPU:$E663 PRG:2663 F0 02
|
|
dec $E1,x ; CPU:$E665 PRG:2665 D6 E1
|
|
; Routine: Sound_ReadSoundCommandState_E667
|
|
; Global: Reachable code entry at CPU $E667 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Sound_ReadSoundCommandState_E667:
|
|
dex ; CPU:$E667 PRG:2667 CA
|
|
bpl Sound_ReadSoundDelay0_E661 ; CPU:$E668 PRG:2668 10 F7
|
|
lda $DF ; CPU:$E66A PRG:266A A5 DF
|
|
bmi Sound_ReadRamE6BC_E69C ; CPU:$E66C PRG:266C 30 2E
|
|
cmp #$07 ; CPU:$E66E PRG:266E C9 07
|
|
bcs Sound_ReturnToCaller_E6AC ; CPU:$E670 PRG:2670 B0 3A
|
|
cmp #$03 ; CPU:$E672 PRG:2672 C9 03
|
|
bcs Sound_WriteSoundCommandState_E681 ; CPU:$E674 PRG:2674 B0 0B
|
|
ldx IndirectPtrLo ; CPU:$E676 PRG:2676 A6 E0
|
|
beq Sound_WriteSoundCommandState_E681 ; CPU:$E678 PRG:2678 F0 07
|
|
txa ; CPU:$E67A PRG:267A 8A
|
|
ora #$80 ; CPU:$E67B PRG:267B 09 80
|
|
sta $DF ; CPU:$E67D PRG:267D 85 DF
|
|
bne Sound_ReadRamE6BC_E69C ; CPU:$E67F PRG:267F D0 1B
|
|
; Routine: Sound_WriteSoundCommandState_E681
|
|
; Global: Reachable code entry at CPU $E681 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Sound_WriteSoundCommandState_E681:
|
|
sta IndirectPtrLo ; CPU:$E681 PRG:2681 85 E0
|
|
ora #$80 ; CPU:$E683 PRG:2683 09 80
|
|
sta $DF ; CPU:$E685 PRG:2685 85 DF
|
|
lda #$00 ; CPU:$E687 PRG:2687 A9 00
|
|
sta IndirectPtrHi ; CPU:$E689 PRG:2689 85 E1
|
|
sta $E2 ; CPU:$E68B PRG:268B 85 E2
|
|
sta $E3 ; CPU:$E68D PRG:268D 85 E3
|
|
lda IndirectPtrLo ; CPU:$E68F PRG:268F A5 E0
|
|
asl a ; CPU:$E691 PRG:2691 0A
|
|
tax ; CPU:$E692 PRG:2692 AA
|
|
lda $E6AE,x ; CPU:$E693 PRG:2693 BD AE E6
|
|
pha ; CPU:$E696 PRG:2696 48
|
|
lda $E6AD,x ; CPU:$E697 PRG:2697 BD AD E6
|
|
pha ; CPU:$E69A PRG:269A 48
|
|
rts ; CPU:$E69B PRG:269B 60
|
|
; Routine: Sound_ReadRamE6BC_E69C
|
|
; Global: Reachable code entry at CPU $E69C traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Sound_ReadRamE6BC_E69C:
|
|
lda IndirectPtrLo ; CPU:$E69C PRG:269C A5 E0
|
|
cmp #$07 ; CPU:$E69E PRG:269E C9 07
|
|
bcs Sound_ReturnToCaller_E6AC ; CPU:$E6A0 PRG:26A0 B0 0A
|
|
asl a ; CPU:$E6A2 PRG:26A2 0A
|
|
tax ; CPU:$E6A3 PRG:26A3 AA
|
|
lda $E6BC,x ; CPU:$E6A4 PRG:26A4 BD BC E6
|
|
pha ; CPU:$E6A7 PRG:26A7 48
|
|
lda $E6BB,x ; CPU:$E6A8 PRG:26A8 BD BB E6
|
|
pha ; CPU:$E6AB PRG:26AB 48
|
|
; Routine: Sound_ReturnToCaller_E6AC
|
|
; Global: Reachable code entry at CPU $E6AC traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Sound_ReturnToCaller_E6AC:
|
|
rts ; CPU:$E6AC PRG:26AC 60
|
|
|
|
; Data region: CPU $E6AD-$E6C8; unreachable by direct recursive trace.
|
|
SoundDispatchAddressTable:
|
|
.byte $41, $E6, $C8, $E6, $CC, $E6, $DE, $E6, $27, $E7, $66, $E7, $92, $E7, $AB, $E6 ; CPU:$E6AD PRG:26AD 41 E6 C8 E6 CC E6 DE E6 27 E7 66 E7 92 E7 AB E6
|
|
.byte $AB, $E6, $AB, $E6, $0A, $E7, $33, $E7, $AB, $E6, $9E, $E7 ; CPU:$E6BD PRG:26BD AB E6 AB E6 0A E7 33 E7 AB E6 9E E7
|
|
; Routine: ConfigureNoiseEffect
|
|
; Global: Reachable code entry at CPU $E6C9 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
ConfigureNoiseEffect:
|
|
lda #$04 ; CPU:$E6C9 PRG:26C9 ??
|
|
bne Sound_UpdateAudioChannelPath_E6CF ; CPU:$E6CB PRG:26CB ??
|
|
; Routine: Sound_HandleControl_E6CD
|
|
; Global: Reachable code entry at CPU $E6CD traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Sound_HandleControl_E6CD:
|
|
lda #$0C ; CPU:$E6CD PRG:26CD ??
|
|
; Routine: Sound_UpdateAudioChannelPath_E6CF
|
|
; Global: Reachable code entry at CPU $E6CF traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Sound_UpdateAudioChannelPath_E6CF:
|
|
sta APUNOISEPERIOD ; CPU:$E6CF PRG:26CF ??
|
|
lda #$00 ; CPU:$E6D1 PRG:26D1 ??
|
|
sta IndirectPtrLo ; CPU:$E6D3 PRG:26D3 ??
|
|
sta APUNOISECTRL ; CPU:$E6D5 PRG:26D5 ??
|
|
lda #$10 ; CPU:$E6D7 PRG:26D7 ??
|
|
sta APUNOISELENGTH ; CPU:$E6D9 PRG:26D9 ??
|
|
rts ; CPU:$E6DB PRG:26DB ??
|
|
; Routine: Sound_UpdateAudioChannelPath_E6DF
|
|
; Global: Reachable code entry at CPU $E6DF traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Sound_UpdateAudioChannelPath_E6DF:
|
|
lda #$10 ; CPU:$E6DD PRG:26DD ??
|
|
sta $E2 ; CPU:$E6DF PRG:26DF ??
|
|
lda #$01 ; CPU:$E6E1 PRG:26E1 ??
|
|
sta APUNOISECTRL ; CPU:$E6E3 PRG:26E3 ??
|
|
lda #$0F ; CPU:$E6E5 PRG:26E5 ??
|
|
sta APUNOISEPERIOD ; CPU:$E6E7 PRG:26E7 ??
|
|
lda #$10 ; CPU:$E6E9 PRG:26E9 ??
|
|
sta APUNOISELENGTH ; CPU:$E6EB PRG:26EB ??
|
|
lda #$FF ; CPU:$E6ED PRG:26ED ??
|
|
sta APUPULSE2CTRL ; CPU:$E6EF PRG:26EF ??
|
|
lda #$84 ; CPU:$E6F1 PRG:26F1 ??
|
|
sta APUPULSE2SWEEP ; CPU:$E6F3 PRG:26F3 ??
|
|
lda #$00 ; CPU:$E6F5 PRG:26F5 ??
|
|
sta APUPULSE2TIMERLO ; CPU:$E6F7 PRG:26F7 ??
|
|
lda #$02 ; CPU:$E6F9 PRG:26F9 ??
|
|
sta APUPULSE2TIMERHI ; CPU:$E6FB PRG:26FB ??
|
|
lda #$04 ; CPU:$E6FD PRG:26FD ??
|
|
sta $E4 ; CPU:$E6FF PRG:26FF ??
|
|
rts ; CPU:$E701 PRG:2701 ??
|
|
; Routine: Sound_UpdateAudioChannelPath_E70B
|
|
; Global: Reachable code entry at CPU $E70B traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Sound_UpdateAudioChannelPath_E70B:
|
|
dec RandomStateAlt ; CPU:$E703 PRG:2703 ??
|
|
bne Sound_ReturnToCaller_E727 ; CPU:$E705 PRG:2705 ??
|
|
lda #$DF ; CPU:$E707 PRG:2707 ??
|
|
sta APUPULSE2CTRL ; CPU:$E709 PRG:2709 ??
|
|
lda #$84 ; CPU:$E70B PRG:270B ??
|
|
sta APUPULSE2SWEEP ; CPU:$E70D PRG:270D ??
|
|
lda #$00 ; CPU:$E70F PRG:270F ??
|
|
sta APUPULSE2TIMERLO ; CPU:$E711 PRG:2711 ??
|
|
lda #$81 ; CPU:$E713 PRG:2713 ??
|
|
sta APUPULSE2TIMERHI ; CPU:$E715 PRG:2715 ??
|
|
lda #$00 ; CPU:$E717 PRG:2717 ??
|
|
sta IndirectPtrLo ; CPU:$E719 PRG:2719 ??
|
|
; Routine: Sound_ReturnToCaller_E727
|
|
; Global: Reachable code entry at CPU $E727 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Sound_ReturnToCaller_E727:
|
|
rts ; CPU:$E71B PRG:271B ??
|
|
; Routine: Sound_WriteSoundDelay1_E728
|
|
; Global: Reachable code entry at CPU $E728 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Sound_WriteSoundDelay1_E728:
|
|
lda #$FF ; CPU:$E71D PRG:271D ??
|
|
sta $E2 ; CPU:$E71F PRG:271F ??
|
|
lda #$00 ; CPU:$E721 PRG:2721 ??
|
|
sta $E4 ; CPU:$E723 PRG:2723 ??
|
|
lda #$04 ; CPU:$E725 PRG:2725 ??
|
|
sta $E5 ; CPU:$E727 PRG:2727 ??
|
|
; Routine: Sound_ReadSoundEnvelopeCounter_E734
|
|
; Global: Reachable code entry at CPU $E734 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Sound_ReadSoundEnvelopeCounter_E734:
|
|
lda $E4 ; CPU:$E729 PRG:2729 ??
|
|
bne Sound_DecrementSoundEnvelopeCounter_E760 ; CPU:$E72B PRG:272B ??
|
|
lda $E5 ; CPU:$E72D PRG:272D ??
|
|
bne Sound_UpdateAudioChannelPath_E743 ; CPU:$E72F PRG:272F ??
|
|
lda #$00 ; CPU:$E731 PRG:2731 ??
|
|
sta IndirectPtrLo ; CPU:$E733 PRG:2733 ??
|
|
sta $E2 ; CPU:$E735 PRG:2735 ??
|
|
rts ; CPU:$E737 PRG:2737 ??
|
|
; Routine: Sound_UpdateAudioChannelPath_E743
|
|
; Global: Reachable code entry at CPU $E743 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Sound_UpdateAudioChannelPath_E743:
|
|
dec $E5 ; CPU:$E739 PRG:2739 ??
|
|
lda #$84 ; CPU:$E73B PRG:273B ??
|
|
sta APUPULSE2CTRL ; CPU:$E73D PRG:273D ??
|
|
lda #$8B ; CPU:$E73F PRG:273F ??
|
|
sta APUPULSE2SWEEP ; CPU:$E741 PRG:2741 ??
|
|
ldx $E5 ; CPU:$E743 PRG:2743 ??
|
|
lda SoundHandlerData,x ; CPU:$E745 PRG:2745 ??
|
|
sta APUPULSE2TIMERLO ; CPU:$E747 PRG:2747 ??
|
|
lda #$10 ; CPU:$E749 PRG:2749 ??
|
|
sta APUPULSE2TIMERHI ; CPU:$E74B PRG:274B ??
|
|
lda #$04 ; CPU:$E74D PRG:274D ??
|
|
sta $E4 ; CPU:$E74F PRG:274F ??
|
|
; Routine: Sound_DecrementSoundEnvelopeCounter_E760
|
|
; Global: Reachable code entry at CPU $E760 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Sound_DecrementSoundEnvelopeCounter_E760:
|
|
dec $E4 ; CPU:$E751 PRG:2751 ??
|
|
rts ; CPU:$E753 PRG:2753 ??
|
|
|
|
; Data region: CPU $E763-$E766; unreachable by direct recursive trace.
|
|
SoundHandlerData:
|
|
.byte $65, $87, $B4, $F0 ; CPU:$E755 PRG:2755 65 87 B4 F0
|
|
; Routine: Sound_UpdateAudioChannelPath_E767
|
|
; Global: Reachable code entry at CPU $E767 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Sound_UpdateAudioChannelPath_E767:
|
|
lda #$30 ; CPU:$E759 PRG:2759 ??
|
|
sta $E2 ; CPU:$E75B PRG:275B ??
|
|
lda #$09 ; CPU:$E75D PRG:275D ??
|
|
sta APUNOISECTRL ; CPU:$E75F PRG:275F ??
|
|
lda #$07 ; CPU:$E761 PRG:2761 ??
|
|
sta APUNOISEPERIOD ; CPU:$E763 PRG:2763 ??
|
|
lda #$30 ; CPU:$E765 PRG:2765 ??
|
|
sta APUNOISELENGTH ; CPU:$E767 PRG:2767 ??
|
|
lda #$1F ; CPU:$E769 PRG:2769 ??
|
|
sta APUPULSE2CTRL ; CPU:$E76B PRG:276B ??
|
|
lda #$8F ; CPU:$E76D PRG:276D ??
|
|
sta APUPULSE2SWEEP ; CPU:$E76F PRG:276F ??
|
|
lda #$00 ; CPU:$E771 PRG:2771 ??
|
|
sta APUPULSE2TIMERLO ; CPU:$E773 PRG:2773 ??
|
|
lda #$33 ; CPU:$E775 PRG:2775 ??
|
|
sta APUPULSE2TIMERHI ; CPU:$E777 PRG:2777 ??
|
|
lda #$00 ; CPU:$E779 PRG:2779 ??
|
|
sta IndirectPtrLo ; CPU:$E77B PRG:277B ??
|
|
rts ; CPU:$E77D PRG:277D ??
|
|
; Routine: Sound_WriteSoundEnvelopeCounter_E793
|
|
; Global: Reachable code entry at CPU $E793 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Sound_WriteSoundEnvelopeCounter_E793:
|
|
lda #$1D ; CPU:$E77F PRG:277F ??
|
|
sta $E4 ; CPU:$E781 PRG:2781 ??
|
|
lda #$FF ; CPU:$E783 PRG:2783 ??
|
|
sta IndirectPtrHi ; CPU:$E785 PRG:2785 ??
|
|
sta $E2 ; CPU:$E787 PRG:2787 ??
|
|
sta $E3 ; CPU:$E789 PRG:2789 ??
|
|
; Routine: Sound_UpdateAudioChannelPath_E79F
|
|
; Global: Reachable code entry at CPU $E79F traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Sound_UpdateAudioChannelPath_E79F:
|
|
dec $E4 ; CPU:$E78B PRG:278B ??
|
|
beq Sound_HandleControl_E7D1 ; CPU:$E78D PRG:278D ??
|
|
lda $E4 ; CPU:$E78F PRG:278F ??
|
|
and #$03 ; CPU:$E791 PRG:2791 ??
|
|
bne Sound_ReturnToCaller_E7D0 ; CPU:$E793 PRG:2793 ??
|
|
lda $E4 ; CPU:$E795 PRG:2795 ??
|
|
lsr a ; CPU:$E797 PRG:2797 ??
|
|
lsr a ; CPU:$E799 PRG:2799 ??
|
|
and #$01 ; CPU:$E79B PRG:279B ??
|
|
tax ; CPU:$E79D PRG:279D ??
|
|
lda $E7DE,x ; CPU:$E79F PRG:279F ??
|
|
sta APUPULSE1TIMERLO ; CPU:$E7A1 PRG:27A1 ??
|
|
lda $E7E0,x ; CPU:$E7A3 PRG:27A3 ??
|
|
sta APUPULSE2TIMERLO ; CPU:$E7A5 PRG:27A5 ??
|
|
lda #$08 ; CPU:$E7A7 PRG:27A7 ??
|
|
sta APUPULSE1CTRL ; CPU:$E7A9 PRG:27A9 ??
|
|
sta APUPULSE2CTRL ; CPU:$E7AB PRG:27AB ??
|
|
sta APUPULSE1SWEEP ; CPU:$E7AD PRG:27AD ??
|
|
sta APUPULSE2SWEEP ; CPU:$E7AF PRG:27AF ??
|
|
sta APUPULSE1TIMERHI ; CPU:$E7B1 PRG:27B1 ??
|
|
sta APUPULSE2TIMERHI ; CPU:$E7B3 PRG:27B3 ??
|
|
; Routine: Sound_ReturnToCaller_E7D0
|
|
; Global: Reachable code entry at CPU $E7D0 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Sound_ReturnToCaller_E7D0:
|
|
rts ; CPU:$E7B5 PRG:27B5 ??
|
|
; Routine: Sound_HandleControl_E7D1
|
|
; Global: Reachable code entry at CPU $E7D1 traced from the interrupt-root control-flow graph.
|
|
; Local: Performs the instruction sequence below; semantic purpose remains provisional.
|
|
; Parameters: Register and memory inputs are caller-dependent.
|
|
; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
|
|
; Side effects: Registers, flags, memory, and hardware registers written below.
|
|
; Confidence: High for reachability and encoding; semantic role provisional.
|
|
Sound_HandleControl_E7D1:
|
|
lda #$20 ; CPU:$E7B7 PRG:27B7 ??
|
|
sta SoundDelay0 ; CPU:$E7B9 PRG:27B9 ??
|
|
sta SoundDelay1 ; CPU:$E7BB PRG:27BB ??
|
|
sta SoundDelay2 ; CPU:$E7BD PRG:27BD ??
|
|
lda #$00 ; CPU:$E7BF PRG:27BF ??
|
|
sta SoundDispatchIndex ; CPU:$E7C1 PRG:27C1 ??
|
|
rts ; CPU:$E7C3 PRG:27C3 ??
|
|
|
|
; Data region: CPU $E7DE-$FFF8; unreachable by direct recursive trace.
|
|
SoundSequenceAndPaddingData:
|
|
.byte $A9, $A0, $6A, $64, $00, $00, $F0, $07, $7E, $07, $12, $07, $AE, $06, $4E, $06 ; CPU:$E7C5 PRG:27C5 A9 A0 6A 64 00 00 F0 07 7E 07 12 07 AE 06 4E 06
|
|
.byte $F3, $05, $9F, $05, $4D, $05, $01, $05, $B9, $04, $75, $04, $35, $04, $F8, $03 ; CPU:$E7D5 PRG:27D5 F3 05 9F 05 4D 05 01 05 B9 04 75 04 35 04 F8 03
|
|
.byte $BF, $03, $89, $03, $57, $03, $27, $03, $F9, $02, $CF, $02, $A6, $02, $80, $02 ; CPU:$E7E5 PRG:27E5 BF 03 89 03 57 03 27 03 F9 02 CF 02 A6 02 80 02
|
|
.byte $5C, $02, $3A, $02, $1A, $02, $FC, $01, $DF, $01, $C4, $01, $AB, $01, $93, $01 ; CPU:$E7F5 PRG:27F5 5C 02 3A 02 1A 02 FC 01 DF 01 C4 01 AB 01 93 01
|
|
.byte $7C, $01, $67, $01, $52, $01, $3F, $01, $2D, $01, $1C, $01, $0C, $01, $FD, $00 ; CPU:$E805 PRG:2805 7C 01 67 01 52 01 3F 01 2D 01 1C 01 0C 01 FD 00
|
|
.byte $EE, $00, $E1, $00, $D4, $00, $C8, $00, $BD, $00, $B2, $00, $A8, $00, $9F, $00 ; CPU:$E815 PRG:2815 EE 00 E1 00 D4 00 C8 00 BD 00 B2 00 A8 00 9F 00
|
|
.byte $96, $00, $8D, $00, $85, $00, $7E, $00, $76, $00, $70, $00, $69, $00, $63, $00 ; CPU:$E825 PRG:2825 96 00 8D 00 85 00 7E 00 76 00 70 00 69 00 63 00
|
|
.byte $5E, $00, $58, $00, $53, $00, $4F, $00, $4A, $00, $46, $00, $42, $00, $3E, $00 ; CPU:$E835 PRG:2835 5E 00 58 00 53 00 4F 00 4A 00 46 00 42 00 3E 00
|
|
.byte $3A, $00, $37, $00, $34, $00, $31, $00, $2E, $00, $2B, $00, $29, $00, $27, $00 ; CPU:$E845 PRG:2845 3A 00 37 00 34 00 31 00 2E 00 2B 00 29 00 27 00
|
|
.byte $24, $00, $22, $00, $20, $00, $1E, $00, $1C, $00, $1B, $00, $1A, $00, $17, $EB ; CPU:$E855 PRG:2855 24 00 22 00 20 00 1E 00 1C 00 1B 00 1A 00 17 EB
|
|
.byte $85, $EB, $EA, $EB, $80, $80, $BC, $EC, $DC, $EC, $FC, $EC, $40, $40, $00, $00 ; CPU:$E865 PRG:2865 85 EB EA EB 80 80 BC EC DC EC FC EC 40 40 00 00
|
|
.byte $00, $00, $9C, $ED, $80, $80, $4D, $ED, $7B, $ED, $18, $ED, $80, $80, $50, $EC ; CPU:$E875 PRG:2875 00 00 9C ED 80 80 4D ED 7B ED 18 ED 80 80 50 EC
|
|
.byte $7E, $EC, $AC, $EC, $80, $80, $27, $EA, $63, $EA, $9F, $EA, $80, $80, $CC, $E8 ; CPU:$E885 PRG:2885 7E EC AC EC 80 80 27 EA 63 EA 9F EA 80 80 CC E8
|
|
.byte $1C, $E9, $70, $E9, $40, $00, $E1, $EA, $FF, $EA, $00, $00, $80, $80, $A2, $E9 ; CPU:$E895 PRG:2895 1C E9 70 E9 40 00 E1 EA FF EA 00 00 80 80 A2 E9
|
|
.byte $D5, $E9, $FF, $E9, $80, $80, $03, $E9, $57, $E9, $88, $E9, $40, $00, $B0, $29 ; CPU:$E8A5 PRG:28A5 D5 E9 FF E9 80 80 03 E9 57 E9 88 E9 40 00 B0 29
|
|
.byte $AA, $29, $86, $29, $A4, $30, $86, $30, $35, $F9, $8C, $2E, $F8, $98, $2D, $86 ; CPU:$E8B5 PRG:28B5 AA 29 86 29 A4 30 86 30 35 F9 8C 2E F8 98 2D 86
|
|
.byte $2D, $2E, $8C, $2D, $C8, $2B, $86, $32, $33, $8C, $32, $B0, $30, $8C, $00, $26 ; CPU:$E8C5 PRG:28C5 2D 2E 8C 2D C8 2B 86 32 33 8C 32 B0 30 8C 00 26
|
|
.byte $28, $B0, $29, $AA, $29, $86, $29, $A4, $30, $86, $30, $35, $F9, $8C, $2E, $F8 ; CPU:$E8D5 PRG:28D5 28 B0 29 AA 29 86 29 A4 30 86 30 35 F9 8C 2E F8
|
|
.byte $98, $2D, $86, $2D, $2E, $8C, $2D, $2B, $32, $33, $30, $00, $92, $30, $83, $32 ; CPU:$E8E5 PRG:28E5 98 2D 86 2D 2E 8C 2D 2B 32 33 30 00 92 30 83 32
|
|
.byte $34, $8C, $35, $00, $1D, $86, $1D, $1D, $8C, $1D, $00, $98, $00, $FF, $B0, $21 ; CPU:$E8F5 PRG:28F5 34 8C 35 00 1D 86 1D 1D 8C 1D 00 98 00 FF B0 21
|
|
.byte $AA, $21, $86, $21, $A4, $2D, $86, $2D, $30, $F9, $8C, $29, $F8, $98, $29, $86 ; CPU:$E905 PRG:2905 AA 21 86 21 A4 2D 86 2D 30 F9 8C 29 F8 98 29 86
|
|
.byte $24, $29, $8C, $24, $C8, $27, $86, $2E, $2B, $8C, $2E, $28, $92, $24, $86, $24 ; CPU:$E915 PRG:2915 24 29 8C 24 C8 27 86 2E 2B 8C 2E 28 92 24 86 24
|
|
.byte $8C, $24, $24, $24, $24, $B0, $21, $AA, $21, $86, $21, $A4, $2D, $86, $2D, $30 ; CPU:$E925 PRG:2925 8C 24 24 24 24 B0 21 AA 21 86 21 A4 2D 86 2D 30
|
|
.byte $F9, $8C, $29, $F8, $98, $29, $86, $24, $29, $8C, $29, $26, $2B, $2E, $28, $00 ; CPU:$E935 PRG:2935 F9 8C 29 F8 98 29 86 24 29 8C 29 26 2B 2E 28 00
|
|
.byte $92, $28, $83, $29, $2B, $8C, $2D, $00, $11, $86, $11, $11, $8C, $11, $00, $98 ; CPU:$E945 PRG:2945 92 28 83 29 2B 8C 2D 00 11 86 11 11 8C 11 00 98
|
|
.byte $00, $FF, $F9, $FD, $02, $98, $1D, $1C, $1A, $18, $FC, $1B, $1A, $18, $16, $18 ; CPU:$E955 PRG:2955 00 FF F9 FD 02 98 1D 1C 1A 18 FC 1B 1A 18 16 18
|
|
.byte $18, $1A, $1C, $FD, $02, $1D, $1C, $1A, $18, $FC, $F8, $8C, $1F, $1D, $1B, $2B ; CPU:$E965 PRG:2965 18 1A 1C FD 02 1D 1C 1A 18 FC F8 8C 1F 1D 1B 2B
|
|
.byte $18, $00, $92, $18, $83, $18, $18, $8C, $29, $00, $11, $86, $11, $11, $8C, $11 ; CPU:$E975 PRG:2975 18 00 92 18 83 18 18 8C 29 00 11 86 11 11 8C 11
|
|
.byte $00, $98, $00, $FF, $98, $28, $92, $24, $86, $24, $98, $27, $92, $24, $86, $24 ; CPU:$E985 PRG:2985 00 98 00 FF 98 28 92 24 86 24 98 27 92 24 86 24
|
|
.byte $28, $29, $2A, $2B, $F9, $8C, $28, $24, $F8, $98, $22, $29, $28, $92, $24, $86 ; CPU:$E995 PRG:2995 28 29 2A 2B F9 8C 28 24 F8 98 22 29 28 92 24 86
|
|
.byte $24, $98, $27, $92, $24, $86, $24, $8C, $22, $84, $21, $20, $1F, $F9, $8C, $22 ; CPU:$E9A5 PRG:29A5 24 98 27 92 24 86 24 8C 22 84 21 20 1F F9 8C 22
|
|
.byte $23, $F8, $24, $00, $98, $00, $FF, $E0, $00, $86, $1F, $21, $22, $23, $F9, $8C ; CPU:$E9B5 PRG:29B5 23 F8 24 00 98 00 FF E0 00 86 1F 21 22 23 F9 8C
|
|
.byte $1F, $1C, $F8, $98, $1D, $22, $1F, $92, $1C, $86, $1C, $98, $1E, $92, $1B, $86 ; CPU:$E9C5 PRG:29C5 1F 1C F8 98 1D 22 1F 92 1C 86 1C 98 1E 92 1B 86
|
|
.byte $1E, $8C, $16, $84, $15, $14, $13, $F9, $8C, $16, $17, $F8, $18, $00, $0C, $00 ; CPU:$E9D5 PRG:29D5 1E 8C 16 84 15 14 13 F9 8C 16 17 F8 18 00 0C 00
|
|
.byte $FF, $8C, $18, $1F, $00, $1F, $18, $1F, $00, $1F, $18, $1F, $00, $1F, $14, $1B ; CPU:$E9E5 PRG:29E5 FF 8C 18 1F 00 1F 18 1F 00 1F 18 1F 00 1F 14 1B
|
|
.byte $00, $1B, $18, $1F, $00, $1F, $14, $1B, $00, $1B, $16, $84, $15, $14, $13, $F9 ; CPU:$E9F5 PRG:29F5 00 1B 18 1F 00 1F 14 1B 00 1B 16 84 15 14 13 F9
|
|
.byte $8C, $16, $17, $F8, $18, $00, $0C, $00, $FF, $94, $00, $85, $2C, $2C, $33, $33 ; CPU:$EA05 PRG:2A05 8C 16 17 F8 18 00 0C 00 FF 94 00 85 2C 2C 33 33
|
|
.byte $8A, $33, $00, $85, $2C, $2C, $33, $33, $32, $32, $30, $30, $2E, $2E, $29, $29 ; CPU:$EA15 PRG:2A15 8A 33 00 85 2C 2C 33 33 32 32 30 30 2E 2E 29 29
|
|
.byte $26, $26, $24, $24, $94, $22, $00, $85, $31, $31, $36, $36, $8A, $36, $00, $85 ; CPU:$EA25 PRG:2A25 26 26 24 24 94 22 00 85 31 31 36 36 8A 36 00 85
|
|
.byte $31, $31, $3A, $3A, $37, $37, $35, $35, $33, $33, $31, $31, $30, $30, $2E, $2E ; CPU:$EA35 PRG:2A35 31 31 3A 3A 37 37 35 35 33 33 31 31 30 30 2E 2E
|
|
.byte $2C, $2C, $2B, $2B, $FE, $94, $00, $85, $24, $24, $30, $30, $8A, $30, $00, $85 ; CPU:$EA45 PRG:2A45 2C 2C 2B 2B FE 94 00 85 24 24 30 30 8A 30 00 85
|
|
.byte $24, $24, $30, $30, $2E, $2E, $2D, $2D, $29, $29, $26, $26, $22, $22, $1D, $1D ; CPU:$EA55 PRG:2A55 24 24 30 30 2E 2E 2D 2D 29 29 26 26 22 22 1D 1D
|
|
.byte $94, $1A, $00, $85, $2E, $2E, $31, $31, $8A, $31, $00, $85, $2E, $2E, $31, $31 ; CPU:$EA65 PRG:2A65 94 1A 00 85 2E 2E 31 31 8A 31 00 85 2E 2E 31 31
|
|
.byte $33, $33, $31, $31, $30, $30, $2E, $2E, $2C, $2C, $2B, $2B, $24, $24, $22, $22 ; CPU:$EA75 PRG:2A75 33 33 31 31 30 30 2E 2E 2C 2C 2B 2B 24 24 22 22
|
|
.byte $FE, $85, $14, $14, $20, $20, $2C, $2C, $20, $20, $14, $14, $20, $20, $2C, $2C ; CPU:$EA85 PRG:2A85 FE 85 14 14 20 20 2C 2C 20 20 14 14 20 20 2C 2C
|
|
.byte $20, $20, $16, $16, $22, $22, $2E, $2E, $22, $22, $16, $16, $22, $22, $16, $16 ; CPU:$EA95 PRG:2A95 20 20 16 16 22 22 2E 2E 22 22 16 16 22 22 16 16
|
|
.byte $22, $22, $12, $12, $1E, $1E, $2A, $2A, $1E, $1E, $12, $12, $1E, $1E, $2A, $2A ; CPU:$EAA5 PRG:2AA5 22 22 12 12 1E 1E 2A 2A 1E 1E 12 12 1E 1E 2A 2A
|
|
.byte $1E, $1E, $0F, $0F, $1B, $1B, $27, $27, $1B, $1B, $0F, $0F, $1B, $1B, $27, $27 ; CPU:$EAB5 PRG:2AB5 1E 1E 0F 0F 1B 1B 27 27 1B 1B 0F 0F 1B 1B 27 27
|
|
.byte $25, $25, $FE, $83, $30, $2B, $24, $1F, $18, $13, $0C, $07, $18, $17, $16, $15 ; CPU:$EAC5 PRG:2AC5 25 25 FE 83 30 2B 24 1F 18 13 0C 07 18 17 16 15
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|
.byte $14, $15, $16, $17, $92, $18, $86, $18, $F9, $8C, $1B, $1B, $F8, $98, $18, $00 ; CPU:$EAD5 PRG:2AD5 14 15 16 17 92 18 86 18 F9 8C 1B 1B F8 98 18 00
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|
.byte $FF, $98, $00, $83, $0C, $0B, $0A, $09, $08, $09, $0A, $0B, $92, $0C, $86, $0C ; CPU:$EAE5 PRG:2AE5 FF 98 00 83 0C 0B 0A 09 08 09 0A 0B 92 0C 86 0C
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|
.byte $F9, $8C, $0F, $0F, $F8, $98, $0C, $00, $FF, $87, $27, $33, $3F, $33, $36, $37 ; CPU:$EAF5 PRG:2AF5 F9 8C 0F 0F F8 98 0C 00 FF 87 27 33 3F 33 36 37
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|
.byte $33, $31, $27, $33, $3F, $33, $36, $37, $33, $31, $16, $16, $F9, $8E, $16, $F8 ; CPU:$EB05 PRG:2B05 33 31 27 33 3F 33 36 37 33 31 16 16 F9 8E 16 F8
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|
.byte $87, $22, $22, $F9, $8E, $2E, $0D, $0F, $F8, $87, $38, $2E, $33, $38, $FD, $03 ; CPU:$EB15 PRG:2B15 87 22 22 F9 8E 2E 0D 0F F8 87 38 2E 33 38 FD 03
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|
.byte $F9, $8E, $37, $33, $32, $33, $F8, $9C, $2E, $87, $2C, $2E, $2A, $2B, $8E, $00 ; CPU:$EB25 PRG:2B25 F9 8E 37 33 32 33 F8 9C 2E 87 2C 2E 2A 2B 8E 00
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|
.byte $3A, $00, $3A, $87, $33, $33, $F9, $8E, $33, $F8, $87, $38, $2E, $33, $38, $FC ; CPU:$EB35 PRG:2B35 3A 00 3A 87 33 33 F9 8E 33 F8 87 38 2E 33 38 FC
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|
.byte $F9, $8E, $37, $F8, $87, $32, $33, $2C, $2E, $F9, $8E, $2B, $F8, $87, $2C, $2C ; CPU:$EB45 PRG:2B45 F9 8E 37 F8 87 32 33 2C 2E F9 8E 2B F8 87 2C 2C
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|
.byte $F9, $8E, $2C, $F8, $87, $2B, $2B, $F9, $8E, $2B, $27, $27, $00, $F8, $87, $25 ; CPU:$EB55 PRG:2B55 F9 8E 2C F8 87 2B 2B F9 8E 2B 27 27 00 F8 87 25
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|
.byte $26, $8E, $27, $00, $9C, $00, $FF, $87, $1B, $27, $33, $27, $2A, $2B, $27, $25 ; CPU:$EB65 PRG:2B65 26 8E 27 00 9C 00 FF 87 1B 27 33 27 2A 2B 27 25
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|
.byte $1B, $27, $33, $27, $2A, $2B, $27, $25, $13, $13, $F9, $8E, $13, $F8, $87, $1F ; CPU:$EB75 PRG:2B75 1B 27 33 27 2A 2B 27 25 13 13 F9 8E 13 F8 87 1F
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|
.byte $1F, $F9, $8E, $2B, $01, $02, $F8, $87, $2C, $22, $27, $2C, $FD, $03, $F9, $8E ; CPU:$EB85 PRG:2B85 1F F9 8E 2B 01 02 F8 87 2C 22 27 2C FD 03 F9 8E
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|
.byte $31, $2E, $2A, $2B, $F8, $9C, $25, $00, $8E, $27, $22, $25, $2C, $9C, $2B, $87 ; CPU:$EB95 PRG:2B95 31 2E 2A 2B F8 9C 25 00 8E 27 22 25 2C 9C 2B 87
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|
.byte $35, $22, $30, $33, $FC, $F9, $8E, $33, $F8, $87, $2A, $2B, $26, $27, $F9, $8E ; CPU:$EBA5 PRG:2BA5 35 22 30 33 FC F9 8E 33 F8 87 2A 2B 26 27 F9 8E
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|
.byte $22, $F8, $87, $27, $27, $F9, $8E, $27, $F8, $87, $27, $27, $F9, $8E, $27, $1F ; CPU:$EBB5 PRG:2BB5 22 F8 87 27 27 F9 8E 27 F8 87 27 27 F9 8E 27 1F
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|
.byte $1F, $00, $F8, $87, $19, $1A, $8E, $1B, $00, $9C, $00, $FF, $87, $1B, $1B, $1B ; CPU:$EBC5 PRG:2BC5 1F 00 F8 87 19 1A 8E 1B 00 9C 00 FF 87 1B 1B 1B
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|
.byte $1B, $9C, $00, $87, $1B, $1B, $1B, $1B, $9C, $00, $87, $19, $19, $F9, $8E, $19 ; CPU:$EBD5 PRG:2BD5 1B 9C 00 87 1B 1B 1B 1B 9C 00 87 19 19 F9 8E 19
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|
.byte $F8, $87, $25, $25, $F9, $8E, $32, $F8, $B8, $00, $FD, $03, $87, $1B, $1B, $F9 ; CPU:$EBE5 PRG:2BE5 F8 87 25 25 F9 8E 32 F8 B8 00 FD 03 87 1B 1B F9
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|
.byte $8E, $1B, $1E, $F8, $87, $1F, $22, $27, $1B, $1B, $1B, $1E, $F9, $8E, $1F, $F8 ; CPU:$EBF5 PRG:2BF5 8E 1B 1E F8 87 1F 22 27 1B 1B 1B 1E F9 8E 1F F8
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|
.byte $87, $18, $19, $19, $19, $25, $18, $1A, $8E, $16, $87, $25, $19, $19, $19, $9C ; CPU:$EC05 PRG:2C05 87 18 19 19 19 25 18 1A 8E 16 87 25 19 19 19 9C
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|
.byte $00, $FC, $F9, $8E, $2E, $F8, $87, $2D, $2E, $2A, $2B, $27, $22, $9C, $00, $87 ; CPU:$EC15 PRG:2C15 00 FC F9 8E 2E F8 87 2D 2E 2A 2B 27 22 9C 00 87
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|
.byte $23, $23, $F9, $8E, $23, $22, $22, $F8, $00, $87, $19, $1A, $8E, $1B, $00, $9C ; CPU:$EC25 PRG:2C25 23 23 F9 8E 23 22 22 F8 00 87 19 1A 8E 1B 00 9C
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|
.byte $00, $FF, $FD, $02, $90, $25, $88, $27, $29, $00, $29, $2B, $00, $FC, $C0, $00 ; CPU:$EC35 PRG:2C35 00 FF FD 02 90 25 88 27 29 00 29 2B 00 FC C0 00
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|
.byte $88, $22, $19, $22, $20, $1F, $19, $1F, $20, $FD, $02, $27, $29, $27, $2A, $00 ; CPU:$EC45 PRG:2C45 88 22 19 22 20 1F 19 1F 20 FD 02 27 29 27 2A 00
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|
.byte $29, $27, $00, $FC, $C0, $00, $88, $20, $17, $20, $1E, $1D, $17, $1D, $1F, $FE ; CPU:$EC55 PRG:2C55 29 27 00 FC C0 00 88 20 17 20 1E 1D 17 1D 1F FE
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|
.byte $FD, $02, $90, $22, $88, $24, $26, $00, $26, $27, $00, $FC, $FD, $02, $1B, $13 ; CPU:$EC65 PRG:2C65 FD 02 90 22 88 24 26 00 26 27 00 FC FD 02 1B 13
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|
.byte $1B, $19, $18, $13, $18, $19, $FC, $FD, $02, $23, $25, $23, $27, $00, $25, $23 ; CPU:$EC75 PRG:2C75 1B 19 18 13 18 19 FC FD 02 23 25 23 27 00 25 23
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|
.byte $00, $FC, $FD, $02, $19, $11, $19, $17, $16, $11, $16, $19, $FC, $FE, $FD, $04 ; CPU:$EC85 PRG:2C85 00 FC FD 02 19 11 19 17 16 11 16 19 FC FE FD 04
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|
.byte $90, $1B, $1B, $1B, $1B, $FC, $FD, $04, $19, $19, $19, $19, $FC, $FE, $85, $33 ; CPU:$EC95 PRG:2C95 90 1B 1B 1B 1B FC FD 04 19 19 19 19 FC FE 85 33
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|
.byte $00, $32, $33, $32, $33, $32, $33, $2E, $00, $2D, $2E, $2D, $2E, $2D, $2E, $2B ; CPU:$ECA5 PRG:2CA5 00 32 33 32 33 32 33 2E 00 2D 2E 2D 2E 2D 2E 2B
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|
.byte $2C, $2D, $2E, $2B, $2C, $2D, $2E, $2B, $00, $27, $00, $94, $25, $FF, $85, $2B ; CPU:$ECB5 PRG:2CB5 2C 2D 2E 2B 2C 2D 2E 2B 00 27 00 94 25 FF 85 2B
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|
.byte $00, $2A, $2B, $2A, $2B, $2A, $2B, $27, $00, $26, $27, $26, $27, $26, $27, $27 ; CPU:$ECC5 PRG:2CC5 00 2A 2B 2A 2B 2A 2B 27 00 26 27 26 27 26 27 27
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|
.byte $29, $2A, $2B, $27, $29, $2A, $2B, $27, $00, $1F, $00, $94, $22, $FF, $F9, $8A ; CPU:$ECD5 PRG:2CD5 29 2A 2B 27 29 2A 2B 27 00 1F 00 94 22 FF F9 8A
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|
.byte $1B, $1B, $1F, $22, $1B, $1B, $1F, $22, $F8, $85, $22, $24, $26, $27, $22, $24 ; CPU:$ECE5 PRG:2CE5 1B 1B 1F 22 1B 1B 1F 22 F8 85 22 24 26 27 22 24
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|
.byte $26, $27, $F9, $8A, $22, $1B, $F8, $94, $16, $FF, $FD, $02, $87, $27, $27, $F9 ; CPU:$ECF5 PRG:2CF5 26 27 F9 8A 22 1B F8 94 16 FF FD 02 87 27 27 F9
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|
.byte $8E, $30, $31, $F8, $87, $22, $22, $F9, $8E, $2E, $30, $F8, $87, $31, $30, $F9 ; CPU:$ED05 PRG:2D05 8E 30 31 F8 87 22 22 F9 8E 2E 30 F8 87 31 30 F9
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|
.byte $8E, $2E, $F8, $FC, $FD, $02, $87, $25, $25, $F9, $8E, $2E, $2F, $F8, $87, $20 ; CPU:$ED15 PRG:2D15 8E 2E F8 FC FD 02 87 25 25 F9 8E 2E 2F F8 87 20
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|
.byte $20, $F9, $8E, $2C, $2E, $F8, $87, $2F, $2E, $F9, $8E, $2C, $F8, $FC, $FE, $9C ; CPU:$ED25 PRG:2D25 20 F9 8E 2C 2E F8 87 2F 2E F9 8E 2C F8 FC FE 9C
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|
.byte $00, $87, $25, $95, $00, $B8, $00, $9C, $00, $95, $27, $87, $27, $F9, $8E, $2C ; CPU:$ED35 PRG:2D35 00 87 25 95 00 B8 00 9C 00 95 27 87 27 F9 8E 2C
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|
.byte $2B, $F8, $27, $00, $9C, $00, $87, $23, $95, $00, $B8, $00, $9C, $00, $95, $25 ; CPU:$ED45 PRG:2D45 2B F8 27 00 9C 00 87 23 95 00 B8 00 9C 00 95 25
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|
.byte $87, $25, $F9, $8E, $2A, $F8, $87, $29, $2A, $8E, $25, $00, $FE, $9C, $00, $87 ; CPU:$ED55 PRG:2D55 87 25 F9 8E 2A F8 87 29 2A 8E 25 00 FE 9C 00 87
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|
.byte $1D, $95, $00, $B8, $00, $9C, $00, $87, $1D, $95, $00, $B8, $00, $9C, $00, $87 ; CPU:$ED65 PRG:2D65 1D 95 00 B8 00 9C 00 87 1D 95 00 B8 00 9C 00 87
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|
.byte $1B, $95, $00, $B8, $00, $9C, $00, $87, $1B, $95, $00, $B8, $00, $FE, $87, $27 ; CPU:$ED75 PRG:2D75 1B 95 00 B8 00 9C 00 87 1B 95 00 B8 00 FE 87 27
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|
.byte $27, $33, $27, $F9, $8E, $2A, $F8, $87, $2E, $30, $F9, $8E, $31, $31, $F8, $30 ; CPU:$ED85 PRG:2D85 27 33 27 F9 8E 2A F8 87 2E 30 F9 8E 31 31 F8 30
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|
.byte $00, $87, $25, $25, $31, $25, $F9, $8E, $29, $F8, $87, $2C, $2E, $F9, $8E, $2F ; CPU:$ED95 PRG:2D95 00 87 25 25 31 25 F9 8E 29 F8 87 2C 2E F9 8E 2F
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|
.byte $F8, $87, $2E, $2F, $25, $24, $F9, $8E, $25, $F8, $87, $22, $22, $2E, $22, $F9 ; CPU:$EDA5 PRG:2DA5 F8 87 2E 2F 25 24 F9 8E 25 F8 87 22 22 2E 22 F9
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|
.byte $8E, $2C, $F8, $87, $2B, $2C, $F9, $8E, $22, $2E, $F8, $22, $00, $87, $22, $22 ; CPU:$EDB5 PRG:2DB5 8E 2C F8 87 2B 2C F9 8E 22 2E F8 22 00 87 22 22
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|
.byte $2E, $22, $F9, $8E, $2C, $F8, $87, $2B, $2C, $F9, $8E, $22, $2E, $F8, $87, $22 ; CPU:$EDC5 PRG:2DC5 2E 22 F9 8E 2C F8 87 2B 2C F9 8E 22 2E F8 87 22
|
|
.byte $22, $24, $26, $FE, $3D, $01, $03, $81, $03, $80, $1B, $04, $06, $84, $1B, $04 ; CPU:$EDD5 PRG:2DD5 22 24 26 FE 3D 01 03 81 03 80 1B 04 06 84 1B 04
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|
.byte $02, $05, $34, $01, $08, $41, $13, $01, $01, $00, $06, $01, $01, $00, $0F, $01 ; CPU:$EDE5 PRG:2DE5 02 05 34 01 08 41 13 01 01 00 06 01 01 00 0F 01
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|
.byte $01, $00, $03, $01, $01, $00, $11, $01, $06, $81, $1B, $01, $03, $81, $0E, $01 ; CPU:$EDF5 PRG:2DF5 01 00 03 01 01 00 11 01 06 81 1B 01 03 81 0E 01
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|
.byte $1A, $00, $11, $01, $05, $81, $16, $01, $02, $00, $01, $01, $11, $04, $10, $00 ; CPU:$EE05 PRG:2E05 1A 00 11 01 05 81 16 01 02 00 01 01 11 04 10 00
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|
.byte $10, $40, $10, $00, $02, $04, $01, $00, $01, $04, $01, $00, $0E, $04, $01, $00 ; CPU:$EE15 PRG:2E15 10 40 10 00 02 04 01 00 01 04 01 00 0E 04 01 00
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|
.byte $02, $04, $01, $00, $01, $04, $38, $00, $1A, $04, $03, $00, $04, $02, $01, $00 ; CPU:$EE25 PRG:2E25 02 04 01 00 01 04 38 00 1A 04 03 00 04 02 01 00
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|
.byte $04, $80, $09, $00, $16, $02, $02, $00, $02, $04, $05, $02, $01, $00, $15, $04 ; CPU:$EE35 PRG:2E35 04 80 09 00 16 02 02 00 02 04 05 02 01 00 15 04
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|
.byte $3A, $00, $0A, $40, $17, $00, $0D, $04, $02, $00, $06, $80, $06, $00, $1D, $08 ; CPU:$EE45 PRG:2E45 3A 00 0A 40 17 00 0D 04 02 00 06 80 06 00 1D 08
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|
.byte $01, $00, $0C, $01, $02, $00, $09, $40, $0A, $00, $28, $02, $01, $00, $20, $02 ; CPU:$EE55 PRG:2E55 01 00 0C 01 02 00 09 40 0A 00 28 02 01 00 20 02
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|
.byte $1E, $04, $02, $84, $05, $80, $5D, $01, $06, $00, $1D, $02, $21, $08, $04, $00 ; CPU:$EE65 PRG:2E65 1E 04 02 84 05 80 5D 01 06 00 1D 02 21 08 04 00
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|
.byte $06, $80, $03, $00, $1A, $02, $02, $00, $0F, $08, $02, $00, $09, $40, $08, $00 ; CPU:$EE75 PRG:2E75 06 80 03 00 1A 02 02 00 0F 08 02 00 09 40 08 00
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|
.byte $08, $40, $14, $00, $0F, $08, $01, $00, $0D, $08, $01, $00, $01, $08, $01, $00 ; CPU:$EE85 PRG:2E85 08 40 14 00 0F 08 01 00 0D 08 01 00 01 08 01 00
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|
.byte $11, $08, $02, $00, $1E, $01, $06, $81, $15, $01, $05, $81, $19, $01, $06, $81 ; CPU:$EE95 PRG:2E95 11 08 02 00 1E 01 06 81 15 01 05 81 19 01 06 81
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|
.byte $06, $00, $1C, $04, $06, $84, $01, $81, $01, $01, $03, $00, $1B, $01, $01, $00 ; CPU:$EEA5 PRG:2EA5 06 00 1C 04 06 84 01 81 01 01 03 00 1B 01 01 00
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|
.byte $0E, $08, $01, $48, $08, $40, $17, $00, $0D, $04, $01, $84, $06, $80, $02, $00 ; CPU:$EEB5 PRG:2EB5 0E 08 01 48 08 40 17 00 0D 04 01 84 06 80 02 00
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|
.byte $1E, $02, $04, $82, $01, $80, $01, $00, $1F, $04, $05, $84, $1E, $04, $04, $84 ; CPU:$EEC5 PRG:2EC5 1E 02 04 82 01 80 01 00 1F 04 05 84 1E 04 04 84
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|
.byte $02, $80, $1C, $02, $02, $00, $0F, $08, $01, $00, $09, $40, $11, $00, $0F, $04 ; CPU:$EED5 PRG:2ED5 02 80 1C 02 02 00 0F 08 01 00 09 40 11 00 0F 04
|
|
.byte $01, $05, $01, $00, $04, $01, $09, $81, $14, $01, $06, $81, $19, $01, $01, $00 ; CPU:$EEE5 PRG:2EE5 01 05 01 00 04 01 09 81 14 01 06 81 19 01 01 00
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|
.byte $0E, $08, $03, $48, $01, $00, $06, $40, $14, $00, $06, $80, $02, $88, $04, $08 ; CPU:$EEF5 PRG:2EF5 0E 08 03 48 01 00 06 40 14 00 06 80 02 88 04 08
|
|
.byte $01, $00, $08, $08, $01, $00, $03, $08, $02, $88, $01, $00, $02, $88, $01, $00 ; CPU:$EF05 PRG:2F05 01 00 08 08 01 00 03 08 02 88 01 00 02 88 01 00
|
|
.byte $14, $08, $05, $88, $04, $08, $02, $00, $1B, $01, $07, $81, $18, $01, $06, $81 ; CPU:$EF15 PRG:2F15 14 08 05 88 04 08 02 00 1B 01 07 81 18 01 06 81
|
|
.byte $15, $01, $02, $09, $10, $08, $0A, $40, $1A, $00, $0A, $04, $01, $00, $06, $04 ; CPU:$EF25 PRG:2F25 15 01 02 09 10 08 0A 40 1A 00 0A 04 01 00 06 04
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|
.byte $01, $00, $1E, $02, $06, $00, $10, $08, $03, $84, $FF, $FF, $FF, $FF, $FF, $FF ; CPU:$EF35 PRG:2F35 01 00 1E 02 06 00 10 08 03 84 FF FF FF FF FF FF
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|
.byte $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF ; CPU:$EF45 PRG:2F45 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
|
|
.byte $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF ; CPU:$EF55 PRG:2F55 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
|
|
.byte $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF ; CPU:$EF65 PRG:2F65 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
|
|
.byte $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF ; CPU:$EF75 PRG:2F75 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
|
|
.byte $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF ; CPU:$EF85 PRG:2F85 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
|
|
.byte $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF ; CPU:$EF95 PRG:2F95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
|
|
.byte $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF ; CPU:$EFA5 PRG:2FA5 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
|
|
.byte $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF ; CPU:$EFB5 PRG:2FB5 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
|
|
.byte $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF ; CPU:$EFC5 PRG:2FC5 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
|
|
.byte $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF ; CPU:$EFD5 PRG:2FD5 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
|
|
.byte $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FC, $00, $00, $1F, $F0 ; CPU:$EFE5 PRG:2FE5 FF FF FF FF FF FF FF FF FF FF FF FC 00 00 1F F0
|
|
.byte $00, $1F, $FE, $00, $00, $07, $FF, $FF, $FF, $30, $00, $00, $3F, $FF, $E0, $07 ; CPU:$EFF5 PRG:2FF5 00 1F FE 00 00 07 FF FF FF 30 00 00 3F FF E0 07
|
|
.byte $F0, $3F, $F8, $1F, $F0, $1F, $FF, $FF, $C0, $00, $03, $FF, $C0, $FF, $FF, $C0 ; CPU:$F005 PRG:3005 F0 3F F8 1F F0 1F FF FF C0 00 03 FF C0 FF FF C0
|
|
.byte $7F, $C7, $FF, $00, $00, $00, $FF, $F0, $00, $1F, $FF, $FE, $00, $00, $00, $00 ; CPU:$F015 PRG:3015 7F C7 FF 00 00 00 FF F0 00 1F FF FE 00 00 00 00
|
|
.byte $00, $00, $00, $7F, $F0, $00, $07, $FF, $FF, $C0, $01, $80, $FF, $00, $02, $80 ; CPU:$F025 PRG:3025 00 00 00 7F F0 00 07 FF FF C0 01 80 FF 00 02 80
|
|
.byte $3F, $FF, $F8, $00, $03, $FF, $FF, $FF, $FE, $00, $00, $1F, $FF, $FF, $F0, $01 ; CPU:$F035 PRG:3035 3F FF F8 00 03 FF FF FF FE 00 00 1F FF FF F0 01
|
|
.byte $FF, $FF, $F0, $00, $0F, $FF, $FF, $FF, $00, $07, $FF, $F0, $00, $FB, $FF, $F8 ; CPU:$F045 PRG:3045 FF FF F0 00 0F FF FF FF 00 07 FF F0 00 FB FF F8
|
|
.byte $FF, $FF, $00, $00, $00, $01, $FF, $FF, $FF, $C0, $3F, $F8, $00, $00, $00, $00 ; CPU:$F055 PRG:3055 FF FF 00 00 00 01 FF FF FF C0 3F F8 00 00 00 00
|
|
.byte $7F, $FF, $FF, $FF, $FF, $FF, $FE, $00, $00, $00, $00, $0F, $FF, $F0, $00, $03 ; CPU:$F065 PRG:3065 7F FF FF FF FF FF FE 00 00 00 00 0F FF F0 00 03
|
|
.byte $FF, $FF, $FF, $E0, $00, $00, $03, $FF, $FF, $F8, $00, $00, $00, $FF, $FF, $FF ; CPU:$F075 PRG:3075 FF FF FF E0 00 00 03 FF FF F8 00 00 00 FF FF FF
|
|
.byte $00, $00, $00, $00, $1F, $E0, $00, $00, $07, $FF, $FF, $FE, $00, $00, $01, $FF ; CPU:$F085 PRG:3085 00 00 00 00 1F E0 00 00 07 FF FF FE 00 00 01 FF
|
|
.byte $FE, $00, $00, $07, $FF, $FF, $FF, $F8, $00, $00, $00, $1F, $FF, $FF, $E0, $00 ; CPU:$F095 PRG:3095 FE 00 00 07 FF FF FF F8 00 00 00 1F FF FF E0 00
|
|
.byte $00, $01, $FF, $FF, $FF, $FF, $FF, $C0, $00, $00, $00, $00, $0F, $FF, $FF, $FF ; CPU:$F0A5 PRG:30A5 00 01 FF FF FF FF FF C0 00 00 00 00 0F FF FF FF
|
|
.byte $FE, $00, $00, $07, $E0, $00, $00, $00, $00, $7F, $FF, $EF, $FF, $FF, $FF, $FF ; CPU:$F0B5 PRG:30B5 FE 00 00 07 E0 00 00 00 00 7F FF EF FF FF FF FF
|
|
.byte $FF, $80, $00, $00, $3F, $FF, $C0, $00, $00, $00, $0F, $FF, $FF, $FC, $00, $FF ; CPU:$F0C5 PRG:30C5 FF 80 00 00 3F FF C0 00 00 00 0F FF FF FC 00 FF
|
|
.byte $FF, $FE, $00, $00, $00, $7F, $FF, $FF, $FF, $C0, $00, $00, $00, $03, $FF, $FF ; CPU:$F0D5 PRG:30D5 FF FE 00 00 00 7F FF FF FF C0 00 00 00 03 FF FF
|
|
.byte $FF, $C0, $00, $00, $00, $1F, $FF, $FF, $FF, $FF, $FE, $00, $07, $FF, $00, $00 ; CPU:$F0E5 PRG:30E5 FF C0 00 00 00 1F FF FF FF FF FE 00 07 FF 00 00
|
|
.byte $0F, $FF, $FF, $FC, $00, $00, $00, $00, $3F, $FF, $FF, $F0, $00, $00, $00, $0F ; CPU:$F0F5 PRG:30F5 0F FF FF FC 00 00 00 00 3F FF FF F0 00 00 00 0F
|
|
.byte $FE, $00, $00, $03, $FF, $FF, $C0, $00, $00, $00, $00, $FF, $FF, $FF, $FF, $FF ; CPU:$F105 PRG:3105 FE 00 00 03 FF FF C0 00 00 00 00 FF FF FF FF FF
|
|
.byte $80, $00, $01, $FF, $FF, $FF, $F0, $00, $00, $00, $00, $7F, $FF, $FF, $DA, $2E ; CPU:$F115 PRG:3115 80 00 01 FF FF FF F0 00 00 00 00 7F FF FF DA 2E
|
|
.byte $00, $00, $00, $7F, $FF, $FF, $FF, $FE, $00, $00, $FF, $80, $FF, $FC, $00, $00 ; CPU:$F125 PRG:3125 00 00 00 7F FF FF FF FE 00 00 FF 80 FF FC 00 00
|
|
.byte $00, $00, $03, $FF, $FF, $FF, $FF, $FF, $80, $00, $00, $0F, $FF, $FF, $F8, $00 ; CPU:$F135 PRG:3135 00 00 03 FF FF FF FF FF 80 00 00 0F FF FF F8 00
|
|
.byte $00, $00, $03, $FF, $FF, $FF, $C0, $00, $00, $00, $07, $FF, $FF, $FF, $FF, $80 ; CPU:$F145 PRG:3145 00 00 03 FF FF FF C0 00 00 00 07 FF FF FF FF 80
|
|
.byte $00, $00, $01, $FF, $FF, $00, $00, $00, $01, $FF, $FF, $FF, $FF, $FF, $FF, $00 ; CPU:$F155 PRG:3155 00 00 01 FF FF 00 00 00 01 FF FF FF FF FF FF 00
|
|
.byte $3F, $FF, $F0, $00, $00, $00, $07, $FF, $FF, $FF, $FE, $00, $03, $FF, $FE, $00 ; CPU:$F165 PRG:3165 3F FF F0 00 00 00 07 FF FF FF FE 00 03 FF FE 00
|
|
.byte $00, $07, $FF, $FF, $FF, $C0, $00, $00, $00, $00, $7F, $FF, $E0, $00, $00, $00 ; CPU:$F175 PRG:3175 00 07 FF FF FF C0 00 00 00 00 7F FF E0 00 00 00
|
|
.byte $03, $FF, $FF, $FF, $FF, $FF, $00, $00, $7C, $00, $00, $00, $0F, $FF, $FF, $FF ; CPU:$F185 PRG:3185 03 FF FF FF FF FF 00 00 7C 00 00 00 0F FF FF FF
|
|
.byte $FF, $FF, $F8, $00, $00, $00, $3F, $FF, $FF, $FF, $C0, $00, $00, $07, $FF, $F0 ; CPU:$F195 PRG:3195 FF FF F8 00 00 00 3F FF FF FF C0 00 00 07 FF F0
|
|
.byte $00, $00, $7F, $FF, $80, $00, $07, $FC, $00, $FF, $FF, $FF, $FF, $00, $00, $00 ; CPU:$F1A5 PRG:31A5 00 00 7F FF 80 00 07 FC 00 FF FF FF FF 00 00 00
|
|
.byte $0F, $FF, $FF, $FF, $FE, $00, $00, $00, $3F, $FF, $FF, $F8, $00, $00, $00, $00 ; CPU:$F1B5 PRG:31B5 0F FF FF FF FE 00 00 00 3F FF FF F8 00 00 00 00
|
|
.byte $3F, $FF, $C0, $00, $00, $FF, $FF, $FF, $E0, $00, $00, $00, $1F, $FF, $FF, $FF ; CPU:$F1C5 PRG:31C5 3F FF C0 00 00 FF FF FF E0 00 00 00 1F FF FF FF
|
|
.byte $FC, $00, $00, $7F, $FF, $FF, $F8, $00, $00, $00, $3F, $FF, $FF, $FF, $00, $00 ; CPU:$F1D5 PRG:31D5 FC 00 00 7F FF FF F8 00 00 00 3F FF FF FF 00 00
|
|
.byte $00, $00, $00, $FF, $FF, $FE, $11, $B0, $3F, $FF, $E0, $00, $00, $00, $00, $07 ; CPU:$F1E5 PRG:31E5 00 00 00 FF FF FE 11 B0 3F FF E0 00 00 00 00 07
|
|
.byte $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $F8, $00, $00, $00, $00, $00, $00, $00 ; CPU:$F1F5 PRG:31F5 FF FF FF FF FF FF FF FF F8 00 00 00 00 00 00 00
|
|
.byte $0F, $FF, $FF, $FF, $FF, $FF, $80, $00, $00, $00, $03, $FF, $FE, $00, $0F, $FF ; CPU:$F205 PRG:3205 0F FF FF FF FF FF 80 00 00 00 03 FF FE 00 0F FF
|
|
.byte $FF, $80, $00, $00, $00, $FF, $FF, $FF, $FC, $00, $00, $00, $00, $FF, $FF, $FE ; CPU:$F215 PRG:3215 FF 80 00 00 00 FF FF FF FC 00 00 00 00 FF FF FE
|
|
.byte $00, $07, $FF, $FF, $FF, $FF, $E0, $00, $00, $00, $00, $0F, $FF, $A0, $BF, $FF ; CPU:$F225 PRG:3225 00 07 FF FF FF FF E0 00 00 00 00 0F FF A0 BF FF
|
|
.byte $FF, $FE, $00, $00, $7F, $FC, $00, $00, $00, $7F, $FF, $FF, $E0, $00, $00, $00 ; CPU:$F235 PRG:3235 FF FE 00 00 7F FC 00 00 00 7F FF FF E0 00 00 00
|
|
.byte $3F, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $80, $00, $00, $00, $07, $F8, $00, $00 ; CPU:$F245 PRG:3245 3F FF FF FF FF FF FF FF 80 00 00 00 07 F8 00 00
|
|
.byte $00, $00, $03, $FF, $FF, $FF, $FF, $FF, $00, $00, $00, $00, $00, $01, $FF, $FF ; CPU:$F255 PRG:3255 00 00 03 FF FF FF FF FF 00 00 00 00 00 01 FF FF
|
|
.byte $FF, $F0, $00, $07, $FF, $FF, $FC, $00, $00, $00, $00, $3F, $FF, $FF, $FF, $FF ; CPU:$F265 PRG:3265 FF F0 00 07 FF FF FC 00 00 00 00 3F FF FF FF FF
|
|
.byte $0F, $FF, $FF, $FE, $00, $00, $00, $00, $00, $FF, $FF, $FF, $FF, $F8, $00, $01 ; CPU:$F275 PRG:3275 0F FF FF FE 00 00 00 00 00 FF FF FF FF F8 00 01
|
|
.byte $FF, $FC, $00, $00, $00, $00, $FF, $FF, $FF, $FF, $C0, $00, $00, $00, $00, $03 ; CPU:$F285 PRG:3285 FF FC 00 00 00 00 FF FF FF FF C0 00 00 00 00 03
|
|
.byte $FF, $FF, $80, $00, $00, $00, $00, $3F, $FF, $FF, $FF, $FF, $FF, $C0, $00, $3F ; CPU:$F295 PRG:3295 FF FF 80 00 00 00 00 3F FF FF FF FF FF C0 00 3F
|
|
.byte $FF, $FF, $FF, $F8, $00, $00, $02, $00, $00, $00, $00, $00, $07, $FF, $FF, $FF ; CPU:$F2A5 PRG:32A5 FF FF FF F8 00 00 02 00 00 00 00 00 07 FF FF FF
|
|
.byte $FF, $FF, $FF, $FF, $E0, $B8, $00, $00, $00, $00, $00, $00, $3F, $FF, $FF, $FF ; CPU:$F2B5 PRG:32B5 FF FF FF FF E0 B8 00 00 00 00 00 00 3F FF FF FF
|
|
.byte $FF, $FF, $F8, $00, $00, $00, $00, $1F, $FF, $FF, $FF, $FF, $80, $00, $00, $00 ; CPU:$F2C5 PRG:32C5 FF FF F8 00 00 00 00 1F FF FF FF FF 80 00 00 00
|
|
.byte $00, $0F, $FF, $FF, $FF, $DF, $FF, $00, $00, $0F, $FF, $FF, $80, $00, $00, $00 ; CPU:$F2D5 PRG:32D5 00 0F FF FF FF DF FF 00 00 0F FF FF 80 00 00 00
|
|
.byte $03, $FF, $FF, $FF, $FF, $FF, $FF, $C0, $00, $00, $00, $01, $FF, $FF, $FF, $00 ; CPU:$F2E5 PRG:32E5 03 FF FF FF FF FF FF C0 00 00 00 01 FF FF FF 00
|
|
.byte $00, $00, $00, $1F, $FF, $FF, $FF, $FF, $FF, $FF, $E0, $00, $FF, $00, $00, $00 ; CPU:$F2F5 PRG:32F5 00 00 00 1F FF FF FF FF FF FF E0 00 FF 00 00 00
|
|
.byte $00, $00, $00, $01, $FF, $FF, $FF, $C0, $00, $00, $03, $FF, $FF, $FF, $FF, $FF ; CPU:$F305 PRG:3305 00 00 00 01 FF FF FF C0 00 00 03 FF FF FF FF FF
|
|
.byte $F0, $00, $00, $00, $00, $00, $07, $FF, $FF, $FF, $FF, $FF, $80, $00, $00, $00 ; CPU:$F315 PRG:3315 F0 00 00 00 00 00 07 FF FF FF FF FF 80 00 00 00
|
|
.byte $00, $0F, $FF, $FF, $FF, $F0, $00, $3F, $FF, $FF, $00, $00, $17, $FB, $C8, $84 ; CPU:$F325 PRG:3325 00 0F FF FF FF F0 00 3F FF FF 00 00 17 FB C8 84
|
|
.byte $E5, $3F, $FF, $20, $00, $14, $19, $D9, $9F, $F6, $00, $00, $17, $FF, $FF, $FF ; CPU:$F335 PRG:3335 E5 3F FF 20 00 14 19 D9 9F F6 00 00 17 FF FF FF
|
|
.byte $FF, $FE, $00, $00, $00, $00, $00, $03, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FE ; CPU:$F345 PRG:3345 FF FE 00 00 00 00 00 03 FF FF FF FF FF FF FF FE
|
|
.byte $00, $00, $00, $00, $00, $00, $00, $00, $FF, $FF, $FF, $DC, $80, $00, $26, $FE ; CPU:$F355 PRG:3355 00 00 00 00 00 00 00 00 FF FF FF DC 80 00 26 FE
|
|
.byte $57, $FF, $FF, $80, $00, $00, $07, $FC, $C0, $3F, $FF, $FF, $7F, $BD, $C4, $61 ; CPU:$F365 PRG:3365 57 FF FF 80 00 00 07 FC C0 3F FF FF 7F BD C4 61
|
|
.byte $4E, $EE, $67, $20, $46, $64, $EF, $E6, $00, $00, $FD, $A0, $00, $00, $00, $00 ; CPU:$F375 PRG:3375 4E EE 67 20 46 64 EF E6 00 00 FD A0 00 00 00 00
|
|
.byte $07, $FF, $FF, $FF, $FF, $FF, $F0, $00, $00, $00, $00, $00, $7F, $FF, $FF, $FF ; CPU:$F385 PRG:3385 07 FF FF FF FF FF F0 00 00 00 00 00 7F FF FF FF
|
|
.byte $FF, $C0, $00, $00, $00, $00, $0F, $7F, $F8, $DF, $FF, $FF, $C0, $03, $FB, $9F ; CPU:$F395 PRG:3395 FF C0 00 00 00 00 0F 7F F8 DF FF FF C0 03 FB 9F
|
|
.byte $AF, $FF, $FF, $80, $00, $00, $02, $F6, $A5, $6F, $FF, $FF, $FC, $00, $3F, $FF ; CPU:$F3A5 PRG:33A5 AF FF FF 80 00 00 02 F6 A5 6F FF FF FC 00 3F FF
|
|
.byte $C0, $00, $00, $00, $00, $00, $1F, $FF, $FF, $FF, $FF, $FF, $82, $00, $00, $00 ; CPU:$F3B5 PRG:33B5 C0 00 00 00 00 00 1F FF FF FF FF FF 82 00 00 00
|
|
.byte $00, $00, $00, $03, $FF, $FF, $FF, $FF, $C0, $00, $00, $00, $00, $7F, $FF, $FF ; CPU:$F3C5 PRG:33C5 00 00 00 03 FF FF FF FF C0 00 00 00 00 7F FF FF
|
|
.byte $FF, $FE, $00, $00, $00, $00, $1E, $7B, $FF, $FF, $FF, $FF, $FF, $F8, $00, $BF ; CPU:$F3D5 PRG:33D5 FF FE 00 00 00 00 1E 7B FF FF FF FF FF F8 00 BF
|
|
.byte $FF, $FF, $C0, $00, $00, $00, $00, $07, $FF, $FF, $FF, $FF, $FF, $FE, $00, $00 ; CPU:$F3E5 PRG:33E5 FF FF C0 00 00 00 00 07 FF FF FF FF FF FE 00 00
|
|
.byte $00, $00, $00, $00, $01, $FF, $FF, $FF, $88, $20, $0D, $FF, $F0, $00, $00, $00 ; CPU:$F3F5 PRG:33F5 00 00 00 00 01 FF FF FF 88 20 0D FF F0 00 00 00
|
|
.byte $03, $FF, $FF, $FF, $FF, $FF, $FF, $F8, $00, $00, $00, $00, $00, $00, $FF, $FF ; CPU:$F405 PRG:3405 03 FF FF FF FF FF FF F8 00 00 00 00 00 00 FF FF
|
|
.byte $FF, $FF, $FF, $F8, $00, $00, $3F, $FF, $FF, $80, $00, $00, $00, $00, $00, $01 ; CPU:$F415 PRG:3415 FF FF FF F8 00 00 3F FF FF 80 00 00 00 00 00 01
|
|
.byte $FF, $FF, $FF, $FF, $FF, $FE, $00, $00, $00, $07, $FF, $FF, $FF, $FF, $FF, $00 ; CPU:$F425 PRG:3425 FF FF FF FF FF FE 00 00 00 07 FF FF FF FF FF 00
|
|
.byte $00, $00, $00, $00, $00, $01, $FF, $FF, $FF, $FF, $FF, $FF, $00, $00, $00, $00 ; CPU:$F435 PRG:3435 00 00 00 00 00 01 FF FF FF FF FF FF 00 00 00 00
|
|
.byte $00, $00, $07, $FF, $FF, $FF, $FF, $F6, $6F, $FF, $E0, $00, $00, $00, $00, $7F ; CPU:$F445 PRG:3445 00 00 07 FF FF FF FF F6 6F FF E0 00 00 00 00 7F
|
|
.byte $FF, $FF, $FE, $00, $00, $00, $00, $1F, $FF, $FF, $FF, $FF, $FE, $00, $00, $00 ; CPU:$F455 PRG:3455 FF FF FE 00 00 00 00 1F FF FF FF FF FE 00 00 00
|
|
.byte $00, $00, $06, $69, $43, $1A, $ED, $BF, $FF, $FF, $F0, $00, $00, $00, $00, $00 ; CPU:$F465 PRG:3465 00 00 06 69 43 1A ED BF FF FF F0 00 00 00 00 00
|
|
.byte $FF, $FF, $FF, $FF, $FF, $FF, $FF, $F0, $00, $00, $00, $00, $1F, $FF, $FF, $FF ; CPU:$F475 PRG:3475 FF FF FF FF FF FF FF F0 00 00 00 00 1F FF FF FF
|
|
.byte $FF, $C0, $00, $00, $00, $00, $00, $00, $17, $FF, $FF, $FF, $FF, $02, $29, $99 ; CPU:$F485 PRG:3485 FF C0 00 00 00 00 00 00 17 FF FF FF FF 02 29 99
|
|
.byte $DF, $FE, $A4, $26, $75, $AC, $61, $AF, $6D, $84, $44, $50, $9F, $BB, $79, $D9 ; CPU:$F495 PRG:3495 DF FE A4 26 75 AC 61 AF 6D 84 44 50 9F BB 79 D9
|
|
.byte $9B, $EC, $DB, $27, $FE, $00, $00, $00, $00, $07, $FF, $FF, $FF, $FC, $00, $00 ; CPU:$F4A5 PRG:34A5 9B EC DB 27 FE 00 00 00 00 07 FF FF FF FC 00 00
|
|
.byte $00, $00, $1F, $FF, $FF, $FF, $80, $00, $0F, $FF, $FF, $FF, $00, $00, $00, $00 ; CPU:$F4B5 PRG:34B5 00 00 1F FF FF FF 80 00 0F FF FF FF 00 00 00 00
|
|
.byte $1F, $FF, $FF, $80, $00, $00, $03, $DC, $DA, $FF, $FF, $FF, $FF, $00, $00, $00 ; CPU:$F4C5 PRG:34C5 1F FF FF 80 00 00 03 DC DA FF FF FF FF 00 00 00
|
|
.byte $00, $00, $00, $3F, $FF, $FF, $FF, $FF, $FF, $F0, $00, $00, $00, $1F, $FF, $FF ; CPU:$F4D5 PRG:34D5 00 00 00 3F FF FF FF FF FF F0 00 00 00 1F FF FF
|
|
.byte $FF, $FF, $F8, $00, $00, $00, $00, $00, $00, $5E, $FB, $EB, $AC, $C7, $EF, $BB ; CPU:$F4E5 PRG:34E5 FF FF F8 00 00 00 00 00 00 5E FB EB AC C7 EF BB
|
|
.byte $79, $BF, $FF, $E0, $00, $0F, $F8, $00, $00, $00, $FF, $FF, $FF, $FF, $FF, $FF ; CPU:$F4F5 PRG:34F5 79 BF FF E0 00 0F F8 00 00 00 FF FF FF FF FF FF
|
|
.byte $FC, $00, $00, $00, $00, $00, $00, $3F, $FF, $FF, $F7, $FF, $FF, $FF, $FA, $10 ; CPU:$F505 PRG:3505 FC 00 00 00 00 00 00 3F FF FF F7 FF FF FF FA 10
|
|
.byte $00, $00, $00, $00, $00, $00, $00, $00, $0F, $FC, $FB, $EE, $FF, $EA, $D9, $DF ; CPU:$F515 PRG:3515 00 00 00 00 00 00 00 00 0F FC FB EE FF EA D9 DF
|
|
.byte $CE, $7F, $FF, $FF, $80, $00, $00, $00, $00, $00, $1F, $FF, $FF, $FF, $FF, $FF ; CPU:$F525 PRG:3525 CE 7F FF FF 80 00 00 00 00 00 1F FF FF FF FF FF
|
|
.byte $FF, $E0, $00, $00, $00, $00, $00, $7F, $FF, $FF, $FF, $F8, $00, $00, $00, $00 ; CPU:$F535 PRG:3535 FF E0 00 00 00 00 00 7F FF FF FF F8 00 00 00 00
|
|
.byte $00, $00, $0F, $FF, $FF, $FF, $FF, $FF, $FF, $FC, $00, $00, $00, $00, $00, $00 ; CPU:$F545 PRG:3545 00 00 0F FF FF FF FF FF FF FC 00 00 00 00 00 00
|
|
.byte $00, $3F, $FF, $FF, $FF, $FF, $D3, $24, $25, $33, $CC, $C9, $20, $7F, $FF, $F0 ; CPU:$F555 PRG:3555 00 3F FF FF FF FF D3 24 25 33 CC C9 20 7F FF F0
|
|
.byte $00, $00, $00, $07, $FF, $FF, $FF, $FF, $00, $00, $00, $00, $0F, $FF, $FF, $FF ; CPU:$F565 PRG:3565 00 00 00 07 FF FF FF FF 00 00 00 00 0F FF FF FF
|
|
.byte $FF, $FF, $C6, $30, $40, $04, $20, $08, $61, $00, $00, $00, $07, $FF, $FF, $FF ; CPU:$F575 PRG:3575 FF FF C6 30 40 04 20 08 61 00 00 00 07 FF FF FF
|
|
.byte $FF, $FF, $FC, $00, $00, $00, $00, $00, $00, $00, $00, $01, $FF, $FF, $FF, $FF ; CPU:$F585 PRG:3585 FF FF FC 00 00 00 00 00 00 00 00 01 FF FF FF FF
|
|
.byte $FF, $FF, $FF, $FF, $FF, $FF, $62, $01, $00, $00, $80, $00, $00, $77, $5F, $FF ; CPU:$F595 PRG:3595 FF FF FF FF FF FF 62 01 00 00 80 00 00 77 5F FF
|
|
.byte $FD, $76, $EB, $5B, $7F, $FF, $FC, $00, $00, $00, $00, $00, $00, $3F, $FF, $FF ; CPU:$F5A5 PRG:35A5 FD 76 EB 5B 7F FF FC 00 00 00 00 00 00 3F FF FF
|
|
.byte $FF, $FF, $FF, $FF, $FF, $FF, $FF, $00, $00, $00, $00, $00, $00, $00, $00, $FF ; CPU:$F5B5 PRG:35B5 FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 FF
|
|
.byte $FF, $FF, $FF, $FF, $FF, $80, $00, $00, $00, $00, $00, $00, $1F, $FF, $FF, $FF ; CPU:$F5C5 PRG:35C5 FF FF FF FF FF 80 00 00 00 00 00 00 1F FF FF FF
|
|
.byte $FF, $00, $80, $00, $85, $11, $9E, $CC, $CD, $DB, $DF, $F6, $DF, $FF, $FF, $C0 ; CPU:$F5D5 PRG:35D5 FF 00 80 00 85 11 9E CC CD DB DF F6 DF FF FF C0
|
|
.byte $00, $00, $00, $00, $00, $0F, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $80, $00 ; CPU:$F5E5 PRG:35E5 00 00 00 00 00 0F FF FF FF FF FF FF FF FF 80 00
|
|
.byte $00, $00, $00, $00, $00, $00, $07, $FF, $FF, $FF, $FF, $FF, $FF, $F0, $00, $00 ; CPU:$F5F5 PRG:35F5 00 00 00 00 00 00 07 FF FF FF FF FF FF F0 00 00
|
|
.byte $00, $00, $00, $00, $00, $00, $1F, $FF, $FF, $C0, $00, $07, $FF, $FF, $FF, $FF ; CPU:$F605 PRG:3605 00 00 00 00 00 00 1F FF FF C0 00 07 FF FF FF FF
|
|
.byte $F0, $06, $31, $66, $6B, $FD, $FE, $D9, $40, $00, $03, $FF, $FF, $FF, $FF, $FF ; CPU:$F615 PRG:3615 F0 06 31 66 6B FD FE D9 40 00 03 FF FF FF FF FF
|
|
.byte $80, $00, $00, $00, $00, $00, $00, $00, $07, $FF, $FF, $FF, $FD, $F9, $88, $44 ; CPU:$F625 PRG:3625 80 00 00 00 00 00 00 00 07 FF FF FF FD F9 88 44
|
|
.byte $4A, $61, $4C, $CF, $6C, $E6, $7E, $EE, $69, $98, $4A, $CE, $B2, $61, $04, $66 ; CPU:$F635 PRG:3635 4A 61 4C CF 6C E6 7E EE 69 98 4A CE B2 61 04 66
|
|
.byte $64, $CE, $6D, $FF, $FF, $FE, $00, $00, $00, $00, $00, $01, $FF, $FF, $FF, $FF ; CPU:$F645 PRG:3645 64 CE 6D FF FF FE 00 00 00 00 00 01 FF FF FF FF
|
|
.byte $FE, $EF, $FF, $FF, $E6, $20, $80, $00, $00, $00, $00, $00, $00, $00, $01, $DB ; CPU:$F655 PRG:3655 FE EF FF FF E6 20 80 00 00 00 00 00 00 00 01 DB
|
|
.byte $EF, $FF, $FF, $FF, $FF, $F9, $8A, $99, $8A, $4C, $99, $9B, $39, $BF, $FF, $C0 ; CPU:$F665 PRG:3665 EF FF FF FF FF F9 8A 99 8A 4C 99 9B 39 BF FF C0
|
|
.byte $00, $00, $00, $00, $00, $03, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FC, $00, $00 ; CPU:$F675 PRG:3675 00 00 00 00 00 03 FF FF FF FF FF FF FF FC 00 00
|
|
.byte $00, $00, $00, $00, $00, $2F, $FF, $DF, $FF, $FF, $FF, $F0, $00, $00, $00, $00 ; CPU:$F685 PRG:3685 00 00 00 00 00 2F FF DF FF FF FF F0 00 00 00 00
|
|
.byte $00, $7F, $FF, $FF, $FF, $FF, $FF, $FF, $00, $00, $00, $00, $00, $3C, $A0, $00 ; CPU:$F695 PRG:3695 00 7F FF FF FF FF FF FF 00 00 00 00 00 3C A0 00
|
|
.byte $00, $00, $1B, $7F, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FC, $A0, $00, $00, $00 ; CPU:$F6A5 PRG:36A5 00 00 1B 7F FF FF FF FF FF FF FF FC A0 00 00 00
|
|
.byte $FF, $FF, $FE, $61, $00, $00, $00, $00, $00, $00, $00, $3F, $FF, $FF, $FF, $FF ; CPU:$F6B5 PRG:36B5 FF FF FE 61 00 00 00 00 00 00 00 3F FF FF FF FF
|
|
.byte $FB, $DF, $FF, $FF, $FF, $CC, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; CPU:$F6C5 PRG:36C5 FB DF FF FF FF CC 00 00 00 00 00 00 00 00 00 00
|
|
.byte $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $F8, $00, $00, $00, $00, $00, $00 ; CPU:$F6D5 PRG:36D5 FF FF FF FF FF FF FF FF FF F8 00 00 00 00 00 00
|
|
.byte $41, $AD, $26, $EF, $FF, $FF, $FF, $FF, $FF, $E0, $00, $00, $00, $00, $00, $00 ; CPU:$F6E5 PRG:36E5 41 AD 26 EF FF FF FF FF FF E0 00 00 00 00 00 00
|
|
.byte $01, $5A, $FF, $FF, $6F, $FF, $FF, $FF, $00, $00, $00, $05, $FF, $FF, $FF, $FF ; CPU:$F6F5 PRG:36F5 01 5A FF FF 6F FF FF FF 00 00 00 05 FF FF FF FF
|
|
.byte $FF, $FA, $28, $88, $10, $40, $00, $02, $10, $94, $66, $73, $36, $F7, $FF, $FF ; CPU:$F705 PRG:3705 FF FA 28 88 10 40 00 02 10 94 66 73 36 F7 FF FF
|
|
.byte $FC, $00, $00, $00, $00, $FF, $FF, $FF, $FF, $FF, $F8, $00, $00, $00, $0F, $B1 ; CPU:$F715 PRG:3715 FC 00 00 00 00 FF FF FF FF FF F8 00 00 00 0F B1
|
|
.byte $44, $10, $00, $00, $65, $33, $DF, $FF, $FF, $F9, $9E, $FF, $FF, $FF, $FF, $FA ; CPU:$F725 PRG:3725 44 10 00 00 65 33 DF FF FF F9 9E FF FF FF FF FA
|
|
.byte $E4, $00, $00, $00, $00, $00, $00, $00, $00, $01, $FF, $FF, $FF, $FF, $FF, $FF ; CPU:$F735 PRG:3735 E4 00 00 00 00 00 00 00 00 01 FF FF FF FF FF FF
|
|
.byte $FF, $80, $00, $00, $00, $02, $FB, $DD, $B6, $B7, $77, $DA, $28, $99, $4A, $BF ; CPU:$F745 PRG:3745 FF 80 00 00 00 02 FB DD B6 B7 77 DA 28 99 4A BF
|
|
.byte $FF, $C8, $00, $00, $00, $00, $00, $1F, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $00 ; CPU:$F755 PRG:3755 FF C8 00 00 00 00 00 1F FF FF FF FF FF FF FF 00
|
|
.byte $00, $00, $00, $00, $00, $00, $0F, $FF, $FF, $FF, $FF, $FF, $FF, $C0, $00, $00 ; CPU:$F765 PRG:3765 00 00 00 00 00 00 0F FF FF FF FF FF FF C0 00 00
|
|
.byte $00, $00, $00, $00, $00, $20, $45, $6D, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF ; CPU:$F775 PRG:3775 00 00 00 00 00 20 45 6D FF FF FF FF FF FF FF FF
|
|
.byte $F4, $00, $00, $07, $BD, $FF, $BC, $C4, $80, $40, $00, $00, $00, $00, $06, $32 ; CPU:$F785 PRG:3785 F4 00 00 07 BD FF BC C4 80 40 00 00 00 00 06 32
|
|
.byte $EE, $CE, $B6, $DF, $7B, $BF, $BF, $F7, $DC, $EF, $FF, $F2, $00, $00, $00, $00 ; CPU:$F795 PRG:3795 EE CE B6 DF 7B BF BF F7 DC EF FF F2 00 00 00 00
|
|
.byte $00, $00, $0B, $FF, $FF, $FF, $FF, $FF, $FC, $00, $8F, $7F, $76, $CE, $52, $90 ; CPU:$F7A5 PRG:37A5 00 00 0B FF FF FF FF FF FC 00 8F 7F 76 CE 52 90
|
|
.byte $00, $00, $00, $7B, $62, $00, $00, $00, $00, $32, $23, $7F, $FF, $FF, $FF, $FF ; CPU:$F7B5 PRG:37B5 00 00 00 7B 62 00 00 00 00 32 23 7F FF FF FF FF
|
|
.byte $FF, $FF, $FF, $FF, $00, $00, $00, $00, $00, $00, $02, $6F, $FF, $FE, $EF, $32 ; CPU:$F7C5 PRG:37C5 FF FF FF FF 00 00 00 00 00 00 02 6F FF FE EF 32
|
|
.byte $98, $8C, $25, $33, $5E, $F7, $BF, $F5, $99, $DF, $FF, $FE, $06, $6C, $48, $C4 ; CPU:$F7D5 PRG:37D5 98 8C 25 33 5E F7 BF F5 99 DF FF FE 06 6C 48 C4
|
|
.byte $89, $11, $04, $45, $14, $33, $BC, $88, $00, $00, $00, $00, $26, $6B, $5D, $FF ; CPU:$F7E5 PRG:37E5 89 11 04 45 14 33 BC 88 00 00 00 00 26 6B 5D FF
|
|
.byte $FF, $FF, $FF, $FF, $FF, $FF, $F0, $04, $00, $00, $00, $08, $88, $C6, $66, $D6 ; CPU:$F7F5 PRG:37F5 FF FF FF FF FF FF F0 04 00 00 00 08 88 C6 66 D6
|
|
.byte $DD, $BB, $33, $67, $3B, $BB, $FF, $FD, $0A, $64, $90, $01, $00, $00, $8C, $AB ; CPU:$F805 PRG:3805 DD BB 33 67 3B BB FF FD 0A 64 90 01 00 00 8C AB
|
|
.byte $BB, $FF, $FF, $FB, $FF, $5D, $CC, $CA, $53, $33, $14, $21, $08, $84, $11, $09 ; CPU:$F815 PRG:3815 BB FF FF FB FF 5D CC CA 53 33 14 21 08 84 11 09
|
|
.byte $14, $45, $22, $4C, $66, $6B, $32, $10, $93, $BF, $FF, $FF, $FF, $FF, $FF, $C0 ; CPU:$F825 PRG:3825 14 45 22 4C 66 6B 32 10 93 BF FF FF FF FF FF C0
|
|
.byte $00, $00, $00, $00, $00, $BF, $FB, $F7, $77, $FF, $E4, $20, $42, $4C, $CD, $67 ; CPU:$F835 PRG:3835 00 00 00 00 00 BF FB F7 77 FF E4 20 42 4C CD 67
|
|
.byte $75, $EE, $CE, $7A, $D9, $9D, $B3, $31, $84, $82, $44, $8A, $65, $55, $9D, $B3 ; CPU:$F845 PRG:3845 75 EE CE 7A D9 9D B3 31 84 82 44 8A 65 55 9D B3
|
|
.byte $33, $5F, $B6, $DC, $A0, $00, $00, $00, $00, $03, $FF, $FF, $FF, $FF, $FF, $FF ; CPU:$F855 PRG:3855 33 5F B6 DC A0 00 00 00 00 03 FF FF FF FF FF FF
|
|
.byte $F9, $02, $00, $00, $00, $32, $88, $00, $12, $99, $9C, $EE, $F7, $FF, $FF, $FF ; CPU:$F865 PRG:3865 F9 02 00 00 00 32 88 00 12 99 9C EE F7 FF FF FF
|
|
.byte $84, $00, $00, $04, $50, $8A, $FF, $FF, $FF, $FF, $FC, $00, $86, $7F, $FF, $FF ; CPU:$F875 PRG:3875 84 00 00 04 50 8A FF FF FF FF FC 00 86 7F FF FF
|
|
.byte $E0, $00, $00, $00, $00, $3F, $BF, $FB, $AE, $D9, $99, $D7, $28, $00, $00, $00 ; CPU:$F885 PRG:3885 E0 00 00 00 00 3F BF FB AE D9 99 D7 28 00 00 00
|
|
.byte $00, $00, $00, $7D, $FF, $FF, $FF, $FF, $FF, $FF, $E8, $48, $A4, $C6, $4D, $62 ; CPU:$F895 PRG:3895 00 00 00 7D FF FF FF FF FF FF E8 48 A4 C6 4D 62
|
|
.byte $88, $45, $5F, $6C, $80, $00, $00, $01, $19, $9A, $DB, $BF, $FF, $FE, $FB, $33 ; CPU:$F8A5 PRG:38A5 88 45 5F 6C 80 00 00 01 19 9A DB BF FF FE FB 33
|
|
.byte $5E, $FF, $BF, $76, $DA, $E6, $64, $D6, $00, $00, $00, $00, $00, $00, $DB, $33 ; CPU:$F8B5 PRG:38B5 5E FF BF 76 DA E6 64 D6 00 00 00 00 00 00 DB 33
|
|
.byte $14, $22, $8C, $44, $18, $EF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $F0, $00, $00 ; CPU:$F8C5 PRG:38C5 14 22 8C 44 18 EF FF FF FF FF FF FF FF F0 00 00
|
|
.byte $00, $00, $00, $CE, $75, $9D, $9C, $E7, $99, $99, $9A, $6A, $64, $CC, $CC, $CC ; CPU:$F8D5 PRG:38D5 00 00 00 CE 75 9D 9C E7 99 99 9A 6A 64 CC CC CC
|
|
.byte $CD, $6B, $2A, $67, $35, $9B, $33, $19, $8C, $CC, $CC, $CA, $67, $7F, $F2, $00 ; CPU:$F8E5 PRG:38E5 CD 6B 2A 67 35 9B 33 19 8C CC CC CA 67 7F F2 00
|
|
.byte $02, $19, $DB, $B7, $5D, $FF, $FF, $FC, $20, $00, $00, $00, $00, $17, $F6, $33 ; CPU:$F8F5 PRG:38F5 02 19 DB B7 5D FF FF FC 20 00 00 00 00 17 F6 33
|
|
.byte $3E, $FF, $FF, $FF, $FE, $F5, $8D, $9F, $4C, $00, $00, $00, $00, $00, $00, $00 ; CPU:$F905 PRG:3905 3E FF FF FF FE F5 8D 9F 4C 00 00 00 00 00 00 00
|
|
.byte $3F, $FF, $FF, $FF, $FF, $FF, $FF, $F4, $80, $00, $00, $00, $00, $7F, $FF, $E6 ; CPU:$F915 PRG:3915 3F FF FF FF FF FF FF F4 80 00 00 00 00 7F FF E6
|
|
.byte $50, $80, $00, $19, $FF, $FF, $FF, $FF, $FF, $EB, $33, $12, $00, $00, $81, $10 ; CPU:$F925 PRG:3925 50 80 00 19 FF FF FF FF FF EB 33 12 00 00 81 10
|
|
.byte $22, $33, $B5, $22, $12, $53, $5B, $5D, $7B, $F7, $EE, $BA, $CC, $CC, $CD, $99 ; CPU:$F935 PRG:3935 22 33 B5 22 12 53 5B 5D 7B F7 EE BA CC CC CD 99
|
|
.byte $98, $C6, $66, $71, $98, $88, $91, $8C, $4C, $FB, $52, $42, $52, $99, $DD, $D9 ; CPU:$F945 PRG:3945 98 C6 66 71 98 88 91 8C 4C FB 52 42 52 99 DD D9
|
|
.byte $9D, $BF, $BF, $CC, $44, $01, $01, $00, $00, $14, $EE, $FF, $FF, $FF, $FF, $FD ; CPU:$F955 PRG:3955 9D BF BF CC 44 01 01 00 00 14 EE FF FF FF FF FD
|
|
.byte $77, $7E, $42, $00, $40, $00, $00, $00, $00, $0A, $33, $3D, $FF, $FF, $FF, $FF ; CPU:$F965 PRG:3965 77 7E 42 00 40 00 00 00 00 0A 33 3D FF FF FF FF
|
|
.byte $FF, $FE, $66, $62, $22, $08, $41, $02, $13, $31, $84, $10, $09, $AF, $7B, $5C ; CPU:$F975 PRG:3975 FF FE 66 62 22 08 41 02 13 31 84 10 09 AF 7B 5C
|
|
.byte $CC, $D6, $73, $39, $94, $B3, $BF, $FF, $FF, $FF, $EE, $D6, $66, $28, $A2, $08 ; CPU:$F985 PRG:3985 CC D6 73 39 94 B3 BF FF FF FF EE D6 66 28 A2 08
|
|
.byte $40, $10, $CA, $40, $00, $00, $10, $50, $CC, $CD, $BB, $F7, $F7, $FD, $FF, $7E ; CPU:$F995 PRG:3995 40 10 CA 40 00 00 10 50 CC CD BB F7 F7 FD FF 7E
|
|
.byte $FA, $D5, $98, $C5, $33, $67, $AE, $75, $99, $4A, $10, $40, $81, $01, $00, $90 ; CPU:$F9A5 PRG:39A5 FA D5 98 C5 33 67 AE 75 99 4A 10 40 81 01 00 90
|
|
.byte $51, $8C, $CD, $EF, $F5, $A9, $45, $12, $94, $CC, $C9, $9E, $F7, $FF, $FF, $FF ; CPU:$F9B5 PRG:39B5 51 8C CD EF F5 A9 45 12 94 CC C9 9E F7 FF FF FF
|
|
.byte $FF, $79, $D9, $CC, $E5, $48, $88, $84, $04, $08, $21, $11, $14, $E3, $1C, $D3 ; CPU:$F9C5 PRG:39C5 FF 79 D9 CC E5 48 88 84 04 08 21 11 14 E3 1C D3
|
|
.byte $35, $99, $91, $00, $09, $36, $FF, $FF, $FF, $FD, $6B, $32, $28, $00, $81, $29 ; CPU:$F9D5 PRG:39D5 35 99 91 00 09 36 FF FF FF FD 6B 32 28 00 81 29
|
|
.byte $B7, $7B, $F7, $EB, $B5, $9B, $19, $4A, $24, $44, $42, $25, $59, $98, $81, $20 ; CPU:$F9E5 PRG:39E5 B7 7B F7 EB B5 9B 19 4A 24 44 42 25 59 98 81 20
|
|
.byte $24, $46, $33, $33, $9E, $EE, $FB, $F7, $FF, $BE, $D9, $9C, $EF, $75, $ED, $EE ; CPU:$F9F5 PRG:39F5 24 46 33 33 9E EE FB F7 FF BE D9 9C EF 75 ED EE
|
|
.byte $D9, $84, $41, $04, $00, $81, $01, $09, $11, $14, $4C, $6A, $6B, $39, $CF, $BA ; CPU:$FA05 PRG:3A05 D9 84 41 04 00 81 01 09 11 14 4C 6A 6B 39 CF BA
|
|
.byte $E6, $B7, $7F, $DF, $66, $22, $00, $04, $65, $D7, $BF, $BE, $FF, $BD, $CE, $66 ; CPU:$FA15 PRG:3A15 E6 B7 7F DF 66 22 00 04 65 D7 BF BE FF BD CE 66
|
|
.byte $62, $94, $91, $42, $93, $AC, $C4, $00, $40, $20, $04, $08, $CD, $7F, $FF, $FF ; CPU:$FA25 PRG:3A25 62 94 91 42 93 AC C4 00 40 20 04 08 CD 7F FF FF
|
|
.byte $F7, $FB, $EF, $76, $A4, $88, $84, $11, $23, $18, $C6, $62, $45, $18, $A4, $CC ; CPU:$FA35 PRG:3A35 F7 FB EF 76 A4 88 84 11 23 18 C6 62 45 18 A4 CC
|
|
.byte $D6, $77, $BE, $D9, $89, $21, $08, $A2, $98, $DA, $EB, $DB, $BB, $EF, $DE, $ED ; CPU:$FA45 PRG:3A45 D6 77 BE D9 89 21 08 A2 98 DA EB DB BB EF DE ED
|
|
.byte $99, $8A, $6B, $5B, $5D, $D6, $CC, $CC, $E7, $28, $00, $00, $00, $00, $00, $99 ; CPU:$FA55 PRG:3A55 99 8A 6B 5B 5D D6 CC CC E7 28 00 00 00 00 00 99
|
|
.byte $33, $1C, $DB, $DE, $F7, $7F, $BF, $CE, $75, $9A, $CD, $93, $08, $A6, $67, $36 ; CPU:$FA65 PRG:3A65 33 1C DB DE F7 7F BF CE 75 9A CD 93 08 A6 67 36
|
|
.byte $B6, $B6, $B3, $9C, $D9, $9B, $24, $10, $21, $02, $11, $46, $4C, $CD, $9C, $D9 ; CPU:$FA75 PRG:3A75 B6 B6 B3 9C D9 9B 24 10 21 02 11 46 4C CD 9C D9
|
|
.byte $D9, $CE, $BD, $FB, $B9, $94, $24, $22, $46, $32, $66, $6D, $75, $ED, $F7, $76 ; CPU:$FA85 PRG:3A85 D9 CE BD FB B9 94 24 22 46 32 66 6D 75 ED F7 76
|
|
.byte $CD, $B3, $33, $9A, $DB, $5A, $CD, $67, $30, $84, $21, $11, $04, $22, $10, $A3 ; CPU:$FA95 PRG:3A95 CD B3 33 9A DB 5A CD 67 30 84 21 11 04 22 10 A3
|
|
.byte $18, $CC, $DA, $D9, $92, $26, $67, $66, $67, $39, $D6, $EB, $D7, $BB, $BB, $9D ; CPU:$FAA5 PRG:3AA5 18 CC DA D9 92 26 67 66 67 39 D6 EB D7 BB BB 9D
|
|
.byte $99, $99, $99, $9B, $32, $61, $49, $9D, $B3, $8C, $21, $11, $10, $51, $43, $1B ; CPU:$FAB5 PRG:3AB5 99 99 99 9B 32 61 49 9D B3 8C 21 11 10 51 43 1B
|
|
.byte $3D, $FB, $FE, $FD, $EE, $E7, $66, $66, $29, $46, $22, $89, $14, $28, $4A, $14 ; CPU:$FAC5 PRG:3AC5 3D FB FE FD EE E7 66 66 29 46 22 89 14 28 4A 14
|
|
.byte $A6, $53, $3B, $6C, $CC, $44, $08, $46, $67, $5F, $BF, $DF, $77, $BE, $FE, $E6 ; CPU:$FAD5 PRG:3AD5 A6 53 3B 6C CC 44 08 46 67 5F BF DF 77 BE FE E6
|
|
.byte $62, $28, $11, $08, $84, $82, $26, $6B, $AF, $7D, $FE, $DD, $66, $66, $33, $18 ; CPU:$FAE5 PRG:3AE5 62 28 11 08 84 82 26 6B AF 7D FE DD 66 66 33 18
|
|
.byte $C5, $28, $C5, $31, $4C, $65, $25, $32, $A9, $99, $32, $66, $66, $66, $B3, $D6 ; CPU:$FAF5 PRG:3AF5 C5 28 C5 31 4C 65 25 32 A9 99 32 66 66 66 B3 D6
|
|
.byte $CC, $E7, $6E, $51, $22, $53, $67, $77, $7D, $73, $4A, $22, $96, $6C, $CC, $CA ; CPU:$FB05 PRG:3B05 CC E7 6E 51 22 53 67 77 7D 73 4A 22 96 6C CC CA
|
|
.byte $66, $33, $2C, $CC, $CC, $E6, $6B, $35, $99, $9A, $CB, $33, $32, $51, $24, $CB ; CPU:$FB15 PRG:3B15 66 33 2C CC CC E6 6B 35 99 9A CB 33 32 51 24 CB
|
|
.byte $39, $D7, $39, $CC, $CC, $C6, $63, $0A, $48, $88, $93, $18, $93, $18, $CC, $CE ; CPU:$FB25 PRG:3B25 39 D7 39 CC CC C6 63 0A 48 88 93 18 93 18 CC CE
|
|
.byte $73, $9B, $59, $CD, $75, $DD, $EE, $B3, $19, $66, $73, $6B, $67, $59, $CE, $66 ; CPU:$FB35 PRG:3B35 73 9B 59 CD 75 DD EE B3 19 66 73 6B 67 59 CE 66
|
|
.byte $66, $E7, $9A, $62, $10, $01, $04, $67, $6D, $99, $33, $33, $9D, $AE, $76, $B6 ; CPU:$FB45 PRG:3B45 66 E7 9A 62 10 01 04 67 6D 99 33 33 9D AE 76 B6
|
|
.byte $AC, $CC, $CE, $6C, $CA, $22, $08, $10, $44, $49, $12, $93, $3A, $FF, $7F, $AD ; CPU:$FB55 PRG:3B55 AC CC CE 6C CA 22 08 10 44 49 12 93 3A FF 7F AD
|
|
.byte $5A, $DA, $EB, $6B, $39, $CC, $D9, $99, $93, $26, $29, $29, $31, $46, $31, $94 ; CPU:$FB65 PRG:3B65 5A DA EB 6B 39 CC D9 99 93 26 29 29 31 46 31 94
|
|
.byte $CC, $CC, $C6, $53, $99, $99, $AB, $35, $6C, $CE, $66, $CD, $9A, $E6, $CD, $99 ; CPU:$FB75 PRG:3B75 CC CC C6 53 99 99 AB 35 6C CE 66 CD 9A E6 CD 99
|
|
.byte $CD, $99, $B2, $B2, $99, $4C, $66, $31, $98, $CC, $CC, $CD, $99, $98, $D3, $58 ; CPU:$FB85 PRG:3B85 CD 99 B2 B2 99 4C 66 31 98 CC CC CD 99 98 D3 58
|
|
.byte $CA, $99, $9A, $DB, $29, $49, $14, $45, $26, $33, $35, $9B, $39, $B5, $DA, $DA ; CPU:$FB95 PRG:3B95 CA 99 9A DB 29 49 14 45 26 33 35 9B 39 B5 DA DA
|
|
.byte $EC, $E6, $CD, $66, $CC, $CC, $C9, $99, $8C, $99, $93, $18, $C9, $8A, $22, $94 ; CPU:$FBA5 PRG:3BA5 EC E6 CD 66 CC CC C9 99 8C 99 93 18 C9 8A 22 94
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|
.byte $CD, $75, $EF, $75, $9A, $51, $14, $44, $89, $25, $29, $AC, $D9, $CC, $E6, $D6 ; CPU:$FBB5 PRG:3BB5 CD 75 EF 75 9A 51 14 44 89 25 29 AC D9 CC E6 D6
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|
.byte $B9, $DB, $5C, $EB, $33, $33, $39, $D7, $6B, $9D, $9C, $E6, $66, $31, $8A, $46 ; CPU:$FBC5 PRG:3BC5 B9 DB 5C EB 33 33 39 D7 6B 9D 9C E6 66 31 8A 46
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|
.byte $14, $48, $A2, $8C, $62, $63, $26, $66, $66, $D7, $66, $32, $64, $CC, $CF, $39 ; CPU:$FBD5 PRG:3BD5 14 48 A2 8C 62 63 26 66 66 D7 66 32 64 CC CF 39
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|
.byte $CE, $76, $73, $AD, $6B, $39, $B3, $33, $32, $66, $4C, $C9, $98, $CA, $63, $18 ; CPU:$FBE5 PRG:3BE5 CE 76 73 AD 6B 39 B3 33 32 66 4C C9 98 CA 63 18
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|
.byte $CA, $66, $53, $33, $31, $99, $8C, $CC, $CC, $D6, $66, $B3, $33, $33, $39, $B3 ; CPU:$FBF5 PRG:3BF5 CA 66 53 33 31 99 8C CC CC D6 66 B3 33 33 39 B3
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|
.byte $99, $B3, $94, $99, $32, $66, $29, $8C, $67, $5B, $5C, $CC, $CC, $DA, $E7, $5A ; CPU:$FC05 PRG:3C05 99 B3 94 99 32 66 29 8C 67 5B 5C CC CC DA E7 5A
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|
.byte $CC, $D6, $66, $63, $26, $31, $26, $56, $67, $3A, $DA, $CE, $66, $66, $4C, $63 ; CPU:$FC15 PRG:3C15 CC D6 66 63 26 31 26 56 67 3A DA CE 66 66 4C 63
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|
.byte $18, $C6, $29, $46, $66, $33, $31, $99, $99, $CE, $73, $31, $85, $14, $CC, $D6 ; CPU:$FC25 PRG:3C25 18 C6 29 46 66 33 31 99 99 CE 73 31 85 14 CC D6
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|
.byte $EB, $AE, $EB, $D7, $6D, $6B, $36, $6B, $59, $89, $44, $93, $18, $CA, $52, $91 ; CPU:$FC35 PRG:3C35 EB AE EB D7 6D 6B 36 6B 59 89 44 93 18 CA 52 91
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.byte $93, $32, $C6, $69, $9A, $CC, $D9, $9A, $CC, $D9, $99, $66, $73, $AD, $6E, $B9 ; CPU:$FC45 PRG:3C45 93 32 C6 69 9A CC D9 9A CC D9 99 66 73 AD 6E B9
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|
.byte $CC, $C6, $24, $44, $44, $89, $28, $A3, $13, $33, $5B, $AE, $EE, $B5, $CE, $75 ; CPU:$FC55 PRG:3C55 CC C6 24 44 44 89 28 A3 13 33 5B AE EE B5 CE 75
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|
.byte $9B, $33, $8C, $CC, $B1, $8C, $CC, $66, $4C, $CA, $99, $99, $96, $66, $66, $66 ; CPU:$FC65 PRG:3C65 9B 33 8C CC B1 8C CC 66 4C CA 99 99 96 66 66 66
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|
.byte $6C, $9C, $CC, $CC, $E6, $CE, $73, $32, $52, $63, $4E, $66, $B3, $B7, $5C, $CC ; CPU:$FC75 PRG:3C75 6C 9C CC CC E6 CE 73 32 52 63 4E 66 B3 B7 5C CC
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|
.byte $C6, $18, $A2, $52, $99, $CD, $5A, $E7, $6D, $98, $C9, $93, $26, $6B, $36, $63 ; CPU:$FC85 PRG:3C85 C6 18 A2 52 99 CD 5A E7 6D 98 C9 93 26 6B 36 63
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.byte $18, $92, $28, $8A, $66, $4C, $CA, $73, $39, $D7, $3D, $75, $B6, $73, $33, $36 ; CPU:$FC95 PRG:3C95 18 92 28 8A 66 4C CA 73 39 D7 3D 75 B6 73 33 36
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|
.byte $32, $98, $CC, $66, $66, $65, $33, $32, $99, $33, $33, $33, $33, $99, $9C, $CC ; CPU:$FCA5 PRG:3CA5 32 98 CC 66 66 65 33 32 99 33 33 33 33 99 9C CC
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|
.byte $D9, $66, $D6, $CC, $C9, $8C, $A6, $66, $6B, $35, $9B, $35, $9D, $63, $32, $95 ; CPU:$FCB5 PRG:3CB5 D9 66 D6 CC C9 8C A6 66 6B 35 9B 35 9D 63 32 95
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|
.byte $33, $33, $33, $33, $32, $66, $53, $4C, $A9, $99, $99, $99, $8C, $4A, $63, $35 ; CPU:$FCC5 PRG:3CC5 33 33 33 33 32 66 53 4C A9 99 99 99 8C 4A 63 35
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|
.byte $9B, $39, $CC, $C6, $63, $32, $66, $66, $59, $99, $9A, $73, $9D, $66, $67, $39 ; CPU:$FCD5 PRG:3CD5 9B 39 CC C6 63 32 66 66 59 99 9A 73 9D 66 67 39
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|
.byte $CE, $73, $32, $63, $19, $99, $9B, $35, $9A, $D9, $CC, $C6, $14, $8A, $28, $C5 ; CPU:$FCE5 PRG:3CE5 CE 73 32 63 19 99 9B 35 9A D9 CC C6 14 8A 28 C5
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|
.byte $26, $33, $19, $99, $9B, $33, $59, $B3, $AC, $E6, $CE, $67, $33, $99, $B3, $39 ; CPU:$FCF5 PRG:3CF5 26 33 19 99 9B 33 59 B3 AC E6 CE 67 33 99 B3 39
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.byte $99, $99, $99, $99, $94, $C5, $31, $AC, $CE, $6C, $CE, $66, $33, $19, $94, $C9 ; CPU:$FD05 PRG:3D05 99 99 99 99 94 C5 31 AC CE 6C CE 66 33 19 94 C9
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|
.byte $8C, $65, $29, $8C, $C6, $66, $73, $66, $65, $25, $33, $33, $39, $AD, $D6, $D6 ; CPU:$FD15 PRG:3D15 8C 65 29 8C C6 66 73 66 65 25 33 33 39 AD D6 D6
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|
.byte $B3, $59, $99, $99, $9B, $33, $33, $39, $9C, $E6, $C9, $9A, $66, $66, $26, $32 ; CPU:$FD25 PRG:3D25 B3 59 99 99 9B 33 33 39 9C E6 C9 9A 66 66 26 32
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|
.byte $B2, $66, $9C, $CC, $CC, $CC, $C9, $93, $29, $8C, $A6, $66, $62, $51, $84, $94 ; CPU:$FD35 PRG:3D35 B2 66 9C CC CC CC C9 93 29 8C A6 66 62 51 84 94
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|
.byte $A6, $66, $CE, $75, $B3, $9E, $73, $9C, $E7, $33, $99, $AC, $CB, $33, $33, $33 ; CPU:$FD45 PRG:3D45 A6 66 CE 75 B3 9E 73 9C E7 33 99 AC CB 33 33 33
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.byte $33, $33, $33, $26, $66, $59, $99, $8C, $CC, $C9, $99, $99, $99, $99, $99, $99 ; CPU:$FD55 PRG:3D55 33 33 33 26 66 59 99 8C CC C9 99 99 99 99 99 99
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|
.byte $9A, $B3, $33, $33, $33, $33, $33, $66, $66, $64, $A6, $33, $33, $33, $26, $55 ; CPU:$FD65 PRG:3D65 9A B3 33 33 33 33 33 66 66 64 A6 33 33 33 26 55
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|
.byte $33, $33, $9C, $E6, $B3, $9A, $AC, $CC, $C6, $66, $66, $69, $99, $99, $99, $98 ; CPU:$FD75 PRG:3D75 33 33 9C E6 B3 9A AC CC C6 66 66 69 99 99 99 98
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|
.byte $CC, $C6, $63, $19, $99, $99, $4C, $CC, $CA, $99, $99, $9C, $CD, $54, $CC, $CC ; CPU:$FD85 PRG:3D85 CC C6 63 19 99 99 4C CC CA 99 99 9C CD 54 CC CC
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|
.byte $CC, $E6, $73, $39, $AC, $E6, $66, $66, $53, $29, $99, $4C, $CC, $CC, $CE, $66 ; CPU:$FD95 PRG:3D95 CC E6 73 39 AC E6 66 66 53 29 99 4C CC CC CE 66
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|
.byte $73, $35, $99, $CC, $CC, $CE, $67, $33, $19, $92, $A4, $CC, $6C, $CE, $73, $59 ; CPU:$FDA5 PRG:3DA5 73 35 99 CC CC CE 67 33 19 92 A4 CC 6C CE 73 59
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|
.byte $31, $88, $A4, $65, $33, $35, $9B, $33, $32, $6B, $33, $31, $93, $26, $B3, $36 ; CPU:$FDB5 PRG:3DB5 31 88 A4 65 33 35 9B 33 32 6B 33 31 93 26 B3 36
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|
.byte $67, $3B, $35, $99, $98, $CC, $A6, $55, $99, $CD, $6B, $59, $CC, $CD, $4E, $66 ; CPU:$FDC5 PRG:3DC5 67 3B 35 99 98 CC A6 55 99 CD 6B 59 CC CD 4E 66
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|
.byte $63, $31, $99, $AC, $CC, $E6, $66, $73, $33, $31, $99, $4C, $A6, $32, $99, $4C ; CPU:$FDD5 PRG:3DD5 63 31 99 AC CC E6 66 73 33 31 99 4C A6 32 99 4C
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|
.byte $99, $8C, $E5, $4C, $C9, $8C, $CC, $CD, $59, $99, $99, $99, $CC, $E6, $73, $39 ; CPU:$FDE5 PRG:3DE5 99 8C E5 4C C9 8C CC CD 59 99 99 99 CC E6 73 39
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|
.byte $9C, $E7, $33, $99, $4C, $99, $98, $CC, $99, $33, $33, $56, $67, $33, $59, $9B ; CPU:$FDF5 PRG:3DF5 9C E7 33 99 4C 99 98 CC 99 33 33 56 67 33 59 9B
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.byte $31, $A9, $99, $94, $CC, $CC, $66, $66, $53, $2A, $66, $4D, $33, $35, $59, $4C ; CPU:$FE05 PRG:3E05 31 A9 99 94 CC CC 66 66 53 2A 66 4D 33 35 59 4C
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.byte $CC, $CC, $D9, $99, $9A, $67, $36, $6C, $CC, $CC, $CA, $65, $4C, $CC, $CC, $CC ; CPU:$FE15 PRG:3E15 CC CC D9 99 9A 67 36 6C CC CC CA 65 4C CC CC CC
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.byte $CD, $99, $AC, $D9, $9B, $33, $39, $99, $9B, $2A, $66, $54, $CC, $C6, $67, $33 ; CPU:$FE25 PRG:3E25 CD 99 AC D9 9B 33 39 99 9B 2A 66 54 CC C6 67 33
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.byte $33, $33, $33, $19, $4C, $99, $4C, $94, $C6, $64, $CC, $66, $66, $55, $66, $35 ; CPU:$FE35 PRG:3E35 33 33 33 19 4C 99 4C 94 C6 64 CC 66 66 55 66 35
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.byte $99, $9A, $CC, $E7, $36, $67, $35, $66, $6B, $33, $66, $73, $5A, $72, $66, $59 ; CPU:$FE45 PRG:3E45 99 9A CC E7 36 67 35 66 6B 33 66 73 5A 72 66 59
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.byte $99, $9C, $E6, $63, $31, $8C, $C6, $33, $29, $99, $99, $54, $CC, $CC, $D9, $99 ; CPU:$FE55 PRG:3E55 99 9C E6 63 31 8C C6 33 29 99 99 54 CC CC D9 99
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.byte $99, $99, $99, $9A, $72, $CC, $CC, $CC, $A9, $9B, $26, $63, $14, $C6, $63, $33 ; CPU:$FE65 PRG:3E65 99 99 99 9A 72 CC CC CC A9 9B 26 63 14 C6 63 33
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.byte $33, $33, $33, $99, $9C, $D3, $33, $19, $93, $9A, $B3, $59, $99, $99, $9C, $CE ; CPU:$FE75 PRG:3E75 33 33 33 99 9C D3 33 19 93 9A B3 59 99 99 9C CE
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.byte $66, $67, $33, $59, $9C, $CC, $CE, $66, $66, $6B, $33, $29, $94, $CC, $CC, $D6 ; CPU:$FE85 PRG:3E85 66 67 33 59 9C CC CE 66 66 6B 33 29 94 CC CC D6
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.byte $66, $66, $66, $63, $33, $19, $32, $99, $4C, $66, $32, $99, $99, $8C, $CC, $CC ; CPU:$FE95 PRG:3E95 66 66 66 63 33 19 32 99 4C 66 32 99 99 8C CC CC
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.byte $CC, $CC, $CD, $99, $AC, $E6, $CC, $CC, $AA, $CC, $E6, $6C, $CE, $67, $34, $E5 ; CPU:$FEA5 PRG:3EA5 CC CC CD 99 AC E6 CC CC AA CC E6 6C CE 67 34 E5
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.byte $99, $99, $99, $99, $99, $99, $93, $33, $33, $33, $26, $31, $8C, $C6, $66, $66 ; CPU:$FEB5 PRG:3EB5 99 99 99 99 99 99 93 33 33 33 26 31 8C C6 66 66
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.byte $73, $33, $33, $29, $99, $99, $99, $CB, $33, $33, $33, $66, $66, $65, $29, $96 ; CPU:$FEC5 PRG:3EC5 73 33 33 29 99 99 99 CB 33 33 33 66 66 65 29 96
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.byte $33, $99, $99, $9C, $CC, $E6, $66, $66, $66, $66, $66, $CC, $CC, $CC, $66, $4C ; CPU:$FED5 PRG:3ED5 33 99 99 9C CC E6 66 66 66 66 66 CC CC CC 66 4C
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.byte $C9, $99, $99, $66, $66, $67, $33, $66, $66, $CC, $CC, $E6, $66, $71, $AA, $66 ; CPU:$FEE5 PRG:3EE5 C9 99 99 66 66 67 33 66 66 CC CC E6 66 71 AA 66
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.byte $65, $8E, $67, $33, $94, $CC, $66, $65, $99, $4C, $CC, $A6, $65, $4C, $CC, $CC ; CPU:$FEF5 PRG:3EF5 65 8E 67 33 94 CC 66 65 99 4C CC A6 65 4C CC CC
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.byte $CC, $98, $C6, $4C, $D3, $95, $99, $99, $9C, $CD, $59, $AC, $CD, $99, $99, $B3 ; CPU:$FF05 PRG:3F05 CC 98 C6 4C D3 95 99 99 9C CD 59 AC CD 99 99 B3
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.byte $39, $AB, $32, $66, $33, $19, $A6, $73, $2C, $CC, $CE, $66, $66, $67, $33, $33 ; CPU:$FF15 PRG:3F15 39 AB 32 66 33 19 A6 73 2C CC CE 66 66 67 33 33
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.byte $33, $26, $53, $18, $C9, $99, $99, $B3, $33, $33, $33, $33, $33, $33, $2A, $CC ; CPU:$FF25 PRG:3F25 33 26 53 18 C9 99 99 B3 33 33 33 33 33 33 2A CC
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.byte $CC, $CC, $CC, $D9, $99, $99, $65, $35, $99, $AC, $CC, $E6, $66, $99, $99, $99 ; CPU:$FF35 PRG:3F35 CC CC CC D9 99 99 65 35 99 AC CC E6 66 99 99 99
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.byte $98, $C9, $98, $CA, $66, $66, $53, $53, $36, $55, $99, $99, $B3, $33, $33, $1A ; CPU:$FF45 PRG:3F45 98 C9 98 CA 66 66 53 53 36 55 99 99 B3 33 33 1A
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.byte $66, $66, $66, $66, $66, $6B, $35, $9B, $33, $39, $99, $B3, $59, $99, $9A, $CC ; CPU:$FF55 PRG:3F55 66 66 66 66 66 6B 35 9B 33 39 99 B3 59 99 9A CC
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.byte $A9, $CC, $66, $64, $CC, $A6, $65, $33, $26, $66, $4C, $C6, $66, $64, $CC, $CC ; CPU:$FF65 PRG:3F65 A9 CC 66 64 CC A6 65 33 26 66 4C C6 66 64 CC CC
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.byte $CC, $CC, $CC, $CC, $CC, $CD, $99, $99, $99, $B3, $33, $33, $39, $99, $99, $B3 ; CPU:$FF75 PRG:3F75 CC CC CC CC CC CD 99 99 99 B3 33 33 39 99 99 B3
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.byte $33, $33, $39, $99, $9A, $66, $53, $31, $99, $99, $39, $98, $CC, $CC, $CC, $CC ; CPU:$FF85 PRG:3F85 33 33 39 99 9A 66 53 31 99 99 39 98 CC CC CC CC
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.byte $CE, $66, $67, $35, $99, $93, $32, $99, $99, $99, $9A, $CC, $CC, $CC, $CC, $CC ; CPU:$FF95 PRG:3F95 CE 66 67 35 99 93 32 99 99 99 9A CC CC CC CC CC
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.byte $CC, $B1, $98, $CC, $CC, $66, $66, $66, $66, $66, $66, $66, $66, $66, $69, $A7 ; CPU:$FFA5 PRG:3FA5 CC B1 98 CC CC 66 66 66 66 66 66 66 66 66 69 A7
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.byte $33, $33, $33, $39, $99, $99, $CC, $CC, $D3, $54, $CC, $CB, $19, $99, $99, $99 ; CPU:$FFB5 PRG:3FB5 33 33 33 39 99 99 CC CC D3 54 CC CB 19 99 99 99
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.byte $99, $99, $AB, $33, $33, $33, $33, $33, $39, $99, $00, $00, $00, $00, $00, $00 ; CPU:$FFC5 PRG:3FC5 99 99 AB 33 33 33 33 33 39 99 00 00 00 00 00 00
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.byte $00, $00, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF ; CPU:$FFD5 PRG:3FD5 00 00 FF FF FF FF FF FF FF FF FF
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; Routine: IrqHandler
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; Global: Reachable code entry at CPU $FFF9 traced from the interrupt-root control-flow graph.
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; Local: Performs the instruction sequence below; semantic purpose remains provisional.
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; Parameters: Register and memory inputs are caller-dependent.
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; Returns: Determined by the terminating RTS, RTI, jump, or branch path.
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; Side effects: Registers, flags, memory, and hardware registers written below.
|
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; Confidence: High for reachability and encoding; semantic role provisional.
|
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IrqHandler:
|
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rti ; CPU:$FFE0 PRG:3FE0 ??
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; Interrupt vectors at CPU $FFFA-$FFFF.
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Vectors:
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.word NmiHandler ; CPU:$FFE2 PRG:3FE2 ??
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.word Reset ; CPU:$FFE4 PRG:3FE4 ??
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.word IrqHandler ; CPU:$FFE6 PRG:3FE6 ??
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