tmerrittandClaude Opus 4.8
49e117bfcc
- Apply symbols.inc hardware register names to Defender 2 (U) (51 operands)
- Apply symbols.inc hardware register names to Donkey Kong 3 (JUE) (36 operands)
- Add APU register symbols (-) to Defender 2 (U) and Donkey Kong 3 (JUE) symbols.inc
- Apply symbols to Donkey Kong Jr. Math (U) (80 operands: 11 single + 69 hardware)
- Apply symbols to Excitebike (JU) (786 operands: 785 single + 1 hardware)
- Add promotion criteria to PROMPTS.md: symbol/local substitution,
ROM-specific semantic naming, and verification checklist
Add branch/jump target naming requirement to PROMPTS.md
All branches and jumps must target symbolic labels with descriptive names
derived from program flow role (e.g., _Loop, _Next, _Done, _Store, _Return),
never raw address literals. Adds criterion 8 to verification checklist.
Rename all OVERVIEW.md to README.md; add root README content to top-level
- Rename all OVERVIEW.md files to README.md throughout the repo (47 files)
- Prepend README.md content to top-level OVERVIEW.md before rename
- Fix apply_symbols.py NAME_RE regex to handle spaced assignments
- Apply symbols.inc to Defender 2 (U) (51 hardware operands)
- Apply symbols.inc to Donkey Kong 3 (JUE) (36 hardware operands)
- Apply symbols.inc to Donkey Kong Jr. Math (U) (80 operands: 11 single + 69 hardware)
- Apply symbols.inc to Excitebike (JU) (786 operands: 785 single + 1 hardware)
- Add missing Zp18/FrameCounter aliases to Excitebike prg.s
- Build all 27 top-level projects: byte-identical
Promote Donkey Kong Jr. Math back to _wip tier
Moves code from `copilot` folder and verifies each builds after
Add pre-commit hook for byte-identical verification
Add .git/hooks/pre-commit that runs 'make' then 'make clean' in each
project directory before committing. This ensures every project builds
byte-identical before any commit is accepted.
Also includes all file moves from the Donkey Kong Jr. Math (U) demotion
and other file restructuring from the session.
moves code out of copilot folder, its all AI generated.
Moves NROM games into NROM folder
removes copilot folder from Lunar Pool
Adds makefile to build all projects recursively
Updates docs to reflect changes in layout
Repromotes Donkey Kong Jr Math
Repromotes Excitebike
Promotes Popeye (JU) (PRG 1)
Updates Makefile to provide summary of build failure/success
Promote Raid on Bungeling Bay (U): Pass 2/3 partial, whole-ROM byte-identical
Move _wip/NROM/Raid on Bungeling Bay (U) to NROM/ and switch the build
from a PRG-only compare to a whole-ROM one:
- header.s/chr.s added (one-line .incbin of header.bin / chr.bin)
- linker.cfg gains HEADER ($0000, $0010) and CHR ($0000, $2000)
areas ahead of PRG ($C000, $4000)
- rom.nes symlink to the space-containing original ROM name
- Makefile builds header.o/prg.o/chr.o into reconstructed.nes and
compares it against rom.nes ('Byte-identical ROM verified.')
- one leftover neutral indirect operand jmp (Zp01) at $E2EC becomes
jmp (IndDispatch01); apply_symbols.py reports 0 substitutions pending
README.md / TODO.md / AGENTS.md updated: 29 promoted, 7 in _wip/.
Pac-Man (U): Pass 2 complete (label renaming) + Pass 3 partial (ZP aliases, table names)
Pass 2 — fresh map derived from the committed split, not from any drafted
map (the drafted maps in other projects were audited and found not
applicable):
- all 194 address-derived Label_XXXX definitions renamed to semantic
routine-entry names plus <Routine>_<Role>_<addr> internal branch
targets; zero Label_ remains
- all 49 jsr/jmp call sites resolved from raw $XXXX to labels; zero
raw $XXXX call operands remain
- routinemap.tsv / derived_names.tsv record the derivation
Pass 3 (partial):
- 15 proven semantic zero-page aliases added to locals.inc
(GameState, NmiFlag, ScrollX/Y, PpuCtrlShadow, OamDmaPage,
CocktailModeFlag, ActivePlayerFlag, GameplaySuspended, FrameCounter,
StateTimer, Player1/2Input, ActiveInput, CopyrightVerified)
- 112 operands substituted into prg.s (11 single + 101 hardware)
- key data tables named: ProgrammerSig ($C0EB), GameStateDispatchTable
($C253), TitleScreenData ($C2FD), EntityPtrTable ($D912),
AudioCommandTable ($EFDD)
Also corrects the README's claim that the RESET vector points at padding:
$FF00 holds real boot code (sei/cld, PPU off, double vblank wait, then
jmp ColdStart at $C042).
.gitignore: ignore reconstructed_prg.bin (build artifact of the _wip
Makefiles; '**/reconstructed.*' does not match the underscore form).
Promote Pac-Man (U): Pass 2/3 complete, whole-ROM byte-identical
Move _wip/NROM/Pac-Man (U) to NROM/ and switch the build from a PRG-only
compare to a whole-ROM one:
- header.s/chr.s added (one-line .incbin of header.bin / chr.bin)
- linker.cfg gains HEADER ($0000, $0010) and CHR ($0000, $2000)
areas ahead of PRG ($C000, $4000)
- rom.nes symlink to 'Pac-Man (U) [!].nes' (the original ROM name
contains a space and brackets)
- Makefile builds header.o/prg.o/chr.o into reconstructed.nes and
compares it against rom.nes
- reconstructed.nes is 24,592 bytes, MD5 a69d310f8cae9397fbd39f204672b5c7
- equal to the original ROM; the header/prg/chr splits were checked
against the original before promotion and are byte-exact
Pass 3 residue closed. The last 7 multi-alias zero-page operands are
resolved per site through a new sites.tsv, each proven from context
rather than guessed:
- jmp ($0010) at $C250/$D3CA/$D90F/$D9B6 -> (DispatchPtrLo); each
is immediately preceded by sta DispatchPtrLo/sta DispatchPtrHi
- jmp ($00FE) at $EFDA -> (AudioHandlerPtrLo); preceded by
sta AudioHandlerPtrLo/sta AudioHandlerPtrHi
- sta a:$0000,y at $C048/$C089 -> a:Zp00,y; the literal zero-page
base in the two ZP clear loops, so the neutral name is used rather
than the semantic WorkPtrLo. The 'a:' prefix survives the
substitution, so the bytes stay 99 00 00 (sta abs,Y)
apply_symbols.py now reports 119 operands substituted (101 hardware,
11 single-name, 7 site) and 0 residue.
New tool _tools/align_audit_comments.py: re-aligns the audit comment to
column 35 after a substitution lengthens an operand (nesdis.py pads each
instruction to 31 characters). Whitespace-only, so the byte identity
cannot change. 405 lines re-aligned in this project; all 2,387 audit
comments still match prg.bin at the stated PRG offset, 0 mismatches.
Docs: root README.md / TODO.md / AGENTS.md updated - 30 promoted, 6 in
_wip/; a per-project detail entry for Pac-Man (U) added; the stale
'Donkey Kong 3 (JUE) has no README.md' claim corrected (it has a
318-line one).
Promote Raid on Bungeling Bay (U) [a2]: Pass 3 complete, whole-ROM byte-identical
Move _wip/NROM/Raid on Bungeling Bay (U) [a2] to NROM/ and switch the build
from a PRG-only compare to a whole-ROM one:
- header.s/chr.s added (one-line .incbin of header.bin / chr.bin)
- linker.cfg gains HEADER ($0000, $0010) and CHR ($0000, $2000)
areas ahead of PRG ($C000, $4000)
- rom.nes symlink to 'Raid on Bungeling Bay (U) [a2].nes' (the original
ROM name contains spaces and brackets)
- reconstructed.nes is 24,592 bytes, MD5 659d340a1e9d420eee28df13319b0094
- equal to the original ROM; the header/prg/chr splits were checked
against the original before promotion and are byte-exact
Pass 3 - 15 semantic zero-page aliases, each applied only at the sites
where its role is proven:
- PpuCtrlShadow ($C2), 15 sites: the reset entry primes it right after
'sta PPUCTRL', and every other use is an ora/and/eor followed by
'sta PPUCTRL'
- NmiPathSelector ($C4), 5 sites: written 1 at $C3E9 and 0 at $C962
- GameState ($D6), 6 sites: 'cmp #$02' and used as an index at $C4C7
- FrameSubCounter ($55), 6 sites: set to $0A at $C520, decremented per
NMI at $C07B
- PrngPeriodCounter ($EA) / PrngSeedB ($EB) / PrngState ($EC), 13 sites:
the PRNG state
- PtrLo ($00) / PtrHi ($01), 8 sites: the 16-bit pair $1C13 and $1610
compared at $E785/$E791
- IndDispatch01 ($01) / IndDispatch02 ($02), 3 sites: the computed
dispatch at $E2EC
- IndDispatch1B ($1B) / IndDispatch1C ($1C), 6 sites: the dispatch at
$E7A3
- IndDispatch17 ($17) / IndDispatch19 ($19): the dispatches at $E79D
and $E7A0
Addresses that carry two names keep the neutral ZpXX name where the other
role applies - $01 is PtrHi at the 16-bit compare and IndDispatch01 at the
dispatch; $17 is IndDispatch17 at the dispatch and Zp17 for the absolute
RAM $0017 store in the copy loop at $E895/$E8D0.
New tool _tools/apply_zp_aliases.py does the per-site substitution:
apply_symbols.py only rewrites *numeric* operands, so it cannot rename an
operand that is already written as a neutral ZpXX name. The tool keeps the
ca65 'a:' prefix (dropping it would turn 'sta a:Zp17,y' into a zero-page
store and change the bytes) and rewrites only the operand token, so the
audit comment survives byte for byte.
Naming correction in the promoted sibling. Finishing this dump showed that
$EA was misnamed 'VBlankWaitCounter': the routine at $C412 is the game's
pseudo-random generator (the classic eor/asl/php/lsr/plp/rol scrambler,
called from thirteen gameplay sites, twice in a row at $CDF4/$CDF9 with the
second result masked #$07), so $EA is the scrambler's phase counter.
Renamed PrngPeriodCounter in both dumps and named $EB/$EC PrngSeedB /
PrngState. The sibling's two 'sta a:IndDispatch17,y' operands were also
wrong - they are absolute stores to RAM $0017, not the dispatch pointer -
and are now 'a:Zp17,y', matching the file's 'a:' = absolute convention.
Audit-comment alignment re-done with _tools/align_audit_comments.py (1,040
lines here, 1,080 in the sibling). Both files still match prg.bin at every
stated PRG offset: 5,467 and 5,483 audit comments, 0 mismatches.
Docs: root README.md / TODO.md / AGENTS.md updated - 31 promoted, 5 in
_wip/; per-project detail entries added for both Raid dumps.
Promote Pac-Man (Tengen) (U): Pass 2/3 from scratch, whole-ROM byte-identical
Move _wip/NROM/Pac-Man (Tengen) (U) to NROM/ and switch the build from a
PRG-only compare to a whole-ROM one:
- header.s/chr.s added (one-line .incbin of header.bin / chr.bin)
- linker.cfg gains HEADER ($0000, $0010) and CHR ($0000, $2000)
areas ahead of PRG ($C000, $4000)
- rom.nes symlink to 'Pac-Man (Tengen) (U) [!].nes'
- reconstructed.nes is 24,592 bytes, MD5 d34e7a74d8d2c231b6cc601210e28ad0
- equal to the original ROM; the header/prg/chr splits were checked
against the original before promotion and are byte-exact
Disassembled from scratch. No name, map or file was carried over from the
sibling 'Pac-Man (U)' dump; the map was derived from this dump's own
committed split and the two were only compared afterwards.
Pass 2 (new tool _tools/apply_pass2_map.py):
- all 194 Label_XXXX definitions renamed to semantic routine entries plus
<Routine>_<Role> branch targets; zero Label_ remains
- all 48 raw $XXXX jsr/jmp operands resolved to labels; zero raw $XXXX
call or branch operands remain
- the map is in routinemap.tsv
Pass 3:
- 30 semantic zero-page aliases, each applied only at the sites where its
role is proven (per-site choice in sites.tsv; the addresses that carry
two roles keep the neutral ZpXX name elsewhere). _tools/
derive_zp_aliases.py records how the set was derived, and locals.inc
records the reason for every remaining neutral slot
- 28 data tables named (new tool _tools/name_data_region.py), including
CharacterDataTable ($C66A) and CharacterNameStrings ($C67E), where the
ROM itself names Blinky, Pinky, Inky and Clyde - which is why the four
indexed entities are called ghosts and not 'actors'
- apply_symbols.py reports 0 substitutions pending and 0 residue
- audit-comment alignment re-done with _tools/align_audit_comments.py;
all 2,479 audit comments still match prg.bin at the stated PRG offset
Pass 1 correction - six command handlers recovered (new tool
_tools/recode_region.py). ScriptCommandTable ($EFDD) is read by the traced
instruction at $EFCC, and six of its entries point at $F00A, $F022, $F03A,
$F052, $F062 and $F072 - all of which the tracer had left as data, and two
of which it had mis-split across the 'jmp $EF61' at $F01F and $F04F.
Those 120 bytes are code here, decoded straight from the ROM; the six
handlers tile $F00A-$F081 exactly. The same gap exists in the promoted
'Pac-Man (U)' dump, which has not been corrected - recorded in both READMEs.
Residue (documented, not guessed): the unreached main game logic at
$C45A-$C55F is still .byte data. It is code - the tracer's own decoder
walks it cleanly and the dispatch table at $C511 points into it - but
nothing reaches it, so it cannot be entered without a guess. The same gap
exists in the promoted 'Pac-Man (U)' dump. Re-deriving it is a Pass 1 job;
a Mesen Code Data Logger capture is the tool the repo uses for it.
Docs: root README.md / TODO.md / AGENTS.md updated - 32 promoted, 4 in
_wip/; a per-project detail entry added for the Tengen dump.
Promote Pyramid (U): Pass 1 corrected, Pass 2/3 complete, whole-ROM byte-identical
Move _wip/NROM/Pyramid (U) to NROM/ and switch the build from a PRG-only
compare to a whole-ROM one:
- header.s/chr.s added (one-line .incbin of header.bin / chr.bin)
- linker.cfg gains HEADER ($0000, $0010) and CHR ($0000, $2000)
areas ahead of PRG ($C000, $4000)
- rom.nes symlink to 'Pyramid (U) (Sachen).nes'
- reconstructed.nes is 24,592 bytes, MD5 aa285ff17f25dd05da5996b7466c59e2
- equal to the original ROM; the header/prg/chr splits were checked
against the original before promotion and are byte-exact
Pass 1 correction - the committed split was a strict subset of the correct
one. This game dispatches through 'jmp' trampoline tables that live
*inside* the data regions, and the tracer cannot follow a jmp there, so
828 bytes of code were still marked as data. Four such tables were found
($C01E 3 entries, $C02A 6, $C042 2, $C054 5) plus ten more entries at
$C000-$C01B; all sixteen targets decode as valid instructions. Seeding
them, the $C800 boot mainline and six further code starts recovers the
whole lot, plus a five-byte stub at $DF89 (lda $33 / jmp $DECB) that sat
in a hole between two routines. The re-trace loses NO committed code byte
and takes the split from 34.5% to 39.6% (3,130 instructions / 6,493 code
bytes). 'make regen' reproduces it, so the split stays verifiable.
Pass 2 - a fresh map derived from this dump's own committed split:
- 428 Label_XXXX definitions renamed; zero Label_ residue
- 320 raw $XXXX jsr/jmp operands resolved; zero raw $XXXX branch
operands remain
- 431 routine entries and the 32 data blocks named from the code
- the internal branch-target names are derived mechanically from the
branch that reaches them by the new _tools/derive_branch_names.py
(beq -> OnZero, bne -> OnNonzero, bcc/bcs -> the carry cases, a
backwards branch -> Loop)
- recorded in routinemap.tsv
Pass 3:
- 24 semantic zero-page aliases, each applied only where its role is
proven; the 57 slots that stay neutral are each listed with the reason
in locals.inc (the neutral set lives in zp_aliases.inc so that
'make regen' can rebuild locals.inc from prg.bin)
- 32 data tables named - TaskVectorTable1/2, LevelScriptData,
MusicPeriodTable, SoundEnvelopeTable, the actor tables - recorded in
data_region_names.tsv
- apply_symbols.py reports 0 substitutions pending and 0 residue; no
hardware register is left as a raw literal
- the audit comments are now canonical on every line, data included
(the old file carried only 'PRG:$xxxx' on its 1,358 data lines);
all 3,762 audit comments match prg.bin at their stated PRG offset
Kept as-is, not 'cleaned up':
- sta $4100 stays a raw operand. The iNES header claims mapper 0 but
the boot code writes past the NES register space; the ROM does not
explain it, so it is recorded rather than guessed
- the 'A'/'V' check on RAM $0120/$0121 and its seed/clear routines
are named for what they do, not for what they are for
- the ninth entry of the $C3A6 task vector table ($D820) is a junk
slot and stays data
Docs: root README.md / TODO.md / AGENTS.md updated - 33 promoted, 3 in
_wip/; a per-project detail entry added.
Hogan's Alley (JU): Pass 1 correction, Pass 2, Pass 3, promoted to NROM/
The light-gun game whose engine dispatches through *inline* tables:
`IndirectCall` at $C34D pops the return address of the `jsr` that called
it and reads a 16-bit handler pointer from the word that follows, so all
six handler tables ($C124 19 entries, $C219 4, $C89C 14, $CDD1 1, $D234 2,
$D3D6 14) live inside the code stream and the static tracer cannot follow
them.
Pass 1 correction. The committed split was a strict subset of the correct
one -- 41.8% of the PRG was classified as code. A fresh Mesen Code Data
Logger capture was merged with the four captures already in the folder
(hogans_merged.cdl, the OR of five per-byte flag arrays, 6,544 code bytes)
and _tools/cdl_reclass.py rewrote the split to match what the CPU actually
fetched: 1,216 bytes moved from data to code, five the other way, 59 labels
emitted. The split is now 49.1% code (3,950 instructions, 8,041 bytes).
The four branch targets the reclassifier could not prove were turned into
labels by the new _tools/resolve_raw_branches.py.
Pass 2. 206 routine entries hand-named from this dump's own code and 413
internal branch targets derived mechanically by _tools/derive_branch_names.py:
630 Label_XXXX definitions gone, 484 raw $XXXX call operands resolved, 15
call targets the tracer had never labelled given a label. Recorded in
routinemap.tsv. No SubC<addr> residue was needed -- every entry the engine
reaches is named after what it does.
Pass 3. 60 semantic zero-page aliases, each applied only where its role is
proven (zp_aliases.inc, zp_alias_sites.tsv); the slots that stay neutral are
each listed with the reason. All 34 data blocks named
(data_region_names.tsv). apply_symbols.py reports 1 residue: `sta a:$00B4,y`
at $C203, the same address as Zp40/ActorPalette but forced to absolute
addressing, so it must stay numeric.
Promotion. header.s, chr.s and a HEADER/PRG/CHR linker.cfg added, rom.nes
symlinked to the original ROM; the whole-ROM cmp passes on the first
promoted build. There is deliberately no `make regen` target: the Pass 1
split here is the static trace corrected by a CDL capture, and the base the
correction was applied to is not what the current _tools/nesdis.py
produces, so prg.s is the maintained source of truth.
Tools changed:
nesdis.py --split/--note/--provenance options, so a data
region can carry its own name and explanation;
a forced-data address is no longer reported as a
recovered routine entry
apply_pass2_map.py can create the label for a call target the tracer
left unlabelled; no longer double-labels it
apply_zp_aliases.py --at-file, an address-based per-site list
derive_branch_names.py keeps the map's own header instead of writing a
fixed one
resolve_raw_branches.py new: turns `bXX *+$NN` operands into labels
build_hogans_map.py new: the hand-written Pass 2 map builder
The existing regen pipelines (MUSCLE (U), Urban Champion (JU)) still
reproduce prg.s byte for byte.
Apply the symbols.inc register names at Pass 1; fix a dropped byte in cdl_reclass
nesdis.py now names the hardware registers as it renders the operands, so a
project's Pass 1 output already reads `lda PPUSTATUS` instead of `lda $2002`
and the Pass 3 apply_symbols.py step has nothing left to do for them.
* nesdis.py --symbols FILE reads a symbols.inc-style file and substitutes
the register names. Only unambiguous entries in the $2000-$4017 window
are used: $4017 is both JOY2 and APUFRAMECOUNTER, so it stays numeric
and apply_symbols.py reports it as multi-alias residue, exactly as
before. The default is the symbols.inc next to --out, so a new project
gets the names without asking; --no-symbols opts out.
* The renderer records the operand's numeric value on the Insn, because
operand_value() used to re-parse the operand text and could no longer
read a name.
* The controller bit masks in symbols.inc (PAD_A and friends) are
constants, not addresses, and are still never substituted.
MUSCLE (U) and Urban Champion (JU) keep --no-symbols: their committed
prg.s was produced with the registers named by the Pass 3 apply_symbols.py
step, and the columns in those files reflect the in-place substitution.
Adding the missing apply_symbols.py step to both regen pipelines makes
them reproduce their committed prg.s byte for byte again - neither did
before this change (MUSCLE was 440 lines out, Urban Champion 772).
cdl_reclass.py had a bug that cost a byte: a region whose last source row
straddled the region's end was replaced by a regeneration of the region
only, so the tail of that row was dropped. Mario Bros (JU) hit it at
$C595, where the rebuild came out one byte short and every label after it
shifted. A region now covers the whole rows it replaces.
pass2.py reflow takes an optional column argument; the default is
unchanged (the ';' lands on the same column as before).
Mario Bros (JU): Pass 1 correction, Pass 2, Pass 3, promoted to NROM/
A two-player platformer whose handler tables are *inline*: the pointers sit
in the middle of the code stream, right after the `jsr` that reads them, so
the static tracer could never follow them.
Pass 1 correction. The committed split was a strict subset of the correct
one -- only 72.0% of the PRG was classified as code. A Mesen Code Data
Logger capture of this ROM (mario_mesen.cdl, 10,915 code bytes) showed
1,010 bytes the tracer had left as data were code; two branch targets the
capture never reached ($E4CB and $E639) were forced with --override for 57
more, so 1,067 bytes moved from data to code and 22 moved the other way.
The split is now 78.4% code (6,210 instructions, 12,847 bytes). The three
branch targets the reclassifier could not prove were turned into labels by
_resolve_raw_branches.py, which now refuses to put a label on a `.byte` row.
Pass 2. 206 routine entries and 519 internal branch targets: 931
Label_XXXX definitions gone, 51 raw $XXXX call operands resolved and 12 call
targets the tracer had never labelled given a label. Zero SubC residue --
the 185 entries a previous session had left as address-derived residue were
all named from this dump's own code. Recorded in routinemap.tsv.
Pass 3. 25 semantic zero-page aliases, each applied only where its role is
proven (zp_aliases.inc); the slots that stay neutral are each listed with the
reason. 35 data tables named -- GameStateHandlerTable, EnemyBehaviourTable,
EnemyScriptTable, EnemyTypePointerTable, SoundRoutineTable,
NoteFrequencyTable and the rest -- and recorded in
data_region_names.tsv. apply_symbols.py reports 0 residue.
Promotion. header.s, chr.s and a HEADER/PRG/CHR linker.cfg added, rom.nes
symlinked to the original ROM; the whole-ROM cmp passes on the first
promoted build. There is deliberately no `make regen` target: the Pass 1
split here is the static trace corrected by a CDL capture, and the base the
correction was applied to is not what the current _tools/nesdis.py
produces, so prg.s is the maintained source of truth.
Tools:
apply_pass2_map.py renames a label of any spelling -- SubC<addr> is
the honest residue form -- and its references
follow it; one combined pattern, so a 16,000-line
file does not need a substitution per label
resolve_raw_branches.py refuses to label a data row
build_mario_map.py new: the hand-written Pass 2 map builder
Remove the old _wip/NROM/Mario Bros (JU) folder (promoted to NROM/)
Mario Bros (JU): add the promoted-tier header, CHR, rom.nes symlink and zero-page aliases
Moves _ROMS/<ROM> into _wip/<MAPPER>/<ROM>
Sync the docs and the skeleton tool with the 857-project _wip tier
The _wip/ tier now holds 857 projects across 30 mapper folders, all
building byte-identical for the whole ROM. README.md, TODO.md and
AGENTS.md still described the old 39-project tier, so bring them in line
with WIP.md, which carries the tier's index.
The tier is no longer 39 projects of NROM-256 with a 16/32 KB PRG:
only two projects have a 16 KB PRG, 151 have 32 KB, 523 have 128 KB and
one has 1.5 MB, so most of it is a banked mapper whose image does not fit
the 6502's address space. Those projects link their MEMORY areas at .nes
file offsets rather than CPU addresses, which is the only option and the
honest model; the 39 older projects keep the CPU-address layout because
their PRG really is one contiguous window.
make_skeleton.py gains the two layouts (--layout flat|cpu), the board
name for the mapper, and a fix for find_rom() mistaking the build
output reconstructed.nes for the source ROM.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
13542 lines
549 KiB
ArmAsm
13542 lines
549 KiB
ArmAsm
; Golf (JU) NES disassembly - Pass 1 generated source
|
|
; Confirmed reachable instructions are assembled explicitly.
|
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; Unclassified or structured-data spans remain localized .incbin blocks.
|
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; Every instruction comment gives CPU address followed by expected bytes.
|
|
|
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.setcpu "6502"
|
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|
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.include "symbols.inc"
|
|
.include "locals.inc"
|
|
|
|
.segment "PRG"
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Reset
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C000.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
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; Clobbers:
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; A, X, Y, and processor flags as used by the instructions below.
|
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; ---------------------------------------------------------------------------
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Reset:
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LDA #$00 ; C000: A9 00
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STA PPUCTRL ; C002: 8D 00 20
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CLD ; C005: D8
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SEI ; C006: 78
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|
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; ---------------------------------------------------------------------------
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; WaitForFirstVblank
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C007.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
WaitForFirstVblank:
|
|
LDA PPUSTATUS ; C007: AD 02 20
|
|
BPL WaitForFirstVblank ; C00A: 10 FB
|
|
LDX #$FF ; C00C: A2 FF
|
|
TXS ; C00E: 9A
|
|
INX ; C00F: E8
|
|
STX PPUMASK ; C010: 8E 01 20
|
|
STX APUSTATUS ; C013: 8E 15 40
|
|
LDA #$90 ; C016: A9 90
|
|
STA ppu_ctrl_shadow ; C018: 85 00
|
|
AND #$7F ; C01A: 29 7F
|
|
STA PPUCTRL ; C01C: 8D 00 20
|
|
LDA #$1A ; C01F: A9 1A
|
|
STA ppu_mask_shadow ; C021: 85 01
|
|
LDA #$64 ; C023: A9 64
|
|
STA $0E ; C025: 85 0E
|
|
STA $82 ; C027: 85 82
|
|
LDA #$00 ; C029: A9 00
|
|
STA PPUMASK ; C02B: 8D 01 20
|
|
STA $0D ; C02E: 85 0D
|
|
STA $0143 ; C030: 8D 43 01
|
|
STA $0F ; C033: 85 0F
|
|
STA $10 ; C035: 85 10
|
|
STA $2B ; C037: 85 2B
|
|
STA $2C ; C039: 85 2C
|
|
STA $14 ; C03B: 85 14
|
|
TAY ; C03D: A8
|
|
TAX ; C03E: AA
|
|
LDA #$FF ; C03F: A9 FF
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ClearStartupRamLoop
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C041.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
ClearStartupRamLoop:
|
|
STA $0700,Y ; C041: 99 00 07
|
|
STA $0700,X ; C044: 9D 00 07
|
|
DEX ; C047: CA
|
|
INY ; C048: C8
|
|
CPY #$40 ; C049: C0 40
|
|
BNE Label_C04F ; C04B: D0 02
|
|
LDA #$00 ; C04D: A9 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C04F
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C04F.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C04F:
|
|
CPY #$7E ; C04F: C0 7E
|
|
BNE Label_C055 ; C051: D0 02
|
|
LDA #$01 ; C053: A9 01
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C055
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C055.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C055:
|
|
CPY #$81 ; C055: C0 81
|
|
BNE ClearStartupRamLoop ; C057: D0 E8
|
|
LDX #$00 ; C059: A2 00
|
|
LDY #$00 ; C05B: A0 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; CopyStartupTableLoop
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C05D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
CopyStartupTableLoop:
|
|
LDA $D563,Y ; C05D: B9 63 D5
|
|
STA $0600,Y ; C060: 99 00 06
|
|
STA $0600,X ; C063: 9D 00 06
|
|
DEX ; C066: CA
|
|
INY ; C067: C8
|
|
CPY #$81 ; C068: C0 81
|
|
BCC CopyStartupTableLoop ; C06A: 90 F1
|
|
LDA #$12 ; C06C: A9 12
|
|
STA $19 ; C06E: 85 19
|
|
LDX #$0E ; C070: A2 0E
|
|
LDA #$08 ; C072: A9 08
|
|
LDY #$00 ; C074: A0 00
|
|
JSR ReadPpuBlocks ; C076: 20 87 C0
|
|
LDA #$07 ; C079: A9 07
|
|
STA $19 ; C07B: 85 19
|
|
LDX #$0F ; C07D: A2 0F
|
|
LDA #$50 ; C07F: A9 50
|
|
JSR ReadPpuBlocks ; C081: 20 87 C0
|
|
JMP InitializeTitleAndGame ; C084: 4C 23 DA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ReadPpuBlocks
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C087.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
ReadPpuBlocks:
|
|
JSR SetPpuAddress ; C087: 20 C1 C8
|
|
LDA PPUDATA ; C08A: AD 07 20
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ReadPpuBlockBytes
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C08D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
ReadPpuBlockBytes:
|
|
LDX #$08 ; C08D: A2 08
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ReadPpuBlockByteLoop
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C08F.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
ReadPpuBlockByteLoop:
|
|
LDA PPUDATA ; C08F: AD 07 20
|
|
STA $0500,Y ; C092: 99 00 05
|
|
INY ; C095: C8
|
|
DEX ; C096: CA
|
|
BNE ReadPpuBlockByteLoop ; C097: D0 F6
|
|
LDX #$08 ; C099: A2 08
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; DiscardPpuBlockByteLoop
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C09B.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
DiscardPpuBlockByteLoop:
|
|
LDA PPUDATA ; C09B: AD 07 20
|
|
DEX ; C09E: CA
|
|
BNE DiscardPpuBlockByteLoop ; C09F: D0 FA
|
|
DEC $19 ; C0A1: C6 19
|
|
BPL ReadPpuBlockBytes ; C0A3: 10 E8
|
|
RTS ; C0A5: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; NmiHandler
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C0A6.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
NmiHandler:
|
|
PHA ; C0A6: 48
|
|
TXA ; C0A7: 8A
|
|
PHA ; C0A8: 48
|
|
TYA ; C0A9: 98
|
|
PHA ; C0AA: 48
|
|
LDA #$00 ; C0AB: A9 00
|
|
STA OAMADDR ; C0AD: 8D 03 20
|
|
LDA #$02 ; C0B0: A9 02
|
|
STA OAMDMA ; C0B2: 8D 14 40
|
|
JMP (nmi_vector_lo) ; C0B5: 6C 02 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; NmiEpilogue
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C0B8.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
NmiEpilogue:
|
|
INC $8B ; C0B8: E6 8B
|
|
LDA #$01 ; C0BA: A9 01
|
|
STA $08 ; C0BC: 85 08
|
|
PLA ; C0BE: 68
|
|
TAY ; C0BF: A8
|
|
PLA ; C0C0: 68
|
|
TAX ; C0C1: AA
|
|
PLA ; C0C2: 68
|
|
RTI ; C0C3: 40
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; IrqLoop
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C0C4.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
IrqLoop:
|
|
JMP IrqLoop ; C0C4: 4C C4 C0
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; InitializeRuntimeState
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C0C7.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
InitializeRuntimeState:
|
|
LDA #$00 ; C0C7: A9 00
|
|
STA $82 ; C0C9: 85 82
|
|
STA $2B ; C0CB: 85 2B
|
|
STA $0F ; C0CD: 85 0F
|
|
STA $10 ; C0CF: 85 10
|
|
STA $11 ; C0D1: 85 11
|
|
STA $12 ; C0D3: 85 12
|
|
STA $7A ; C0D5: 85 7A
|
|
STA $84 ; C0D7: 85 84
|
|
STA $14 ; C0D9: 85 14
|
|
LDA #$18 ; C0DB: A9 18
|
|
STA animation_frame_index ; C0DD: 85 8F
|
|
LDA #$12 ; C0DF: A9 12
|
|
STA $88 ; C0E1: 85 88
|
|
LDA $0D ; C0E3: A5 0D
|
|
STA $0143 ; C0E5: 8D 43 01
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC0E8
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C0E8.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC0E8:
|
|
LDY #$C8 ; C0E8: A0 C8
|
|
LDX #$C6 ; C0EA: A2 C6
|
|
JSR InstallNmiCallback ; C0EC: 20 88 C8
|
|
LDY #$00 ; C0EF: A0 00
|
|
STY $0141 ; C0F1: 8C 41 01
|
|
STY $0142 ; C0F4: 8C 42 01
|
|
STY $17 ; C0F7: 84 17
|
|
STY $15 ; C0F9: 84 15
|
|
STY $44 ; C0FB: 84 44
|
|
STY $45 ; C0FD: 84 45
|
|
STY $2C ; C0FF: 84 2C
|
|
STY $2D ; C101: 84 2D
|
|
STY $49 ; C103: 84 49
|
|
STY $7B ; C105: 84 7B
|
|
STY $7C ; C107: 84 7C
|
|
STY $7F ; C109: 84 7F
|
|
STY $80 ; C10B: 84 80
|
|
STY $53 ; C10D: 84 53
|
|
STY APUPULSE1CTRL ; C10F: 8C 00 40
|
|
STY APUPULSE2CTRL ; C112: 8C 04 40
|
|
STY APUTRIANGLECTRL ; C115: 8C 08 40
|
|
STY APUNOISECTRL ; C118: 8C 0C 40
|
|
INY ; C11B: C8
|
|
STY $4A ; C11C: 84 4A
|
|
LDA #$0F ; C11E: A9 0F
|
|
STA APUSTATUS ; C120: 8D 15 40
|
|
LDA $8B ; C123: A5 8B
|
|
STA $8C ; C125: 85 8C
|
|
JSR ClearNametableAndOam ; C127: 20 C8 C8
|
|
JSR SubCE6B0 ; C12A: 20 B0 E6
|
|
LDA ppu_ctrl_shadow ; C12D: A5 00
|
|
ORA #$80 ; C12F: 09 80
|
|
STA ppu_ctrl_shadow ; C131: 85 00
|
|
STA PPUCTRL ; C133: 8D 00 20
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC136
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C136.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC136:
|
|
LDY #$FF ; C136: A0 FF
|
|
STY $0278 ; C138: 8C 78 02
|
|
STY $027C ; C13B: 8C 7C 02
|
|
LDA $0D ; C13E: A5 0D
|
|
BEQ Label_C17E ; C140: F0 3C
|
|
LDA $84 ; C142: A5 84
|
|
BNE Label_C14A ; C144: D0 04
|
|
LDA $7B ; C146: A5 7B
|
|
BEQ Label_C17E ; C148: F0 34
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C14A
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C14A.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C14A:
|
|
LDA $7C ; C14A: A5 7C
|
|
BEQ Label_C182 ; C14C: F0 34
|
|
LDA $7B ; C14E: A5 7B
|
|
BEQ Label_C17E ; C150: F0 2C
|
|
LDA $7C ; C152: A5 7C
|
|
CMP $7B ; C154: C5 7B
|
|
BNE Label_C17C ; C156: D0 24
|
|
CMP #$02 ; C158: C9 02
|
|
BCC Label_C160 ; C15A: 90 04
|
|
LDA #$01 ; C15C: A9 01
|
|
STA $49 ; C15E: 85 49
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C160
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C160.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C160:
|
|
LDA $40 ; C160: A5 40
|
|
STA $3B ; C162: 85 3B
|
|
LDA $3E ; C164: A5 3E
|
|
STA $38 ; C166: 85 38
|
|
JSR SubCF931 ; C168: 20 31 F9
|
|
LDA $5E ; C16B: A5 5E
|
|
PHA ; C16D: 48
|
|
LDA $41 ; C16E: A5 41
|
|
STA $3B ; C170: 85 3B
|
|
LDA $3F ; C172: A5 3F
|
|
STA $38 ; C174: 85 38
|
|
JSR SubCF931 ; C176: 20 31 F9
|
|
PLA ; C179: 68
|
|
CMP $5E ; C17A: C5 5E
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C17C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C17C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C17C:
|
|
BCC Label_C182 ; C17C: 90 04
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C17E
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C17E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C17E:
|
|
LDA #$00 ; C17E: A9 00
|
|
BEQ Label_C184 ; C180: F0 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C182
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C182.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C182:
|
|
LDA #$01 ; C182: A9 01
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C184
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C184.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C184:
|
|
STA $7A ; C184: 85 7A
|
|
TAX ; C186: AA
|
|
LDA $7B,X ; C187: B5 7B
|
|
STA $87 ; C189: 85 87
|
|
CMP #$03 ; C18B: C9 03
|
|
BNE Label_C192 ; C18D: D0 03
|
|
JMP SubCC484 ; C18F: 4C 84 C4
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C192
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C192.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C192:
|
|
CMP #$02 ; C192: C9 02
|
|
BNE Label_C199 ; C194: D0 03
|
|
LDA #$01 ; C196: A9 01
|
|
; Overlapping instruction idiom:
|
|
; C198: BIT $00A9 (2C A9 00)
|
|
; C199: LDA #$00 (A9 00)
|
|
Label_C198:
|
|
.byte $2C ; C198: 2C BIT absolute opcode
|
|
Label_C199:
|
|
.byte $A9,$00 ; C199-C19A: A9 00 LDA #$00
|
|
STA $49 ; C19B: 85 49
|
|
JSR WaitForFrame ; C19D: 20 F3 C8
|
|
JSR SubCC84D ; C1A0: 20 4D C8
|
|
JSR DecodeCoursePackage ; C1A3: 20 78 DD
|
|
LDX $7A ; C1A6: A6 7A
|
|
LDA $40,X ; C1A8: B5 40
|
|
STA $3B ; C1AA: 85 3B
|
|
LDA $3E,X ; C1AC: B5 3E
|
|
STA $38 ; C1AE: 85 38
|
|
LDA $7B,X ; C1B0: B5 7B
|
|
BNE Label_C1BC ; C1B2: D0 08
|
|
LDA $7E ; C1B4: A5 7E
|
|
STA $3B ; C1B6: 85 3B
|
|
LDA $7D ; C1B8: A5 7D
|
|
STA $38 ; C1BA: 85 38
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C1BC
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C1BC.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C1BC:
|
|
LDA $87 ; C1BC: A5 87
|
|
BEQ Label_C1CA ; C1BE: F0 0A
|
|
LDA $49 ; C1C0: A5 49
|
|
CMP $4A ; C1C2: C5 4A
|
|
BEQ Label_C1D1 ; C1C4: F0 0B
|
|
LDA $4A ; C1C6: A5 4A
|
|
BNE Label_C1CD ; C1C8: D0 03
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C1CA
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C1CA.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C1CA:
|
|
JSR UploadGeneratedCourseGrid ; C1CA: 20 98 FC
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C1CD
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C1CD.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C1CD:
|
|
LDA $49 ; C1CD: A5 49
|
|
STA $4A ; C1CF: 85 4A
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C1D1
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C1D1.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C1D1:
|
|
LDA #$00 ; C1D1: A9 00
|
|
STA $1A ; C1D3: 85 1A
|
|
JSR SubCFE72 ; C1D5: 20 72 FE
|
|
JSR SubCC916 ; C1D8: 20 16 C9
|
|
JSR SubCFCE6 ; C1DB: 20 E6 FC
|
|
JSR SpriteOffsetForController ; C1DE: 20 94 C8
|
|
LDA $3B ; C1E1: A5 3B
|
|
STA $0200,X ; C1E3: 9D 00 02
|
|
LDA #$DD ; C1E6: A9 DD
|
|
CPX #$00 ; C1E8: E0 00
|
|
BEQ Label_C1EF ; C1EA: F0 03
|
|
CLC ; C1EC: 18
|
|
ADC #$16 ; C1ED: 69 16
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C1EF
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C1EF.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C1EF:
|
|
STA $0201,X ; C1EF: 9D 01 02
|
|
LDA #$01 ; C1F2: A9 01
|
|
STA $0202,X ; C1F4: 9D 02 02
|
|
LDA $38 ; C1F7: A5 38
|
|
STA $0203,X ; C1F9: 9D 03 02
|
|
LDA $3B ; C1FC: A5 3B
|
|
STA $78 ; C1FE: 85 78
|
|
LDA $38 ; C200: A5 38
|
|
STA $79 ; C202: 85 79
|
|
JSR SubCD65D ; C204: 20 5D D6
|
|
JSR SubCD9FF ; C207: 20 FF D9
|
|
LDX active_controller_index ; C20A: A6 7A
|
|
LDA $0141,X ; C20C: BD 41 01
|
|
STA club_selection_index ; C20F: 85 17
|
|
JSR SubCCE64 ; C211: 20 64 CE
|
|
LDX active_controller_index ; C214: A6 7A
|
|
LDA club_selection_index ; C216: A5 17
|
|
STA $0141,X ; C218: 9D 41 01
|
|
LDA $34 ; C21B: A5 34
|
|
CMP #$02 ; C21D: C9 02
|
|
BEQ Label_C240 ; C21F: F0 1F
|
|
LDA #$02 ; C221: A9 02
|
|
STA APUNOISECTRL ; C223: 8D 0C 40
|
|
LDA #$09 ; C226: A9 09
|
|
STA APUNOISEPERIOD ; C228: 8D 0E 40
|
|
LDA #$10 ; C22B: A9 10
|
|
STA APUNOISELENGTH ; C22D: 8D 0F 40
|
|
LDX active_controller_index ; C230: A6 7A
|
|
LDA $7B,X ; C232: B5 7B
|
|
BNE Label_C238 ; C234: D0 02
|
|
INC $7B,X ; C236: F6 7B
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C238
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C238.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C238:
|
|
JSR SubCD13E ; C238: 20 3E D1
|
|
LDA #$00 ; C23B: A9 00
|
|
STA APUTRIANGLECTRL ; C23D: 8D 08 40
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C240
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C240.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C240:
|
|
LDY #$C8 ; C240: A0 C8
|
|
LDX #$C6 ; C242: A2 C6
|
|
JSR WaitForFramePreservingY ; C244: 20 81 C8
|
|
JSR RestorePpuCtrlShadow ; C247: 20 B5 C8
|
|
LDA #$00 ; C24A: A9 00
|
|
STA APUPULSE1CTRL ; C24C: 8D 00 40
|
|
JSR SubCCA8E ; C24F: 20 8E CA
|
|
JSR SubCC916 ; C252: 20 16 C9
|
|
LDX $7A ; C255: A6 7A
|
|
LDA $3B ; C257: A5 3B
|
|
STA $40,X ; C259: 95 40
|
|
LDA $38 ; C25B: A5 38
|
|
STA $3E,X ; C25D: 95 3E
|
|
LDA $34 ; C25F: A5 34
|
|
CMP #$02 ; C261: C9 02
|
|
BEQ Label_C2BA ; C263: F0 55
|
|
LDA $49 ; C265: A5 49
|
|
BEQ Label_C26C ; C267: F0 03
|
|
JMP SubCC3B1 ; C269: 4C B1 C3
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C26C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C26C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C26C:
|
|
JSR SubCD65A ; C26C: 20 5A D6
|
|
LDA $53 ; C26F: A5 53
|
|
BNE Label_C2C2 ; C271: D0 4F
|
|
LDA $52 ; C273: A5 52
|
|
BEQ Label_C27A ; C275: F0 03
|
|
JMP SubCC305 ; C277: 4C 05 C3
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C27A
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C27A.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C27A:
|
|
LDA $4F ; C27A: A5 4F
|
|
ORA $56 ; C27C: 05 56
|
|
BNE Label_C2D9 ; C27E: D0 59
|
|
LDA $55 ; C280: A5 55
|
|
BNE Label_C286 ; C282: D0 02
|
|
BEQ Label_C2BF ; C284: F0 39
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C286
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C286.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C286:
|
|
LDA #$06 ; C286: A9 06
|
|
STA APUNOISECTRL ; C288: 8D 0C 40
|
|
LDA #$02 ; C28B: A9 02
|
|
STA APUNOISEPERIOD ; C28D: 8D 0E 40
|
|
LDA #$30 ; C290: A9 30
|
|
STA APUNOISELENGTH ; C292: 8D 0F 40
|
|
JSR SubCFD12 ; C295: 20 12 FD
|
|
LDX $7A ; C298: A6 7A
|
|
LDA $3B ; C29A: A5 3B
|
|
STA $40,X ; C29C: 95 40
|
|
LDA $38 ; C29E: A5 38
|
|
STA $3E,X ; C2A0: 95 3E
|
|
JSR SubCCA8E ; C2A2: 20 8E CA
|
|
LDA #$09 ; C2A5: A9 09
|
|
JSR SubCFEBF ; C2A7: 20 BF FE
|
|
JSR SpriteOffsetForController ; C2AA: 20 94 C8
|
|
LDA $3B ; C2AD: A5 3B
|
|
STA $0200,X ; C2AF: 9D 00 02
|
|
LDA $38 ; C2B2: A5 38
|
|
STA $0203,X ; C2B4: 9D 03 02
|
|
JMP SubCC383 ; C2B7: 4C 83 C3
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C2BA
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C2BA.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C2BA:
|
|
LDA #$8B ; C2BA: A9 8B
|
|
STA $027D ; C2BC: 8D 7D 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C2BF
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C2BF.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C2BF:
|
|
JMP SubCC380 ; C2BF: 4C 80 C3
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C2C2
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C2C2.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C2C2:
|
|
LDA #$04 ; C2C2: A9 04
|
|
STA APUNOISECTRL ; C2C4: 8D 0C 40
|
|
LDA #$0E ; C2C7: A9 0E
|
|
STA APUNOISEPERIOD ; C2C9: 8D 0E 40
|
|
LDA #$20 ; C2CC: A9 20
|
|
STA APUNOISELENGTH ; C2CE: 8D 0F 40
|
|
LDA #$0A ; C2D1: A9 0A
|
|
JSR SubCFEBF ; C2D3: 20 BF FE
|
|
JMP SubCC380 ; C2D6: 4C 80 C3
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C2D9
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C2D9.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C2D9:
|
|
LDA #$FF ; C2D9: A9 FF
|
|
STA $0280 ; C2DB: 8D 80 02
|
|
STA $0208 ; C2DE: 8D 08 02
|
|
LDA #$08 ; C2E1: A9 08
|
|
JSR SubCFEBF ; C2E3: 20 BF FE
|
|
JSR SubCC907 ; C2E6: 20 07 C9
|
|
LDX $7A ; C2E9: A6 7A
|
|
LDA $78 ; C2EB: A5 78
|
|
STA $40,X ; C2ED: 95 40
|
|
STA $3B ; C2EF: 85 3B
|
|
LDA $79 ; C2F1: A5 79
|
|
STA $3E,X ; C2F3: 95 3E
|
|
STA $38 ; C2F5: 85 38
|
|
JSR SpriteOffsetForController ; C2F7: 20 94 C8
|
|
LDA #$FF ; C2FA: A9 FF
|
|
STA $0200,X ; C2FC: 9D 00 02
|
|
JSR SubCCA8E ; C2FF: 20 8E CA
|
|
JMP SubCC383 ; C302: 4C 83 C3
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC305
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C305.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC305:
|
|
LDX $7A ; C305: A6 7A
|
|
LDA $40,X ; C307: B5 40
|
|
CMP $65 ; C309: C5 65
|
|
BNE Label_C33E ; C30B: D0 31
|
|
LDA $3E,X ; C30D: B5 3E
|
|
CMP $66 ; C30F: C5 66
|
|
BNE Label_C33E ; C311: D0 2B
|
|
JSR SubCC593 ; C313: 20 93 C5
|
|
LDA $7B,X ; C316: B5 7B
|
|
CMP #$02 ; C318: C9 02
|
|
BNE Label_C336 ; C31A: D0 1A
|
|
LDA $7F,X ; C31C: B5 7F
|
|
BNE Label_C336 ; C31E: D0 16
|
|
LDA $40,X ; C320: B5 40
|
|
STA $3B ; C322: 85 3B
|
|
LDA $3E,X ; C324: B5 3E
|
|
STA $38 ; C326: 85 38
|
|
JSR SubCE52F ; C328: 20 2F E5
|
|
JSR SubCC593 ; C32B: 20 93 C5
|
|
LDA $3B ; C32E: A5 3B
|
|
STA $40,X ; C330: 95 40
|
|
LDA $38 ; C332: A5 38
|
|
STA $3E,X ; C334: 95 3E
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C336
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C336.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C336:
|
|
LDA #$FF ; C336: A9 FF
|
|
STA $0280 ; C338: 8D 80 02
|
|
JMP SubCC41B ; C33B: 4C 1B C4
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C33E
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C33E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C33E:
|
|
LDA #$02 ; C33E: A9 02
|
|
STA $7B,X ; C340: 95 7B
|
|
LDA $0D ; C342: A5 0D
|
|
BEQ Label_C369 ; C344: F0 23
|
|
JSR SubCC593 ; C346: 20 93 C5
|
|
LDA $7B,X ; C349: B5 7B
|
|
CMP #$02 ; C34B: C9 02
|
|
BCC SubCC380 ; C34D: 90 31
|
|
LDA $7F,X ; C34F: B5 7F
|
|
BNE Label_C369 ; C351: D0 16
|
|
LDA $40,X ; C353: B5 40
|
|
STA $3B ; C355: 85 3B
|
|
LDA $3E,X ; C357: B5 3E
|
|
STA $38 ; C359: 85 38
|
|
JSR SubCE52F ; C35B: 20 2F E5
|
|
JSR SubCC593 ; C35E: 20 93 C5
|
|
LDA $3B ; C361: A5 3B
|
|
STA $40,X ; C363: 95 40
|
|
LDA $38 ; C365: A5 38
|
|
STA $3E,X ; C367: 95 3E
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C369
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C369.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C369:
|
|
LDX $7A ; C369: A6 7A
|
|
LDA $40,X ; C36B: B5 40
|
|
STA $3B ; C36D: 85 3B
|
|
LDA $3E,X ; C36F: B5 3E
|
|
STA $38 ; C371: 85 38
|
|
JSR SubCE52F ; C373: 20 2F E5
|
|
LDX $7A ; C376: A6 7A
|
|
LDA $3B ; C378: A5 3B
|
|
STA $40,X ; C37A: 95 40
|
|
LDA $38 ; C37C: A5 38
|
|
STA $3E,X ; C37E: 95 3E
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC380
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C380.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC380:
|
|
JSR SubCC907 ; C380: 20 07 C9
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC383
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C383.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC383:
|
|
LDA $0D ; C383: A5 0D
|
|
CMP #$02 ; C385: C9 02
|
|
BNE Label_C3AE ; C387: D0 25
|
|
LDX $7A ; C389: A6 7A
|
|
TXA ; C38B: 8A
|
|
EOR #$01 ; C38C: 49 01
|
|
TAY ; C38E: A8
|
|
LDA a:$007B,Y ; C38F: B9 7B 00
|
|
CMP #$03 ; C392: C9 03
|
|
BNE Label_C3AE ; C394: D0 18
|
|
LDA a:$002C,Y ; C396: B9 2C 00
|
|
CMP $2C,X ; C399: D5 2C
|
|
BEQ Label_C39F ; C39B: F0 02
|
|
BCS Label_C3AE ; C39D: B0 0F
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C39F
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C39F.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C39F:
|
|
TYA ; C39F: 98
|
|
STA $84 ; C3A0: 85 84
|
|
ASL A ; C3A2: 0A
|
|
SEC ; C3A3: 38
|
|
SBC #$01 ; C3A4: E9 01
|
|
CLC ; C3A6: 18
|
|
ADC $14 ; C3A7: 65 14
|
|
STA $14 ; C3A9: 85 14
|
|
JMP SubCC4CB ; C3AB: 4C CB C4
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C3AE
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C3AE.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C3AE:
|
|
JMP SubCC136 ; C3AE: 4C 36 C1
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC3B1
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C3B1.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC3B1:
|
|
LDA $76 ; C3B1: A5 76
|
|
BNE SubCC41B ; C3B3: D0 66
|
|
LDA $4F ; C3B5: A5 4F
|
|
BNE Label_C3BF ; C3B7: D0 06
|
|
JSR SubCC907 ; C3B9: 20 07 C9
|
|
JMP SubCC383 ; C3BC: 4C 83 C3
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C3BF
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C3BF.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C3BF:
|
|
LDX $7A ; C3BF: A6 7A
|
|
LDY #$01 ; C3C1: A0 01
|
|
STY $7B,X ; C3C3: 94 7B
|
|
DEY ; C3C5: 88
|
|
STY $7F,X ; C3C6: 94 7F
|
|
STY PPUMASK ; C3C8: 8C 01 20
|
|
STY $49 ; C3CB: 84 49
|
|
DEY ; C3CD: 88
|
|
STY $0288 ; C3CE: 8C 88 02
|
|
STY $028C ; C3D1: 8C 8C 02
|
|
STY $0290 ; C3D4: 8C 90 02
|
|
JSR DecodeCoursePackage ; C3D7: 20 78 DD
|
|
LDA $49 ; C3DA: A5 49
|
|
STA $4A ; C3DC: 85 4A
|
|
LDA $3B ; C3DE: A5 3B
|
|
SEC ; C3E0: 38
|
|
SBC $67 ; C3E1: E5 67
|
|
STA $6C ; C3E3: 85 6C
|
|
LDA $38 ; C3E5: A5 38
|
|
SEC ; C3E7: 38
|
|
SBC $68 ; C3E8: E5 68
|
|
STA $6B ; C3EA: 85 6B
|
|
JSR SubCD906 ; C3EC: 20 06 D9
|
|
STA $45 ; C3EF: 85 45
|
|
LDA $65 ; C3F1: A5 65
|
|
STA $3B ; C3F3: 85 3B
|
|
LDA $66 ; C3F5: A5 66
|
|
STA $38 ; C3F7: 85 38
|
|
LDA #$80 ; C3F9: A9 80
|
|
STA $3C ; C3FB: 85 3C
|
|
STA $39 ; C3FD: 85 39
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C3FF
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C3FF.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C3FF:
|
|
JSR SubCD48B ; C3FF: 20 8B D4
|
|
JSR SubCD65D ; C402: 20 5D D6
|
|
LDA $52 ; C405: A5 52
|
|
BNE Label_C3FF ; C407: D0 F6
|
|
LDX $7A ; C409: A6 7A
|
|
LDA $3B ; C40B: A5 3B
|
|
STA $40,X ; C40D: 95 40
|
|
LDA $38 ; C40F: A5 38
|
|
STA $3E,X ; C411: 95 3E
|
|
LDA #$0D ; C413: A9 0D
|
|
STA $0141,X ; C415: 9D 41 01
|
|
JMP SubCC380 ; C418: 4C 80 C3
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC41B
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C41B.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC41B:
|
|
LDA #$3F ; C41B: A9 3F
|
|
STA APUPULSE1CTRL ; C41D: 8D 00 40
|
|
LDA #$B9 ; C420: A9 B9
|
|
STA APUPULSE1SWEEP ; C422: 8D 01 40
|
|
LDY #$00 ; C425: A0 00
|
|
STY APUPULSE1TIMERLO ; C427: 8C 02 40
|
|
INY ; C42A: C8
|
|
STY APUPULSE1TIMERHI ; C42B: 8C 03 40
|
|
LDY $7A ; C42E: A4 7A
|
|
LDA #$03 ; C430: A9 03
|
|
STA a:$007B,Y ; C432: 99 7B 00
|
|
JSR SpriteOffsetForController ; C435: 20 94 C8
|
|
LDA #$FF ; C438: A9 FF
|
|
STA $0200,X ; C43A: 9D 00 02
|
|
LDX $7A ; C43D: A6 7A
|
|
LDA $83 ; C43F: A5 83
|
|
SEC ; C441: 38
|
|
SBC $2C,X ; C442: F5 2C
|
|
CLC ; C444: 18
|
|
ADC #$02 ; C445: 69 02
|
|
CMP #$06 ; C447: C9 06
|
|
BCS Label_C44E ; C449: B0 03
|
|
JSR SubCFEBF ; C44B: 20 BF FE
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C44E
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C44E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C44E:
|
|
LDA $0D ; C44E: A5 0D
|
|
BEQ SubCC484 ; C450: F0 32
|
|
LDX $7A ; C452: A6 7A
|
|
TXA ; C454: 8A
|
|
EOR #$01 ; C455: 49 01
|
|
TAY ; C457: A8
|
|
LDA a:$007B,Y ; C458: B9 7B 00
|
|
CMP #$03 ; C45B: C9 03
|
|
BEQ SubCC484 ; C45D: F0 25
|
|
LDA $0D ; C45F: A5 0D
|
|
CMP #$02 ; C461: C9 02
|
|
BNE Label_C481 ; C463: D0 1C
|
|
LDA a:$002C,Y ; C465: B9 2C 00
|
|
CMP $2C,X ; C468: D5 2C
|
|
BCC Label_C481 ; C46A: 90 15
|
|
TXA ; C46C: 8A
|
|
ASL A ; C46D: 0A
|
|
SEC ; C46E: 38
|
|
SBC #$01 ; C46F: E9 01
|
|
CLC ; C471: 18
|
|
ADC $14 ; C472: 65 14
|
|
STA $14 ; C474: 85 14
|
|
TXA ; C476: 8A
|
|
STA $84 ; C477: 85 84
|
|
LDY #$02 ; C479: A0 02
|
|
JSR WaitFrameGroups ; C47B: 20 09 C9
|
|
JMP SubCC4CB ; C47E: 4C CB C4
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C481
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C481.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C481:
|
|
JMP SubCC380 ; C481: 4C 80 C3
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC484
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C484.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC484:
|
|
LDA $0D ; C484: A5 0D
|
|
CMP #$02 ; C486: C9 02
|
|
BEQ Label_C4A7 ; C488: F0 1D
|
|
LDA $14 ; C48A: A5 14
|
|
CLC ; C48C: 18
|
|
ADC $83 ; C48D: 65 83
|
|
STA $14 ; C48F: 85 14
|
|
LDA $0F ; C491: A5 0F
|
|
CLC ; C493: 18
|
|
ADC $2C ; C494: 65 2C
|
|
STA $0F ; C496: 85 0F
|
|
BCC Label_C49C ; C498: 90 02
|
|
INC $10 ; C49A: E6 10
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C49C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C49C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C49C:
|
|
LDA $11 ; C49C: A5 11
|
|
CLC ; C49E: 18
|
|
ADC $2D ; C49F: 65 2D
|
|
STA $11 ; C4A1: 85 11
|
|
BCC Label_C4A7 ; C4A3: 90 02
|
|
INC $12 ; C4A5: E6 12
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C4A7
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C4A7.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C4A7:
|
|
LDY #$02 ; C4A7: A0 02
|
|
JSR WaitFrameGroups ; C4A9: 20 09 C9
|
|
LDA $2C ; C4AC: A5 2C
|
|
CMP $2D ; C4AE: C5 2D
|
|
BEQ SubCC4CB ; C4B0: F0 19
|
|
BCS Label_C4B8 ; C4B2: B0 04
|
|
LDA #$00 ; C4B4: A9 00
|
|
BEQ Label_C4BA ; C4B6: F0 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C4B8
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C4B8.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C4B8:
|
|
LDA #$01 ; C4B8: A9 01
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C4BA
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C4BA.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C4BA:
|
|
STA $84 ; C4BA: 85 84
|
|
LDY $0D ; C4BC: A4 0D
|
|
CPY #$02 ; C4BE: C0 02
|
|
BNE SubCC4CB ; C4C0: D0 09
|
|
ASL A ; C4C2: 0A
|
|
SEC ; C4C3: 38
|
|
SBC #$01 ; C4C4: E9 01
|
|
CLC ; C4C6: 18
|
|
ADC $14 ; C4C7: 65 14
|
|
STA $14 ; C4C9: 85 14
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC4CB
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C4CB.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC4CB:
|
|
JSR SubCC916 ; C4CB: 20 16 C9
|
|
LDA $0D ; C4CE: A5 0D
|
|
CMP #$02 ; C4D0: C9 02
|
|
BNE Label_C4EB ; C4D2: D0 17
|
|
DEC $88 ; C4D4: C6 88
|
|
BPL Label_C4DC ; C4D6: 10 04
|
|
LDA #$00 ; C4D8: A9 00
|
|
STA $88 ; C4DA: 85 88
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C4DC
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C4DC.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C4DC:
|
|
LDA $14 ; C4DC: A5 14
|
|
JSR SubCD9B1 ; C4DE: 20 B1 D9
|
|
STA $19 ; C4E1: 85 19
|
|
LDA $88 ; C4E3: A5 88
|
|
CMP $19 ; C4E5: C5 19
|
|
BPL Label_C4EB ; C4E7: 10 02
|
|
BMI Label_C504 ; C4E9: 30 19
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C4EB
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C4EB.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C4EB:
|
|
INC $2B ; C4EB: E6 2B
|
|
LDA $2B ; C4ED: A5 2B
|
|
CMP #$12 ; C4EF: C9 12
|
|
BCC Label_C4F7 ; C4F1: 90 04
|
|
LDA #$00 ; C4F3: A9 00
|
|
STA $2B ; C4F5: 85 2B
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C4F7
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C4F7.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C4F7:
|
|
LDY $0D ; C4F7: A4 0D
|
|
CPY #$02 ; C4F9: C0 02
|
|
BEQ Label_C501 ; C4FB: F0 04
|
|
CMP #$00 ; C4FD: C9 00
|
|
BEQ Label_C504 ; C4FF: F0 03
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C501
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C501.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C501:
|
|
JMP SubCC0E8 ; C501: 4C E8 C0
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C504
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C504.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C504:
|
|
LDY #$02 ; C504: A0 02
|
|
JSR WaitFrameGroups ; C506: 20 09 C9
|
|
LDA $0D ; C509: A5 0D
|
|
CMP #$02 ; C50B: C9 02
|
|
BNE Label_C51F ; C50D: D0 10
|
|
LDA $14 ; C50F: A5 14
|
|
BMI Label_C517 ; C511: 30 04
|
|
LDA #$0E ; C513: A9 0E
|
|
BNE Label_C519 ; C515: D0 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C517
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C517.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C517:
|
|
LDA #$0D ; C517: A9 0D
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C519
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C519.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C519:
|
|
JSR SubCFEBF ; C519: 20 BF FE
|
|
JSR SubCFF2B ; C51C: 20 2B FF
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C51F
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C51F.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C51F:
|
|
LDA $0D ; C51F: A5 0D
|
|
CMP #$02 ; C521: C9 02
|
|
BEQ Label_C542 ; C523: F0 1D
|
|
LDX #$02 ; C525: A2 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C527
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C527.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C527:
|
|
STX $1F ; C527: 86 1F
|
|
LDY #$12 ; C529: A0 12
|
|
JSR SubCC8F5 ; C52B: 20 F5 C8
|
|
LDA #$16 ; C52E: A9 16
|
|
STA $1A ; C530: 85 1A
|
|
JSR SubCFE72 ; C532: 20 72 FE
|
|
LDY #$0F ; C535: A0 0F
|
|
JSR SubCC8F5 ; C537: 20 F5 C8
|
|
JSR SubCC916 ; C53A: 20 16 C9
|
|
LDX $1F ; C53D: A6 1F
|
|
DEX ; C53F: CA
|
|
BPL Label_C527 ; C540: 10 E5
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C542
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C542.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C542:
|
|
LDA #$0C ; C542: A9 0C
|
|
JSR SubCFEBF ; C544: 20 BF FE
|
|
JSR SubCFF2B ; C547: 20 2B FF
|
|
LDY #$05 ; C54A: A0 05
|
|
JSR WaitFrameGroups ; C54C: 20 09 C9
|
|
LDA $0D ; C54F: A5 0D
|
|
CMP #$02 ; C551: C9 02
|
|
BEQ Label_C575 ; C553: F0 20
|
|
LDA $10 ; C555: A5 10
|
|
BNE Label_C563 ; C557: D0 0A
|
|
LDA $0F ; C559: A5 0F
|
|
CMP $0E ; C55B: C5 0E
|
|
BCS Label_C563 ; C55D: B0 04
|
|
LDA $0F ; C55F: A5 0F
|
|
STA $0E ; C561: 85 0E
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C563
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C563.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C563:
|
|
LDA $0D ; C563: A5 0D
|
|
BEQ Label_C575 ; C565: F0 0E
|
|
LDA $12 ; C567: A5 12
|
|
BCS Label_C575 ; C569: B0 0A
|
|
LDA $11 ; C56B: A5 11
|
|
CMP $0E ; C56D: C5 0E
|
|
BCS Label_C575 ; C56F: B0 04
|
|
LDA $11 ; C571: A5 11
|
|
STA $0E ; C573: 85 0E
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C575
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C575.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C575:
|
|
JSR WaitForFrame ; C575: 20 F3 C8
|
|
JMP InitializeTitleAndGame ; C578: 4C 23 DA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; StrobeAndReadController
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C57B.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
StrobeAndReadController:
|
|
LDA #$01 ; C57B: A9 01
|
|
STA JOY1 ; C57D: 8D 16 40
|
|
LDA #$00 ; C580: A9 00
|
|
STA JOY1 ; C582: 8D 16 40
|
|
RTS ; C585: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC586
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C586.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC586:
|
|
JSR SetPpuAddress ; C586: 20 C1 C8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC589
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C589.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC589:
|
|
TYA ; C589: 98
|
|
PHA ; C58A: 48
|
|
LDY #$07 ; C58B: A0 07
|
|
JSR SubCC599 ; C58D: 20 99 C5
|
|
PLA ; C590: 68
|
|
TAY ; C591: A8
|
|
RTS ; C592: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC593
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C593.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC593:
|
|
LDA $7A ; C593: A5 7A
|
|
EOR #$01 ; C595: 49 01
|
|
TAX ; C597: AA
|
|
RTS ; C598: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC599
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C599.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC599:
|
|
STA PPUDATA ; C599: 8D 07 20
|
|
DEY ; C59C: 88
|
|
BPL SubCC599 ; C59D: 10 FA
|
|
RTS ; C59F: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; GameplayInputNmiCallback
|
|
;
|
|
; Global:
|
|
; Samples the active controller during NMI, updates club and aim selection,
|
|
; rebuilds the related gameplay OAM entries, and joins the common display
|
|
; callback before returning through NmiEpilogue.
|
|
; Local:
|
|
; Reads the serial controller bits from JOY1,X, derives a directional index,
|
|
; applies repeat-latch behavior, wraps the club index through $00-$0D, and
|
|
; updates the low-nibble aim index according to aim_adjust_direction.
|
|
; Parameters:
|
|
; active_controller_index selects JOY1 or JOY2.
|
|
; Returns:
|
|
; Does not RTS. Control reaches GameplayDisplayNmiCallback and NmiEpilogue.
|
|
; Clobbers:
|
|
; A, X, Y, processor flags, controller temporaries, selection fields, and OAM.
|
|
; ---------------------------------------------------------------------------
|
|
GameplayInputNmiCallback:
|
|
JSR StrobeAndReadController ; C5A0: 20 7B C5
|
|
STA $77 ; C5A3: 85 77
|
|
LDX active_controller_index ; C5A5: A6 7A
|
|
LDA JOY1,X ; C5A7: BD 16 40
|
|
AND #$01 ; C5AA: 29 01
|
|
STA primary_action_pressed ; C5AC: 85 2E
|
|
LDA JOY1,X ; C5AE: BD 16 40
|
|
LDA JOY1,X ; C5B1: BD 16 40
|
|
LDA JOY1,X ; C5B4: BD 16 40
|
|
LDY #$03 ; C5B7: A0 03
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ScanDirectionalSerialBits
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C5B9.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
ScanDirectionalSerialBits:
|
|
LDA JOY1,X ; C5B9: BD 16 40
|
|
AND #$01 ; C5BC: 29 01
|
|
BNE StoreDirectionalInputIndex ; C5BE: D0 03
|
|
DEY ; C5C0: 88
|
|
BPL ScanDirectionalSerialBits ; C5C1: 10 F6
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; StoreDirectionalInputIndex
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C5C3.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
StoreDirectionalInputIndex:
|
|
STY directional_input_index ; C5C3: 84 30
|
|
LDA $49 ; C5C5: A5 49
|
|
BEQ HandleClubSelectionInput ; C5C7: F0 04
|
|
LDA #$0E ; C5C9: A9 0E
|
|
BNE RefreshClubSelectionDisplay ; C5CB: D0 28
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; HandleClubSelectionInput
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C5CD.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
HandleClubSelectionInput:
|
|
LDA directional_input_index ; C5CD: A5 30
|
|
BMI ResetDirectionalRepeatLatch ; C5CF: 30 2F
|
|
CMP #$02 ; C5D1: C9 02
|
|
BCC ResetDirectionalRepeatLatch ; C5D3: 90 2B
|
|
LDA directional_repeat_latch ; C5D5: A5 18
|
|
BNE BuildGameplayOam ; C5D7: D0 2B
|
|
INC directional_repeat_latch ; C5D9: E6 18
|
|
LDA directional_input_index ; C5DB: A5 30
|
|
CMP #$02 ; C5DD: C9 02
|
|
BNE WrapClubSelectionIndex ; C5DF: D0 0C
|
|
INC club_selection_index ; C5E1: E6 17
|
|
LDA club_selection_index ; C5E3: A5 17
|
|
CMP #$0E ; C5E5: C9 0E
|
|
BCC RefreshClubSelectionDisplay ; C5E7: 90 0C
|
|
LDA #$00 ; C5E9: A9 00
|
|
BEQ RefreshClubSelectionDisplay ; C5EB: F0 08
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; WrapClubSelectionIndex
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C5ED.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
WrapClubSelectionIndex:
|
|
DEC club_selection_index ; C5ED: C6 17
|
|
LDA club_selection_index ; C5EF: A5 17
|
|
BPL RefreshClubSelectionDisplay ; C5F1: 10 02
|
|
LDA #$0D ; C5F3: A9 0D
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; RefreshClubSelectionDisplay
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C5F5.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
RefreshClubSelectionDisplay:
|
|
STA club_selection_index ; C5F5: 85 17
|
|
JSR SubCC84D ; C5F7: 20 4D C8
|
|
JSR RefreshSequenceSpriteLayout ; C5FA: 20 A8 CA
|
|
JMP BuildGameplayOam ; C5FD: 4C 04 C6
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ResetDirectionalRepeatLatch
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C600.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
ResetDirectionalRepeatLatch:
|
|
LDA #$00 ; C600: A9 00
|
|
STA directional_repeat_latch ; C602: 85 18
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; BuildGameplayOam
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C604.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
BuildGameplayOam:
|
|
LDA #$C8 ; C604: A9 C8
|
|
STA $0278 ; C606: 8D 78 02
|
|
STA $027C ; C609: 8D 7C 02
|
|
LDA #$8B ; C60C: A9 8B
|
|
STA $0279 ; C60E: 8D 79 02
|
|
STA $027D ; C611: 8D 7D 02
|
|
LDA #$03 ; C614: A9 03
|
|
STA $027A ; C616: 8D 7A 02
|
|
STA $027E ; C619: 8D 7E 02
|
|
LDA #$4C ; C61C: A9 4C
|
|
STA $027B ; C61E: 8D 7B 02
|
|
STA $027F ; C621: 8D 7F 02
|
|
STA $32 ; C624: 85 32
|
|
LDA $49 ; C626: A5 49
|
|
BNE HandleAimAdjustmentInput ; C628: D0 03
|
|
JMP HandleAimDirectionChange ; C62A: 4C 7E C6
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; HandleAimAdjustmentInput
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C62D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
HandleAimAdjustmentInput:
|
|
LDA directional_input_index ; C62D: A5 30
|
|
BMI UpdateAimOamEntryLoop ; C62F: 30 11
|
|
LDA directional_input_index ; C631: A5 30
|
|
AND #$02 ; C633: 29 02
|
|
BNE UpdateAimOamEntryLoop ; C635: D0 0B
|
|
LDA directional_input_index ; C637: A5 30
|
|
BNE InitializeAimOamLoop ; C639: D0 05
|
|
INC aim_adjust_direction ; C63B: E6 45
|
|
JMP UpdateAimOamEntryLoop ; C63D: 4C 42 C6
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; InitializeAimOamLoop
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C640.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
InitializeAimOamLoop:
|
|
DEC aim_adjust_direction ; C640: C6 45
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; UpdateAimOamEntryLoop
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C642.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
UpdateAimOamEntryLoop:
|
|
LDX #$00 ; C642: A2 00
|
|
STX $39 ; C644: 86 39
|
|
STX $3C ; C646: 86 3C
|
|
LDA $78 ; C648: A5 78
|
|
STA $3B ; C64A: 85 3B
|
|
LDA $79 ; C64C: A5 79
|
|
STA $38 ; C64E: 85 38
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; PositionAimOamEntries
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C650.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
PositionAimOamEntries:
|
|
JSR SubCD48B ; C650: 20 8B D4
|
|
INX ; C653: E8
|
|
CPX #$10 ; C654: E0 10
|
|
BCC PositionAimOamEntries ; C656: 90 F8
|
|
LDY $3B ; C658: A4 3B
|
|
DEY ; C65A: 88
|
|
DEY ; C65B: 88
|
|
STY $020C ; C65C: 8C 0C 02
|
|
LDY $38 ; C65F: A4 38
|
|
DEY ; C661: 88
|
|
DEY ; C662: 88
|
|
STY $020F ; C663: 8C 0F 02
|
|
LDA #$DC ; C666: A9 DC
|
|
STA $020D ; C668: 8D 0D 02
|
|
LDA #$03 ; C66B: A9 03
|
|
STA $020E ; C66D: 8D 0E 02
|
|
LDA $78 ; C670: A5 78
|
|
STA $3B ; C672: 85 3B
|
|
LDA $79 ; C674: A5 79
|
|
STA $38 ; C676: 85 38
|
|
JSR SubCC721 ; C678: 20 21 C7
|
|
JMP GameplayDisplayNmiCallback ; C67B: 4C C8 C6
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; HandleAimDirectionChange
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C67E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
HandleAimDirectionChange:
|
|
LDA directional_input_index ; C67E: A5 30
|
|
BPL InitializeAimDirection ; C680: 10 04
|
|
LDA #$00 ; C682: A9 00
|
|
STA aim_adjust_direction ; C684: 85 45
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; InitializeAimDirection
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C686.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
InitializeAimDirection:
|
|
LDA aim_adjust_direction ; C686: A5 45
|
|
BNE StoreWrappedAimAngle ; C688: D0 19
|
|
LDA directional_input_index ; C68A: A5 30
|
|
AND #$02 ; C68C: 29 02
|
|
BNE StoreWrappedAimAngle ; C68E: D0 13
|
|
LDA #$01 ; C690: A9 01
|
|
STA aim_adjust_direction ; C692: 85 45
|
|
LDA directional_input_index ; C694: A5 30
|
|
BNE DecrementAimAngle ; C696: D0 07
|
|
INC aim_angle_index ; C698: E6 44
|
|
INC $77 ; C69A: E6 77
|
|
JMP StoreWrappedAimAngle ; C69C: 4C A3 C6
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; DecrementAimAngle
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C69F.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
DecrementAimAngle:
|
|
DEC aim_angle_index ; C69F: C6 44
|
|
INC $77 ; C6A1: E6 77
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; StoreWrappedAimAngle
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C6A3.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
StoreWrappedAimAngle:
|
|
LDA aim_angle_index ; C6A3: A5 44
|
|
AND #$0F ; C6A5: 29 0F
|
|
STA aim_angle_index ; C6A7: 85 44
|
|
TAY ; C6A9: A8
|
|
LDA $C80D,Y ; C6AA: B9 0D C8
|
|
CLC ; C6AD: 18
|
|
ADC $3B ; C6AE: 65 3B
|
|
STA $020C ; C6B0: 8D 0C 02
|
|
LDA $C81D,Y ; C6B3: B9 1D C8
|
|
STA $020D ; C6B6: 8D 0D 02
|
|
LDA $C82D,Y ; C6B9: B9 2D C8
|
|
STA $020E ; C6BC: 8D 0E 02
|
|
LDA $C83D,Y ; C6BF: B9 3D C8
|
|
CLC ; C6C2: 18
|
|
ADC $38 ; C6C3: 65 38
|
|
STA $020F ; C6C5: 8D 0F 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; GameplayDisplayNmiCallback
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C6C8.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
GameplayDisplayNmiCallback:
|
|
LDA club_selection_index ; C6C8: A5 17
|
|
BNE ShowAnimationMarker ; C6CA: D0 08
|
|
INC animation_tick_counter ; C6CC: E6 8E
|
|
LDA animation_tick_counter ; C6CE: A5 8E
|
|
AND #$08 ; C6D0: 29 08
|
|
BNE SelectAnimationMarkerTile ; C6D2: D0 04
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ShowAnimationMarker
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C6D4.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
ShowAnimationMarker:
|
|
LDA #$FF ; C6D4: A9 FF
|
|
BNE WriteAnimationMarkerOam ; C6D6: D0 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SelectAnimationMarkerTile
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C6D8.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SelectAnimationMarkerTile:
|
|
LDA #$C0 ; C6D8: A9 C0
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; WriteAnimationMarkerOam
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C6DA.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
WriteAnimationMarkerOam:
|
|
STA $0284 ; C6DA: 8D 84 02
|
|
LDA #animation_frame_index ; C6DD: A9 8F
|
|
STA $0285 ; C6DF: 8D 85 02
|
|
LDA #$03 ; C6E2: A9 03
|
|
STA $0286 ; C6E4: 8D 86 02
|
|
LDA #$4B ; C6E7: A9 4B
|
|
STA $0287 ; C6E9: 8D 87 02
|
|
LDA animation_frame_index ; C6EC: A5 8F
|
|
CMP #$19 ; C6EE: C9 19
|
|
BCS FinishGameplayNmi ; C6F0: B0 29
|
|
INC animation_frame_index ; C6F2: E6 8F
|
|
LDA animation_frame_index ; C6F4: A5 8F
|
|
AND #directional_repeat_latch ; C6F6: 29 18
|
|
LSR A ; C6F8: 4A
|
|
LSR A ; C6F9: 4A
|
|
LSR A ; C6FA: 4A
|
|
TAY ; C6FB: A8
|
|
LDA $C71E,Y ; C6FC: B9 1E C7
|
|
STA $0215 ; C6FF: 8D 15 02
|
|
LDA animation_frame_index ; C702: A5 8F
|
|
CMP #directional_repeat_latch ; C704: C9 18
|
|
BCC SelectSecondaryMarkerTile ; C706: 90 04
|
|
LDA #$FF ; C708: A9 FF
|
|
BNE WriteSecondaryMarkerOam ; C70A: D0 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SelectSecondaryMarkerTile
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C70C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SelectSecondaryMarkerTile:
|
|
LDA #$B8 ; C70C: A9 B8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; WriteSecondaryMarkerOam
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C70E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
WriteSecondaryMarkerOam:
|
|
STA $0214 ; C70E: 8D 14 02
|
|
LDA #$03 ; C711: A9 03
|
|
STA $0216 ; C713: 8D 16 02
|
|
LDA #$4B ; C716: A9 4B
|
|
STA $0217 ; C718: 8D 17 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; FinishGameplayNmi
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C71B.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
FinishGameplayNmi:
|
|
JMP NmiEpilogue ; C71B: 4C B8 C0
|
|
.incbin "prg.bin", $071E, $0003 ; C71E-C720: unclassified/data
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC721
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C721.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC721:
|
|
JSR SubCD9C7 ; C721: 20 C7 D9
|
|
JSR SubCF931 ; C724: 20 31 F9
|
|
LDA $5E ; C727: A5 5E
|
|
CMP #$18 ; C729: C9 18
|
|
BCC Label_C72F ; C72B: 90 02
|
|
LDA #$18 ; C72D: A9 18
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C72F
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C72F.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C72F:
|
|
STA $75 ; C72F: 85 75
|
|
LDY #$D7 ; C731: A0 D7
|
|
CMP #$14 ; C733: C9 14
|
|
BCS Label_C73F ; C735: B0 08
|
|
LDY #$D4 ; C737: A0 D4
|
|
CMP #$0A ; C739: C9 0A
|
|
BCS Label_C73F ; C73B: B0 02
|
|
LDY #$8C ; C73D: A0 8C
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C73F
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C73F.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C73F:
|
|
JSR SubCC752 ; C73F: 20 52 C7
|
|
LDA $0289 ; C742: AD 89 02
|
|
CMP #$8C ; C745: C9 8C
|
|
BNE Label_C751 ; C747: D0 08
|
|
LDA #$FF ; C749: A9 FF
|
|
STA $0288 ; C74B: 8D 88 02
|
|
STA $028C ; C74E: 8D 8C 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C751
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C751.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C751:
|
|
RTS ; C751: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC752
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C752.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC752:
|
|
SEC ; C752: 38
|
|
SBC #$A5 ; C753: E9 A5
|
|
EOR #$FF ; C755: 49 FF
|
|
STA $0288 ; C757: 8D 88 02
|
|
ADC #$07 ; C75A: 69 07
|
|
STA $028C ; C75C: 8D 8C 02
|
|
ADC #$08 ; C75F: 69 08
|
|
STA $0290 ; C761: 8D 90 02
|
|
STY $0289 ; C764: 8C 89 02
|
|
INY ; C767: C8
|
|
STY $028D ; C768: 8C 8D 02
|
|
INY ; C76B: C8
|
|
STY $0291 ; C76C: 8C 91 02
|
|
LDA #$01 ; C76F: A9 01
|
|
STA $028A ; C771: 8D 8A 02
|
|
STA $028E ; C774: 8D 8E 02
|
|
STA $0292 ; C777: 8D 92 02
|
|
LDA $74 ; C77A: A5 74
|
|
STA $028B ; C77C: 8D 8B 02
|
|
STA $028F ; C77F: 8D 8F 02
|
|
STA $0293 ; C782: 8D 93 02
|
|
RTS ; C785: 60
|
|
.incbin "prg.bin", $0786, $00C7 ; C786-C84C: unclassified/data
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC84D
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C84D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC84D:
|
|
LDX #$23 ; C84D: A2 23
|
|
LDA #$4A ; C84F: A9 4A
|
|
JSR SetPpuAddress ; C851: 20 C1 C8
|
|
LDA $17 ; C854: A5 17
|
|
ASL A ; C856: 0A
|
|
TAY ; C857: A8
|
|
LDA $C78B,Y ; C858: B9 8B C7
|
|
STA PPUDATA ; C85B: 8D 07 20
|
|
LDA $C78C,Y ; C85E: B9 8C C7
|
|
STA PPUDATA ; C861: 8D 07 20
|
|
LDX #$23 ; C864: A2 23
|
|
LDA #$04 ; C866: A9 04
|
|
JSR SetPpuAddress ; C868: 20 C1 C8
|
|
LDX $17 ; C86B: A6 17
|
|
LDY $C7A9,X ; C86D: BC A9 C7
|
|
LDX #$00 ; C870: A2 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C872
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C872.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C872:
|
|
LDA $C7B8,Y ; C872: B9 B8 C7
|
|
STA PPUDATA ; C875: 8D 07 20
|
|
INY ; C878: C8
|
|
INX ; C879: E8
|
|
CPX #$0A ; C87A: E0 0A
|
|
BCC Label_C872 ; C87C: 90 F4
|
|
JMP SetPpuScrollAndMask ; C87E: 4C 9D C8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; WaitForFramePreservingY
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C881.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
WaitForFramePreservingY:
|
|
TYA ; C881: 98
|
|
PHA ; C882: 48
|
|
JSR WaitForFrame ; C883: 20 F3 C8
|
|
PLA ; C886: 68
|
|
TAY ; C887: A8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; InstallNmiCallback
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C888.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
InstallNmiCallback:
|
|
LDA ppu_ctrl_shadow ; C888: A5 00
|
|
AND #$7F ; C88A: 29 7F
|
|
STA PPUCTRL ; C88C: 8D 00 20
|
|
STY nmi_vector_lo ; C88F: 84 02
|
|
STX nmi_vector_hi ; C891: 86 03
|
|
RTS ; C893: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SpriteOffsetForController
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C894.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SpriteOffsetForController:
|
|
LDA $7A ; C894: A5 7A
|
|
ASL A ; C896: 0A
|
|
ASL A ; C897: 0A
|
|
TAX ; C898: AA
|
|
RTS ; C899: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC89A
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C89A.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC89A:
|
|
JSR WaitForFrame ; C89A: 20 F3 C8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SetPpuScrollAndMask
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C89D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SetPpuScrollAndMask:
|
|
LDA #$20 ; C89D: A9 20
|
|
STA PPUADDR ; C89F: 8D 06 20
|
|
LDA #$00 ; C8A2: A9 00
|
|
STA PPUADDR ; C8A4: 8D 06 20
|
|
STA PPUSCROLL ; C8A7: 8D 05 20
|
|
LDA #$FF ; C8AA: A9 FF
|
|
STA PPUSCROLL ; C8AC: 8D 05 20
|
|
LDA $01 ; C8AF: A5 01
|
|
STA PPUMASK ; C8B1: 8D 01 20
|
|
RTS ; C8B4: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; RestorePpuCtrlShadow
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C8B5.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
RestorePpuCtrlShadow:
|
|
LDA ppu_ctrl_shadow ; C8B5: A5 00
|
|
STA PPUCTRL ; C8B7: 8D 00 20
|
|
RTS ; C8BA: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; MultiplyABy32
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C8BB.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
MultiplyABy32:
|
|
ASL A ; C8BB: 0A
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; MultiplyBy32
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C8BC.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
MultiplyBy32:
|
|
ASL A ; C8BC: 0A
|
|
ASL A ; C8BD: 0A
|
|
ASL A ; C8BE: 0A
|
|
ASL A ; C8BF: 0A
|
|
RTS ; C8C0: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SetPpuAddress
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C8C1.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SetPpuAddress:
|
|
STX PPUADDR ; C8C1: 8E 06 20
|
|
STA PPUADDR ; C8C4: 8D 06 20
|
|
RTS ; C8C7: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ClearNametableAndOam
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C8C8.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
ClearNametableAndOam:
|
|
LDA ppu_mask_shadow ; C8C8: A5 01
|
|
AND #$E7 ; C8CA: 29 E7
|
|
STA PPUMASK ; C8CC: 8D 01 20
|
|
LDX #$20 ; C8CF: A2 20
|
|
LDA #$00 ; C8D1: A9 00
|
|
JSR SetPpuAddress ; C8D3: 20 C1 C8
|
|
TAX ; C8D6: AA
|
|
LDA #$9D ; C8D7: A9 9D
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C8D9
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C8D9.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C8D9:
|
|
STA PPUDATA ; C8D9: 8D 07 20
|
|
STA PPUDATA ; C8DC: 8D 07 20
|
|
STA PPUDATA ; C8DF: 8D 07 20
|
|
STA PPUDATA ; C8E2: 8D 07 20
|
|
INX ; C8E5: E8
|
|
BNE Label_C8D9 ; C8E6: D0 F1
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ClearOamShadowLoop
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C8E8.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
ClearOamShadowLoop:
|
|
LDX #$00 ; C8E8: A2 00
|
|
LDA #$FF ; C8EA: A9 FF
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C8EC
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C8EC.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C8EC:
|
|
STA $0200,X ; C8EC: 9D 00 02
|
|
INX ; C8EF: E8
|
|
BNE Label_C8EC ; C8F0: D0 FA
|
|
RTS ; C8F2: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; WaitForFrame
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C8F3.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
WaitForFrame:
|
|
LDY #$01 ; C8F3: A0 01
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC8F5
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C8F5.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC8F5:
|
|
LDA #$00 ; C8F5: A9 00
|
|
STA $0C ; C8F7: 85 0C
|
|
STA $08 ; C8F9: 85 08
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C8FB
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C8FB.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C8FB:
|
|
LDA $0C ; C8FB: A5 0C
|
|
BNE Label_C906 ; C8FD: D0 07
|
|
LDA $08 ; C8FF: A5 08
|
|
BEQ Label_C8FB ; C901: F0 F8
|
|
DEY ; C903: 88
|
|
BNE SubCC8F5 ; C904: D0 EF
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C906
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C906.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C906:
|
|
RTS ; C906: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC907
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C907.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC907:
|
|
LDY #$01 ; C907: A0 01
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; WaitFrameGroups
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C909.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
WaitFrameGroups:
|
|
STY $0B ; C909: 84 0B
|
|
LDY #$3C ; C90B: A0 3C
|
|
JSR SubCC8F5 ; C90D: 20 F5 C8
|
|
LDY $0B ; C910: A4 0B
|
|
DEY ; C912: 88
|
|
BNE WaitFrameGroups ; C913: D0 F4
|
|
RTS ; C915: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC916
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C916.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC916:
|
|
JSR WaitForFrame ; C916: 20 F3 C8
|
|
LDA #$21 ; C919: A9 21
|
|
STA $04 ; C91B: 85 04
|
|
LDA #$24 ; C91D: A9 24
|
|
STA $05 ; C91F: 85 05
|
|
LDX #$00 ; C921: A2 00
|
|
JSR SubCC946 ; C923: 20 46 C9
|
|
LDA $82 ; C926: A5 82
|
|
BEQ Label_C931 ; C928: F0 07
|
|
LDA $0143 ; C92A: AD 43 01
|
|
BEQ Label_C945 ; C92D: F0 16
|
|
BNE Label_C935 ; C92F: D0 04
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C931
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C931.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C931:
|
|
LDA $0D ; C931: A5 0D
|
|
BEQ Label_C945 ; C933: F0 10
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C935
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C935.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C935:
|
|
JSR WaitForFrame ; C935: 20 F3 C8
|
|
LDA #$21 ; C938: A9 21
|
|
STA $04 ; C93A: 85 04
|
|
LDA #$64 ; C93C: A9 64
|
|
STA $05 ; C93E: 85 05
|
|
LDX #$01 ; C940: A2 01
|
|
JSR SubCC946 ; C942: 20 46 C9
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C945
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C945.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C945:
|
|
RTS ; C945: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCC946
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C946.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCC946:
|
|
LDA $04 ; C946: A5 04
|
|
STA PPUADDR ; C948: 8D 06 20
|
|
LDA $05 ; C94B: A5 05
|
|
STA PPUADDR ; C94D: 8D 06 20
|
|
LDA $2C,X ; C950: B5 2C
|
|
STA $19 ; C952: 85 19
|
|
LDA #$00 ; C954: A9 00
|
|
STA $1A ; C956: 85 1A
|
|
JSR SubCCA30 ; C958: 20 30 CA
|
|
JSR SetPpuScrollAndMask ; C95B: 20 9D C8
|
|
LDA $82 ; C95E: A5 82
|
|
BEQ Label_C96B ; C960: F0 09
|
|
LDA $0143 ; C962: AD 43 01
|
|
CMP #$02 ; C965: C9 02
|
|
BEQ Label_C9E6 ; C967: F0 7D
|
|
BNE Label_C971 ; C969: D0 06
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C96B
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C96B.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C96B:
|
|
LDA $0D ; C96B: A5 0D
|
|
CMP #$02 ; C96D: C9 02
|
|
BEQ Label_C9E6 ; C96F: F0 75
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C971
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C971.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C971:
|
|
JSR WaitForFrame ; C971: 20 F3 C8
|
|
LDA $04 ; C974: A5 04
|
|
STA PPUADDR ; C976: 8D 06 20
|
|
LDA $05 ; C979: A5 05
|
|
CLC ; C97B: 18
|
|
ADC #$03 ; C97C: 69 03
|
|
STA PPUADDR ; C97E: 8D 06 20
|
|
TXA ; C981: 8A
|
|
ASL A ; C982: 0A
|
|
TAX ; C983: AA
|
|
LDA $10,X ; C984: B5 10
|
|
BNE Label_C998 ; C986: D0 10
|
|
LDA $0F,X ; C988: B5 0F
|
|
CMP $14 ; C98A: C5 14
|
|
BNE Label_C998 ; C98C: D0 0A
|
|
LDA #$00 ; C98E: A9 00
|
|
STA $19 ; C990: 85 19
|
|
STA $1A ; C992: 85 1A
|
|
LDA #$A8 ; C994: A9 A8
|
|
BNE Label_C9BA ; C996: D0 22
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C998
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C998.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C998:
|
|
LDA $0F,X ; C998: B5 0F
|
|
SEC ; C99A: 38
|
|
SBC $14 ; C99B: E5 14
|
|
STA $19 ; C99D: 85 19
|
|
LDA $10,X ; C99F: B5 10
|
|
SBC #$00 ; C9A1: E9 00
|
|
STA $1A ; C9A3: 85 1A
|
|
BCC Label_C9AB ; C9A5: 90 04
|
|
LDA #$A1 ; C9A7: A9 A1
|
|
BNE Label_C9BA ; C9A9: D0 0F
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C9AB
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C9AB.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C9AB:
|
|
LDA $14 ; C9AB: A5 14
|
|
SEC ; C9AD: 38
|
|
SBC $0F,X ; C9AE: F5 0F
|
|
STA $19 ; C9B0: 85 19
|
|
LDA #$00 ; C9B2: A9 00
|
|
SBC $10,X ; C9B4: F5 10
|
|
STA $1A ; C9B6: 85 1A
|
|
LDA #$A2 ; C9B8: A9 A2
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C9BA
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C9BA.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C9BA:
|
|
STA PPUDATA ; C9BA: 8D 07 20
|
|
JSR SubCCA30 ; C9BD: 20 30 CA
|
|
LDA #$9D ; C9C0: A9 9D
|
|
STA PPUDATA ; C9C2: 8D 07 20
|
|
JSR SetPpuScrollAndMask ; C9C5: 20 9D C8
|
|
JSR WaitForFrame ; C9C8: 20 F3 C8
|
|
LDA $04 ; C9CB: A5 04
|
|
STA PPUADDR ; C9CD: 8D 06 20
|
|
LDA $05 ; C9D0: A5 05
|
|
CLC ; C9D2: 18
|
|
ADC #$08 ; C9D3: 69 08
|
|
STA PPUADDR ; C9D5: 8D 06 20
|
|
LDA $0F,X ; C9D8: B5 0F
|
|
STA $19 ; C9DA: 85 19
|
|
LDA $10,X ; C9DC: B5 10
|
|
STA $1A ; C9DE: 85 1A
|
|
JSR SubCCA30 ; C9E0: 20 30 CA
|
|
JMP SetPpuScrollAndMask ; C9E3: 4C 9D C8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_C9E6
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $C9E6.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_C9E6:
|
|
JSR WaitForFrame ; C9E6: 20 F3 C8
|
|
LDA $04 ; C9E9: A5 04
|
|
STA PPUADDR ; C9EB: 8D 06 20
|
|
LDA $05 ; C9EE: A5 05
|
|
CLC ; C9F0: 18
|
|
ADC #$05 ; C9F1: 69 05
|
|
STA PPUADDR ; C9F3: 8D 06 20
|
|
LDA #$00 ; C9F6: A9 00
|
|
STA $1A ; C9F8: 85 1A
|
|
CPX #$00 ; C9FA: E0 00
|
|
BEQ Label_CA06 ; C9FC: F0 08
|
|
LDA $14 ; C9FE: A5 14
|
|
BEQ Label_CA26 ; CA00: F0 24
|
|
BMI Label_CA26 ; CA02: 30 22
|
|
BPL Label_CA0F ; CA04: 10 09
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CA06
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CA06.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CA06:
|
|
LDA $14 ; CA06: A5 14
|
|
BEQ Label_CA26 ; CA08: F0 1C
|
|
BPL Label_CA26 ; CA0A: 10 1A
|
|
JSR SubCD9B1 ; CA0C: 20 B1 D9
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CA0F
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CA0F.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CA0F:
|
|
STA $19 ; CA0F: 85 19
|
|
JSR SubCCA30 ; CA11: 20 30 CA
|
|
LDA #$9D ; CA14: A9 9D
|
|
STA PPUDATA ; CA16: 8D 07 20
|
|
LDA #$1E ; CA19: A9 1E
|
|
STA PPUDATA ; CA1B: 8D 07 20
|
|
LDA #$19 ; CA1E: A9 19
|
|
STA PPUDATA ; CA20: 8D 07 20
|
|
JMP SetPpuScrollAndMask ; CA23: 4C 9D C8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CA26
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CA26.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CA26:
|
|
LDA #$00 ; CA26: A9 00
|
|
STA $19 ; CA28: 85 19
|
|
JSR SubCCA30 ; CA2A: 20 30 CA
|
|
JMP SetPpuScrollAndMask ; CA2D: 4C 9D C8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCCA30
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CA30.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCCA30:
|
|
TXA ; CA30: 8A
|
|
PHA ; CA31: 48
|
|
LDA #$00 ; CA32: A9 00
|
|
STA $1B ; CA34: 85 1B
|
|
STA $1C ; CA36: 85 1C
|
|
STA $1D ; CA38: 85 1D
|
|
LDX #$02 ; CA3A: A2 02
|
|
LDA #$64 ; CA3C: A9 64
|
|
JSR SubCCA53 ; CA3E: 20 53 CA
|
|
DEX ; CA41: CA
|
|
LDA #$0A ; CA42: A9 0A
|
|
JSR SubCCA53 ; CA44: 20 53 CA
|
|
DEX ; CA47: CA
|
|
LDA #$01 ; CA48: A9 01
|
|
JSR SubCCA53 ; CA4A: 20 53 CA
|
|
JSR SubCCA70 ; CA4D: 20 70 CA
|
|
PLA ; CA50: 68
|
|
TAX ; CA51: AA
|
|
RTS ; CA52: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCCA53
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CA53.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCCA53:
|
|
STA $1E ; CA53: 85 1E
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCCA55
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CA55.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCCA55:
|
|
LDA $1A ; CA55: A5 1A
|
|
BNE Label_CA60 ; CA57: D0 07
|
|
LDA $19 ; CA59: A5 19
|
|
CMP $1E ; CA5B: C5 1E
|
|
BCS Label_CA60 ; CA5D: B0 01
|
|
RTS ; CA5F: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CA60
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CA60.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CA60:
|
|
INC $1B,X ; CA60: F6 1B
|
|
LDA $19 ; CA62: A5 19
|
|
SEC ; CA64: 38
|
|
SBC $1E ; CA65: E5 1E
|
|
STA $19 ; CA67: 85 19
|
|
BCS SubCCA55 ; CA69: B0 EA
|
|
DEC $1A ; CA6B: C6 1A
|
|
JMP SubCCA55 ; CA6D: 4C 55 CA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCCA70
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CA70.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCCA70:
|
|
LDA $1D ; CA70: A5 1D
|
|
STA $13 ; CA72: 85 13
|
|
BNE Label_CA78 ; CA74: D0 02
|
|
BEQ Label_CA7B ; CA76: F0 03
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CA78
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CA78.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CA78:
|
|
STA PPUDATA ; CA78: 8D 07 20
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CA7B
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CA7B.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CA7B:
|
|
LDA $1C ; CA7B: A5 1C
|
|
BNE Label_CA85 ; CA7D: D0 06
|
|
LDY $13 ; CA7F: A4 13
|
|
BNE Label_CA85 ; CA81: D0 02
|
|
BEQ Label_CA88 ; CA83: F0 03
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CA85
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CA85.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CA85:
|
|
STA PPUDATA ; CA85: 8D 07 20
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CA88
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CA88.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CA88:
|
|
LDA $1B ; CA88: A5 1B
|
|
STA PPUDATA ; CA8A: 8D 07 20
|
|
RTS ; CA8D: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCCA8E
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CA8E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCCA8E:
|
|
LDX $7A ; CA8E: A6 7A
|
|
INC $2C,X ; CA90: F6 2C
|
|
LDA $2C,X ; CA92: B5 2C
|
|
CMP #$63 ; CA94: C9 63
|
|
BCC Label_CA9C ; CA96: 90 04
|
|
LDA #$63 ; CA98: A9 63
|
|
STA $2C,X ; CA9A: 95 2C
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CA9C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CA9C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CA9C:
|
|
RTS ; CA9C: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCCA9D
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CA9D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCCA9D:
|
|
LDY #$5B ; CA9D: A0 5B
|
|
LDA #$FF ; CA9F: A9 FF
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CAA1
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CAA1.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CAA1:
|
|
STA $0218,Y ; CAA1: 99 18 02
|
|
DEY ; CAA4: 88
|
|
BPL Label_CAA1 ; CAA5: 10 FA
|
|
RTS ; CAA7: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; RefreshSequenceSpriteLayout
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CAA8.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
RefreshSequenceSpriteLayout:
|
|
JSR SubCCA9D ; CAA8: 20 9D CA
|
|
LDY $17 ; CAAB: A4 17
|
|
LDA $C7FE,Y ; CAAD: B9 FE C7
|
|
STA $33 ; CAB0: 85 33
|
|
CLC ; CAB2: 18
|
|
ADC #$10 ; CAB3: 69 10
|
|
STA $0273 ; CAB5: 8D 73 02
|
|
LDA #$90 ; CAB8: A9 90
|
|
STA $0270 ; CABA: 8D 70 02
|
|
LDA #$0F ; CABD: A9 0F
|
|
STA $0271 ; CABF: 8D 71 02
|
|
LDA #$01 ; CAC2: A9 01
|
|
STA $0272 ; CAC4: 8D 72 02
|
|
LDA $CC15,Y ; CAC7: B9 15 CC
|
|
STA $16 ; CACA: 85 16
|
|
LDY $15 ; CACC: A4 15
|
|
LDA $16 ; CACE: A5 16
|
|
CMP #$04 ; CAD0: C9 04
|
|
BEQ Label_CB2C ; CAD2: F0 58
|
|
CMP #$02 ; CAD4: C9 02
|
|
BCC Label_CAEB ; CAD6: 90 13
|
|
LDX $CD85,Y ; CAD8: BE 85 CD
|
|
CPX #$02 ; CADB: E0 02
|
|
BCS Label_CAEB ; CADD: B0 0C
|
|
LDA $16 ; CADF: A5 16
|
|
CMP #$02 ; CAE1: C9 02
|
|
BNE Label_CAE8 ; CAE3: D0 03
|
|
JMP SubCCB63 ; CAE5: 4C 63 CB
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CAE8
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CAE8.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CAE8:
|
|
JMP SubCCB97 ; CAE8: 4C 97 CB
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CAEB
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CAEB.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CAEB:
|
|
LDX $CD85,Y ; CAEB: BE 85 CD
|
|
LDY $CD93,X ; CAEE: BC 93 CD
|
|
INX ; CAF1: E8
|
|
LDA $CD93,X ; CAF2: BD 93 CD
|
|
STA $21 ; CAF5: 85 21
|
|
LDX #$18 ; CAF7: A2 18
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CAF9
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CAF9.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CAF9:
|
|
LDA #$78 ; CAF9: A9 78
|
|
CLC ; CAFB: 18
|
|
ADC $CDBA,Y ; CAFC: 79 BA CD
|
|
STA $0200,X ; CAFF: 9D 00 02
|
|
LDA $16 ; CB02: A5 16
|
|
BNE Label_CB0C ; CB04: D0 06
|
|
LDA $CDD6,Y ; CB06: B9 D6 CD
|
|
JMP SubCCB0F ; CB09: 4C 0F CB
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CB0C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CB0C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CB0C:
|
|
LDA $CDF2,Y ; CB0C: B9 F2 CD
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCCB0F
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CB0F.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCCB0F:
|
|
STA $0201,X ; CB0F: 9D 01 02
|
|
LDA #$03 ; CB12: A9 03
|
|
STA $0202,X ; CB14: 9D 02 02
|
|
LDA $33 ; CB17: A5 33
|
|
SEC ; CB19: 38
|
|
SBC #$0C ; CB1A: E9 0C
|
|
CLC ; CB1C: 18
|
|
ADC $CD9E,Y ; CB1D: 79 9E CD
|
|
STA $0203,X ; CB20: 9D 03 02
|
|
JSR SubCD4F1 ; CB23: 20 F1 D4
|
|
CPY $21 ; CB26: C4 21
|
|
BCC Label_CAF9 ; CB28: 90 CF
|
|
BCS SubCCB60 ; CB2A: B0 34
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CB2C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CB2C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CB2C:
|
|
LDX $CE3B,Y ; CB2C: BE 3B CE
|
|
LDY $CE41,X ; CB2F: BC 41 CE
|
|
INX ; CB32: E8
|
|
LDA $CE41,X ; CB33: BD 41 CE
|
|
STA $21 ; CB36: 85 21
|
|
LDX #$18 ; CB38: A2 18
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CB3A
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CB3A.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CB3A:
|
|
LDA #$A7 ; CB3A: A9 A7
|
|
CLC ; CB3C: 18
|
|
ADC $CE50,Y ; CB3D: 79 50 CE
|
|
STA $0200,X ; CB40: 9D 00 02
|
|
LDA $CE5A,Y ; CB43: B9 5A CE
|
|
STA $0201,X ; CB46: 9D 01 02
|
|
LDA #$03 ; CB49: A9 03
|
|
STA $0202,X ; CB4B: 9D 02 02
|
|
LDA $33 ; CB4E: A5 33
|
|
CLC ; CB50: 18
|
|
ADC #$03 ; CB51: 69 03
|
|
ADC $CE46,Y ; CB53: 79 46 CE
|
|
STA $0203,X ; CB56: 9D 03 02
|
|
JSR SubCD4F1 ; CB59: 20 F1 D4
|
|
CPY $21 ; CB5C: C4 21
|
|
BCC Label_CB3A ; CB5E: 90 DA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCCB60
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CB60.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCCB60:
|
|
JMP SubCCBCB ; CB60: 4C CB CB
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCCB63
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CB63.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCCB63:
|
|
LDY $CE0E,X ; CB63: BC 0E CE
|
|
INX ; CB66: E8
|
|
LDA $CE0E,X ; CB67: BD 0E CE
|
|
STA $21 ; CB6A: 85 21
|
|
LDX #$18 ; CB6C: A2 18
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CB6E
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CB6E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CB6E:
|
|
LDA #$A6 ; CB6E: A9 A6
|
|
CLC ; CB70: 18
|
|
ADC $CE18,Y ; CB71: 79 18 CE
|
|
STA $0200,X ; CB74: 9D 00 02
|
|
LDA $CE1F,Y ; CB77: B9 1F CE
|
|
STA $0201,X ; CB7A: 9D 01 02
|
|
LDA #$03 ; CB7D: A9 03
|
|
STA $0202,X ; CB7F: 9D 02 02
|
|
LDA $33 ; CB82: A5 33
|
|
CLC ; CB84: 18
|
|
ADC #$13 ; CB85: 69 13
|
|
ADC $CE11,Y ; CB87: 79 11 CE
|
|
STA $0203,X ; CB8A: 9D 03 02
|
|
JSR SubCD4F1 ; CB8D: 20 F1 D4
|
|
CPY $21 ; CB90: C4 21
|
|
BCC Label_CB6E ; CB92: 90 DA
|
|
JMP SubCCB60 ; CB94: 4C 60 CB
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCCB97
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CB97.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCCB97:
|
|
LDY $CE0E,X ; CB97: BC 0E CE
|
|
INX ; CB9A: E8
|
|
LDA $CE0E,X ; CB9B: BD 0E CE
|
|
STA $21 ; CB9E: 85 21
|
|
LDX #$18 ; CBA0: A2 18
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CBA2
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CBA2.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CBA2:
|
|
LDA #$A7 ; CBA2: A9 A7
|
|
CLC ; CBA4: 18
|
|
ADC $CE2D,Y ; CBA5: 79 2D CE
|
|
STA $0200,X ; CBA8: 9D 00 02
|
|
LDA $CE34,Y ; CBAB: B9 34 CE
|
|
STA $0201,X ; CBAE: 9D 01 02
|
|
LDA #$03 ; CBB1: A9 03
|
|
STA $0202,X ; CBB3: 9D 02 02
|
|
LDA $33 ; CBB6: A5 33
|
|
CLC ; CBB8: 18
|
|
ADC #$0D ; CBB9: 69 0D
|
|
ADC $CE26,Y ; CBBB: 79 26 CE
|
|
STA $0203,X ; CBBE: 9D 03 02
|
|
JSR SubCD4F1 ; CBC1: 20 F1 D4
|
|
CPY $21 ; CBC4: C4 21
|
|
BCC Label_CBA2 ; CBC6: 90 DA
|
|
JMP SubCCB60 ; CBC8: 4C 60 CB
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCCBCB
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CBCB.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCCBCB:
|
|
LDY $15 ; CBCB: A4 15
|
|
LDA $16 ; CBCD: A5 16
|
|
CMP #$04 ; CBCF: C9 04
|
|
BEQ Label_CBDE ; CBD1: F0 0B
|
|
LDA $CC24,Y ; CBD3: B9 24 CC
|
|
STA $04 ; CBD6: 85 04
|
|
LDA $CC31,Y ; CBD8: B9 31 CC
|
|
JMP SubCCBE6 ; CBDB: 4C E6 CB
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CBDE
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CBDE.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CBDE:
|
|
LDA $CC3E,Y ; CBDE: B9 3E CC
|
|
STA $04 ; CBE1: 85 04
|
|
LDA $CC44,Y ; CBE3: B9 44 CC
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCCBE6
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CBE6.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCCBE6:
|
|
STA $05 ; CBE6: 85 05
|
|
LDY #$00 ; CBE8: A0 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ParseSpriteLayout
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CBEA.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
ParseSpriteLayout:
|
|
LDA ($04),Y ; CBEA: B1 04
|
|
CMP #$FF ; CBEC: C9 FF
|
|
BEQ Label_CC0F ; CBEE: F0 1F
|
|
LDA #$88 ; CBF0: A9 88
|
|
CLC ; CBF2: 18
|
|
ADC $CC5F,Y ; CBF3: 79 5F CC
|
|
STA $0200,X ; CBF6: 9D 00 02
|
|
LDA ($04),Y ; CBF9: B1 04
|
|
STA $0201,X ; CBFB: 9D 01 02
|
|
LDA #$00 ; CBFE: A9 00
|
|
STA $0202,X ; CC00: 9D 02 02
|
|
LDA $33 ; CC03: A5 33
|
|
CLC ; CC05: 18
|
|
ADC $CC4A,Y ; CC06: 79 4A CC
|
|
STA $0203,X ; CC09: 9D 03 02
|
|
JSR SubCD4F2 ; CC0C: 20 F2 D4
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CC0F
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CC0F.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CC0F:
|
|
INY ; CC0F: C8
|
|
CPY #$15 ; CC10: C0 15
|
|
BCC ParseSpriteLayout ; CC12: 90 D6
|
|
RTS ; CC14: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SpriteLayoutGroupMap
|
|
|
|
; Maps state values to one of five sprite-layout groups.
|
|
; Range: $CC15-$CC23 (15 bytes)
|
|
; ---------------------------------------------------------------------------
|
|
SpriteLayoutGroupMap:
|
|
.byte $00,$00,$00,$01,$01,$02,$02,$02,$03,$03,$03,$03,$03,$04,$04 ; CC15-CC23: 00 00 00 01 01 02 02 02 03 03 03 03 03 04 04
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SpriteLayoutPointerLo
|
|
|
|
; Low bytes for 13 standard sprite-layout lists.
|
|
; Range: $CC24-$CC30 (13 bytes)
|
|
; ---------------------------------------------------------------------------
|
|
SpriteLayoutPointerLo:
|
|
.byte $74,$89,$9E,$B3,$C8,$DD,$C8,$B3,$F2,$07,$1C,$31,$46 ; CC24-CC30: 74 89 9E B3 C8 DD C8 B3 F2 07 1C 31 46
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SpriteLayoutPointerHi
|
|
|
|
; High bytes for 13 standard sprite-layout lists.
|
|
; Range: $CC31-$CC3D (13 bytes)
|
|
; ---------------------------------------------------------------------------
|
|
SpriteLayoutPointerHi:
|
|
.byte $CC,$CC,$CC,$CC,$CC,$CC,$CC,$CC,$CC,$CD,$CD,$CD,$CD ; CC31-CC3D: CC CC CC CC CC CC CC CC CC CD CD CD CD
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; AltSpriteLayoutPointerLo
|
|
|
|
; Low bytes for six alternate sprite-layout lists.
|
|
; Range: $CC3E-$CC43 (6 bytes)
|
|
; ---------------------------------------------------------------------------
|
|
AltSpriteLayoutPointerLo:
|
|
.byte $5B,$70,$9E,$70,$5B,$74 ; CC3E-CC43: 5B 70 9E 70 5B 74
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; AltSpriteLayoutPointerHi
|
|
|
|
; High bytes for six alternate sprite-layout lists.
|
|
; Range: $CC44-$CC49 (6 bytes)
|
|
; ---------------------------------------------------------------------------
|
|
AltSpriteLayoutPointerHi:
|
|
.byte $CD,$CD,$CC,$CD,$CD,$CC ; CC44-CC49: CD CD CC CD CD CC
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SpriteLayoutXOffsets
|
|
|
|
; Twenty-one X offsets used while expanding a layout into OAM.
|
|
; Range: $CC4A-$CC5E (21 bytes)
|
|
; ---------------------------------------------------------------------------
|
|
SpriteLayoutXOffsets:
|
|
.byte $00,$08,$10,$00,$08,$10,$00,$08,$10,$00,$08,$10,$00,$08,$10,$04 ; CC4A-CC59: 00 08 10 00 08 10 00 08 10 00 08 10 00 08 10 04
|
|
.byte $0C,$00,$00,$08,$10 ; CC5A-CC5E: 0C 00 00 08 10
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SpriteLayoutYOffsets
|
|
|
|
; Twenty-one Y offsets used while expanding a layout into OAM.
|
|
; Range: $CC5F-$CC73 (21 bytes)
|
|
; ---------------------------------------------------------------------------
|
|
SpriteLayoutYOffsets:
|
|
.byte $00,$00,$00,$08,$08,$08,$10,$10,$10,$18,$18,$18,$20,$20,$20,$28 ; CC5F-CC6E: 00 00 00 08 08 08 10 10 10 18 18 18 20 20 20 28
|
|
.byte $28,$28,$30,$30,$30 ; CC6F-CC73: 28 28 30 30 30
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SpriteLayoutLists
|
|
|
|
; FF-terminated tile/index lists selected through the split pointer tables.
|
|
; Range: $CC74-$CD84 (273 bytes)
|
|
; ---------------------------------------------------------------------------
|
|
SpriteLayoutLists:
|
|
.byte $FF,$00,$01,$FF,$02,$03,$04,$05,$06,$07,$08,$09,$0A,$0B,$0C,$0D ; CC74-CC83: FF 00 01 FF 02 03 04 05 06 07 08 09 0A 0B 0C 0D
|
|
.byte $0E,$FF,$10,$11,$12,$FF,$00,$01,$FF,$13,$14,$04,$15,$16,$07,$17 ; CC84-CC93: 0E FF 10 11 12 FF 00 01 FF 13 14 04 15 16 07 17
|
|
.byte $18,$0A,$0B,$19,$0D,$0E,$FF,$10,$11,$12,$FF,$00,$01,$1A,$1B,$14 ; CC94-CCA3: 18 0A 0B 19 0D 0E FF 10 11 12 FF 00 01 1A 1B 14
|
|
.byte $1C,$1D,$1E,$1F,$20,$21,$0A,$22,$FF,$0D,$0E,$FF,$10,$11,$12,$FF ; CCA4-CCB3: 1C 1D 1E 1F 20 21 0A 22 FF 0D 0E FF 10 11 12 FF
|
|
.byte $00,$01,$23,$24,$14,$25,$26,$27,$28,$29,$2A,$2B,$2C,$2D,$2E,$2F ; CCB4-CCC3: 00 01 23 24 14 25 26 27 28 29 2A 2B 2C 2D 2E 2F
|
|
.byte $FF,$10,$30,$31,$FF,$00,$01,$32,$33,$14,$34,$35,$36,$37,$38,$39 ; CCC4-CCD3: FF 10 30 31 FF 00 01 32 33 14 34 35 36 37 38 39
|
|
.byte $2B,$3A,$2D,$2E,$2F,$FF,$10,$3C,$3D,$3E,$3F,$01,$40,$41,$14,$42 ; CCD4-CCE3: 2B 3A 2D 2E 2F FF 10 3C 3D 3E 3F 01 40 41 14 42
|
|
.byte $43,$44,$37,$45,$39,$2B,$3A,$2D,$2E,$2F,$FF,$10,$3C,$3D,$FF,$00 ; CCE4-CCF3: 43 44 37 45 39 2B 3A 2D 2E 2F FF 10 3C 3D FF 00
|
|
.byte $01,$FF,$13,$14,$46,$47,$48,$49,$4A,$4B,$4C,$4D,$4E,$4F,$50,$FF ; CCF4-CD03: 01 FF 13 14 46 47 48 49 4A 4B 4C 4D 4E 4F 50 FF
|
|
.byte $52,$53,$12,$FF,$00,$01,$FF,$13,$14,$46,$54,$55,$49,$56,$57,$4C ; CD04-CD13: 52 53 12 FF 00 01 FF 13 14 46 54 55 49 56 57 4C
|
|
.byte $58,$59,$5A,$5B,$FF,$5D,$5E,$12,$FF,$00,$01,$5F,$60,$61,$62,$63 ; CD14-CD23: 58 59 5A 5B FF 5D 5E 12 FF 00 01 5F 60 61 62 63
|
|
.byte $64,$49,$65,$66,$4C,$58,$67,$5A,$5B,$FF,$5D,$5E,$12,$FF,$FF,$68 ; CD24-CD33: 64 49 65 66 4C 58 67 5A 5B FF 5D 5E 12 FF FF 68
|
|
.byte $69,$6A,$6B,$62,$63,$6C,$49,$6D,$6E,$4C,$58,$67,$5A,$5B,$FF,$5D ; CD34-CD43: 69 6A 6B 62 63 6C 49 6D 6E 4C 58 67 5A 5B FF 5D
|
|
.byte $5E,$12,$6F,$70,$68,$71,$72,$6B,$73,$74,$6C,$75,$6D,$76,$77,$78 ; CD44-CD53: 5E 12 6F 70 68 71 72 6B 73 74 6C 75 6D 76 77 78
|
|
.byte $79,$7A,$7B,$FF,$FF,$7D,$12,$FF,$00,$01,$FF,$13,$14,$04,$7E,$84 ; CD54-CD63: 79 7A 7B FF FF 7D 12 FF 00 01 FF 13 14 04 7E 84
|
|
.byte $07,$7F,$80,$0A,$81,$82,$0D,$0E,$FF,$10,$11,$12,$FF,$00,$01,$FF ; CD64-CD73: 07 7F 80 0A 81 82 0D 0E FF 10 11 12 FF 00 01 FF
|
|
.byte $13,$14,$04,$83,$84,$07,$85,$86,$0A,$87,$FF,$0D,$0E,$FF,$10,$11 ; CD74-CD83: 13 14 04 83 84 07 85 86 0A 87 FF 0D 0E FF 10 11
|
|
.byte $12 ; CD84-CD84: 12
|
|
.incbin "prg.bin", $0D85, $00DF ; CD85-CE63: remaining unaudited data
|
|
; ---------------------------------------------------------------------------
|
|
; SubCCE64
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CE64.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCCE64:
|
|
JSR UploadGeneratedCourseGrid ; CE64: 20 98 FC
|
|
LDA #$18 ; CE67: A9 18
|
|
STA animation_frame_index ; CE69: 85 8F
|
|
LDA #$0F ; CE6B: A9 0F
|
|
STA $1A ; CE6D: 85 1A
|
|
JSR SubCFE72 ; CE6F: 20 72 FE
|
|
LDA $49 ; CE72: A5 49
|
|
BNE Label_CEBB ; CE74: D0 45
|
|
JSR SubCFF2B ; CE76: 20 2B FF
|
|
JSR WaitForFrame ; CE79: 20 F3 C8
|
|
LDX #$20 ; CE7C: A2 20
|
|
LDA #$AB ; CE7E: A9 AB
|
|
JSR SetPpuAddress ; CE80: 20 C1 C8
|
|
LDA $8C ; CE83: A5 8C
|
|
AND #$7F ; CE85: 29 7F
|
|
LSR A ; CE87: 4A
|
|
LSR A ; CE88: 4A
|
|
LSR A ; CE89: 4A
|
|
PHA ; CE8A: 48
|
|
STA $19 ; CE8B: 85 19
|
|
LDA #$00 ; CE8D: A9 00
|
|
STA $1A ; CE8F: 85 1A
|
|
JSR SubCCA30 ; CE91: 20 30 CA
|
|
LDA #$A4 ; CE94: A9 A4
|
|
STA PPUDATA ; CE96: 8D 07 20
|
|
JSR SetPpuScrollAndMask ; CE99: 20 9D C8
|
|
PLA ; CE9C: 68
|
|
BEQ Label_CEBB ; CE9D: F0 1C
|
|
LDA $8C ; CE9F: A5 8C
|
|
AND #$07 ; CEA1: 29 07
|
|
ASL A ; CEA3: 0A
|
|
TAY ; CEA4: A8
|
|
LDA $C82D,Y ; CEA5: B9 2D C8
|
|
STA $0212 ; CEA8: 8D 12 02
|
|
LDA $C81D,Y ; CEAB: B9 1D C8
|
|
STA $0211 ; CEAE: 8D 11 02
|
|
LDA #$28 ; CEB1: A9 28
|
|
STA $0210 ; CEB3: 8D 10 02
|
|
LDA #$48 ; CEB6: A9 48
|
|
STA $0213 ; CEB8: 8D 13 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CEBB
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CEBB.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CEBB:
|
|
LDA #$02 ; CEBB: A9 02
|
|
STA $4D ; CEBD: 85 4D
|
|
LDA #$20 ; CEBF: A9 20
|
|
STA $4E ; CEC1: 85 4E
|
|
LDY #$FF ; CEC3: A0 FF
|
|
STY $0274 ; CEC5: 8C 74 02
|
|
INY ; CEC8: C8
|
|
STY $0282 ; CEC9: 8C 82 02
|
|
LDA #$BA ; CECC: A9 BA
|
|
STA $0280 ; CECE: 8D 80 02
|
|
LDA #$88 ; CED1: A9 88
|
|
STA $0281 ; CED3: 8D 81 02
|
|
LDA #$4C ; CED6: A9 4C
|
|
STA $0283 ; CED8: 8D 83 02
|
|
LDA $87 ; CEDB: A5 87
|
|
BNE Label_CEF3 ; CEDD: D0 14
|
|
LDA #$B8 ; CEDF: A9 B8
|
|
STA $0274 ; CEE1: 8D 74 02
|
|
LDA #$8D ; CEE4: A9 8D
|
|
STA $0275 ; CEE6: 8D 75 02
|
|
LDA #$00 ; CEE9: A9 00
|
|
STA $0276 ; CEEB: 8D 76 02
|
|
LDA #$4C ; CEEE: A9 4C
|
|
STA $0277 ; CEF0: 8D 77 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CEF3
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CEF3.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CEF3:
|
|
LDA #$FF ; CEF3: A9 FF
|
|
STA $0284 ; CEF5: 8D 84 02
|
|
LDA $49 ; CEF8: A5 49
|
|
BEQ Label_CF03 ; CEFA: F0 07
|
|
JSR SubCC721 ; CEFC: 20 21 C7
|
|
LDA #$0E ; CEFF: A9 0E
|
|
STA $17 ; CF01: 85 17
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CF03
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CF03.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CF03:
|
|
LDA $53 ; CF03: A5 53
|
|
STA $54 ; CF05: 85 54
|
|
LDA #$00 ; CF07: A9 00
|
|
STA $15 ; CF09: 85 15
|
|
JSR WaitForFrame ; CF0B: 20 F3 C8
|
|
JSR SubCC84D ; CF0E: 20 4D C8
|
|
JSR SetPpuScrollAndMask ; CF11: 20 9D C8
|
|
LDA $49 ; CF14: A5 49
|
|
BEQ Label_CF2F ; CF16: F0 17
|
|
LDX $7A ; CF18: A6 7A
|
|
LDA $2C,X ; CF1A: B5 2C
|
|
CMP #$05 ; CF1C: C9 05
|
|
BCS Label_CF2F ; CF1E: B0 0F
|
|
LDA $83 ; CF20: A5 83
|
|
CLC ; CF22: 18
|
|
SBC $2C,X ; CF23: F5 2C
|
|
BEQ Label_CF2F ; CF25: F0 08
|
|
BCC Label_CF2F ; CF27: 90 06
|
|
CLC ; CF29: 18
|
|
ADC #$05 ; CF2A: 69 05
|
|
JSR SubCFEBF ; CF2C: 20 BF FE
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CF2F
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CF2F.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CF2F:
|
|
JSR SubCC907 ; CF2F: 20 07 C9
|
|
JSR RefreshSequenceSpriteLayout ; CF32: 20 A8 CA
|
|
LDY #$A0 ; CF35: A0 A0
|
|
LDX #$C5 ; CF37: A2 C5
|
|
JSR WaitForFramePreservingY ; CF39: 20 81 C8
|
|
LDA $49 ; CF3C: A5 49
|
|
BEQ Label_CF48 ; CF3E: F0 08
|
|
LDA #$02 ; CF40: A9 02
|
|
STA $4D ; CF42: 85 4D
|
|
LDA #$00 ; CF44: A9 00
|
|
STA $4E ; CF46: 85 4E
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CF48
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CF48.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CF48:
|
|
STA $2E ; CF48: 85 2E
|
|
STA $34 ; CF4A: 85 34
|
|
STA $35 ; CF4C: 85 35
|
|
JSR RestorePpuCtrlShadow ; CF4E: 20 B5 C8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_CF51
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CF51.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_CF51:
|
|
JSR SubCFC78 ; CF51: 20 78 FC
|
|
LDA $2E ; CF54: A5 2E
|
|
BEQ Label_CF51 ; CF56: F0 F9
|
|
LDY #$AA ; CF58: A0 AA
|
|
LDX #$CF ; CF5A: A2 CF
|
|
JSR InstallNmiCallback ; CF5C: 20 88 C8
|
|
LDA #$FF ; CF5F: A9 FF
|
|
STA $020C ; CF61: 8D 0C 02
|
|
LDA #$01 ; CF64: A9 01
|
|
STA $2E ; CF66: 85 2E
|
|
LDA $17 ; CF68: A5 17
|
|
CMP #$0E ; CF6A: C9 0E
|
|
BEQ DeriveAimAngleNibble ; CF6C: F0 19
|
|
CMP #$0D ; CF6E: C9 0D
|
|
BEQ InitializeSequenceBounds ; CF70: F0 1C
|
|
LDA #$1E ; CF72: A9 1E
|
|
STA $1E ; CF74: 85 1E
|
|
LDY $17 ; CF76: A4 17
|
|
LDA $D63C,Y ; CF78: B9 3C D6
|
|
STA $1D ; CF7B: 85 1D
|
|
LDA #$6C ; CF7D: A9 6C
|
|
STA $1F ; CF7F: 85 1F
|
|
JSR RestorePpuCtrlShadow ; CF81: 20 B5 C8
|
|
JMP WaitForSequenceStart ; CF84: 4C 9D CF
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; DeriveAimAngleNibble
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CF87.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
DeriveAimAngleNibble:
|
|
LDA $45 ; CF87: A5 45
|
|
JSR SubCDA1E ; CF89: 20 1E DA
|
|
STA $44 ; CF8C: 85 44
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; InitializeSequenceBounds
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CF8E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
InitializeSequenceBounds:
|
|
LDA #$2E ; CF8E: A9 2E
|
|
STA sequence_lower_bound ; CF90: 85 1E
|
|
LDA #$4C ; CF92: A9 4C
|
|
STA sequence_upper_bound ; CF94: 85 1D
|
|
LDA #$5C ; CF96: A9 5C
|
|
STA sequence_return_bound ; CF98: 85 1F
|
|
JSR RestorePpuCtrlShadow ; CF9A: 20 B5 C8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; WaitForSequenceStart
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CF9D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
WaitForSequenceStart:
|
|
LDA sequence_phase ; CF9D: A5 34
|
|
CMP #nmi_vector_lo ; CF9F: C9 02
|
|
BCC WaitForSequenceStart ; CFA1: 90 FA
|
|
LDA sequence_position ; CFA3: A5 32
|
|
CMP #$4C ; CFA5: C9 4C
|
|
BCC WaitForSequenceStart ; CFA7: 90 F4
|
|
RTS ; CFA9: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; GameplaySequenceNmiCallback
|
|
;
|
|
; Global:
|
|
; Advances the animated gameplay sequence through decrementing, incrementing,
|
|
; and return phases while updating the two OAM Y positions at $027B/$027F.
|
|
; Local:
|
|
; Changes the installed NMI continuation at the configured position bounds,
|
|
; polls the action button to trigger phase changes, selects a sprite-layout
|
|
; frame from position-threshold tables, then joins GameplayDisplayNmiCallback.
|
|
; Parameters:
|
|
; sequence_position and the three sequence bounds must be initialized.
|
|
; Returns:
|
|
; Does not RTS. Continues through a dynamic NMI phase and NmiEpilogue.
|
|
; Clobbers:
|
|
; A, X, Y, processor flags, sequence fields, NMI vector, and related OAM.
|
|
; ---------------------------------------------------------------------------
|
|
GameplaySequenceNmiCallback:
|
|
DEC sequence_position ; CFAA: C6 32
|
|
LDA sequence_position ; CFAC: A5 32
|
|
STA $027B ; CFAE: 8D 7B 02
|
|
STA $027F ; CFB1: 8D 7F 02
|
|
CMP sequence_lower_bound ; CFB4: C5 1E
|
|
BCS UpdateSequenceInput ; CFB6: B0 08
|
|
LDA #$C3 ; CFB8: A9 C3
|
|
STA nmi_vector_lo ; CFBA: 85 02
|
|
LDA #$CF ; CFBC: A9 CF
|
|
STA nmi_vector_hi ; CFBE: 85 03
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; UpdateSequenceInput
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CFC0.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
UpdateSequenceInput:
|
|
JMP PollSequenceActionButton ; CFC0: 4C EA CF
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; GameplaySequenceNmiContinue1
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CFC3.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
GameplaySequenceNmiContinue1:
|
|
INC sequence_position ; CFC3: E6 32
|
|
LDA sequence_position ; CFC5: A5 32
|
|
STA $027B ; CFC7: 8D 7B 02
|
|
STA $027F ; CFCA: 8D 7F 02
|
|
CMP sequence_upper_bound ; CFCD: C5 1D
|
|
BCC PollSequenceActionButton ; CFCF: 90 19
|
|
LDA $17 ; CFD1: A5 17
|
|
CMP #$0D ; CFD3: C9 0D
|
|
BCS InitializeSequenceReturnPhase ; CFD5: B0 4E
|
|
LDA #$01 ; CFD7: A9 01
|
|
STA sequence_phase ; CFD9: 85 34
|
|
LDA #$3E ; CFDB: A9 3E
|
|
STA nmi_vector_lo ; CFDD: 85 02
|
|
LDA #$D0 ; CFDF: A9 D0
|
|
STA nmi_vector_hi ; CFE1: 85 03
|
|
LDA #$8A ; CFE3: A9 8A
|
|
STA $0279 ; CFE5: 8D 79 02
|
|
BNE AdvanceSequencePosition ; CFE8: D0 4F
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; PollSequenceActionButton
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $CFEA.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
PollSequenceActionButton:
|
|
JSR StrobeAndReadController ; CFEA: 20 7B C5
|
|
LDX $7A ; CFED: A6 7A
|
|
LDA JOY1,X ; CFEF: BD 16 40
|
|
AND #$01 ; CFF2: 29 01
|
|
BEQ AdvanceSequencePosition ; CFF4: F0 43
|
|
LDA $2E ; CFF6: A5 2E
|
|
BNE AdvanceSequencePosition ; CFF8: D0 3F
|
|
LDA $17 ; CFFA: A5 17
|
|
CMP #$0D ; CFFC: C9 0D
|
|
BCS InitializeSequenceReturnPhase ; CFFE: B0 25
|
|
LDA #$01 ; D000: A9 01
|
|
STA sequence_phase ; D002: 85 34
|
|
LDA #$3E ; D004: A9 3E
|
|
STA nmi_vector_lo ; D006: 85 02
|
|
LDA #$D0 ; D008: A9 D0
|
|
STA nmi_vector_hi ; D00A: 85 03
|
|
LDA #$8A ; D00C: A9 8A
|
|
STA $0279 ; D00E: 8D 79 02
|
|
LDA sequence_position ; D011: A5 32
|
|
AND #$01 ; D013: 29 01
|
|
BEQ AdvanceSequenceToNextParity ; D015: F0 0A
|
|
LDA sequence_position ; D017: A5 32
|
|
CLC ; D019: 18
|
|
ADC #$01 ; D01A: 69 01
|
|
STA sequence_position ; D01C: 85 32
|
|
STA $027F ; D01E: 8D 7F 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; AdvanceSequenceToNextParity
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D021.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
AdvanceSequenceToNextParity:
|
|
LDA #$01 ; D021: A9 01
|
|
BNE AdvanceSequencePosition ; D023: D0 14
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; InitializeSequenceReturnPhase
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D025.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
InitializeSequenceReturnPhase:
|
|
LDA #nmi_vector_hi ; D025: A9 03
|
|
STA sequence_phase ; D027: 85 34
|
|
LDA #$8A ; D029: A9 8A
|
|
STA nmi_vector_lo ; D02B: 85 02
|
|
LDA #$D0 ; D02D: A9 D0
|
|
STA nmi_vector_hi ; D02F: 85 03
|
|
LDA #$8A ; D031: A9 8A
|
|
STA $0279 ; D033: 8D 79 02
|
|
STA $027D ; D036: 8D 7D 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; AdvanceSequencePosition
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D039.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
AdvanceSequencePosition:
|
|
STA $2E ; D039: 85 2E
|
|
JMP SelectSequenceFrame ; D03B: 4C A9 D0
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; GameplaySequenceNmiContinue2
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D03E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
GameplaySequenceNmiContinue2:
|
|
INC sequence_position ; D03E: E6 32
|
|
LDA $17 ; D040: A5 17
|
|
CMP #$0D ; D042: C9 0D
|
|
BCS Label_D048 ; D044: B0 02
|
|
INC sequence_position ; D046: E6 32
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D048
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D048.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D048:
|
|
LDA sequence_position ; D048: A5 32
|
|
STA $027F ; D04A: 8D 7F 02
|
|
CMP sequence_return_bound ; D04D: C5 1F
|
|
BCC Label_D064 ; D04F: 90 13
|
|
LDA sequence_return_bound ; D051: A5 1F
|
|
STA $027F ; D053: 8D 7F 02
|
|
LDA #nmi_vector_lo ; D056: A9 02
|
|
STA sequence_phase ; D058: 85 34
|
|
STA sequence_return_complete ; D05A: 85 35
|
|
LDA #$8A ; D05C: A9 8A
|
|
STA nmi_vector_lo ; D05E: 85 02
|
|
LDA #$D0 ; D060: A9 D0
|
|
STA nmi_vector_hi ; D062: 85 03
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D064
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D064.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D064:
|
|
JSR StrobeAndReadController ; D064: 20 7B C5
|
|
LDX $7A ; D067: A6 7A
|
|
LDA JOY1,X ; D069: BD 16 40
|
|
AND #$01 ; D06C: 29 01
|
|
BEQ Label_D085 ; D06E: F0 15
|
|
LDA $2E ; D070: A5 2E
|
|
BNE Label_D085 ; D072: D0 11
|
|
LDA #nmi_vector_hi ; D074: A9 03
|
|
STA sequence_phase ; D076: 85 34
|
|
LDA #$8A ; D078: A9 8A
|
|
STA nmi_vector_lo ; D07A: 85 02
|
|
LDA #$D0 ; D07C: A9 D0
|
|
STA nmi_vector_hi ; D07E: 85 03
|
|
LDA #$8A ; D080: A9 8A
|
|
STA $027D ; D082: 8D 7D 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D085
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D085.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D085:
|
|
STA $2E ; D085: 85 2E
|
|
JMP SelectSequenceFrame ; D087: 4C A9 D0
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; GameplaySequenceNmiContinue3
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D08A.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
GameplaySequenceNmiContinue3:
|
|
LDA sequence_return_complete ; D08A: A5 35
|
|
BNE SelectSequenceFrame ; D08C: D0 1B
|
|
INC sequence_position ; D08E: E6 32
|
|
LDA $17 ; D090: A5 17
|
|
CMP #$0D ; D092: C9 0D
|
|
BCS Label_D098 ; D094: B0 02
|
|
INC sequence_position ; D096: E6 32
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D098
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D098.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D098:
|
|
LDA sequence_position ; D098: A5 32
|
|
CMP sequence_return_bound ; D09A: C5 1F
|
|
BCC JumpToSelectSequenceFrame ; D09C: 90 08
|
|
LDA sequence_return_bound ; D09E: A5 1F
|
|
STA sequence_position ; D0A0: 85 32
|
|
LDA #$01 ; D0A2: A9 01
|
|
STA sequence_return_complete ; D0A4: 85 35
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SelectSequenceFrame
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D0A6.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
JumpToSelectSequenceFrame:
|
|
JMP SelectSequenceFrame ; D0A6: 4C A9 D0
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SelectSequenceFrame
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D0A9.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SelectSequenceFrame:
|
|
LDA sequence_phase ; D0A9: A5 34
|
|
BNE SelectReturnSequenceFrame ; D0AB: D0 33
|
|
LDA $17 ; D0AD: A5 17
|
|
CMP #$0D ; D0AF: C9 0D
|
|
BCS SelectTerminalSequenceFrame ; D0B1: B0 19
|
|
LDY #$05 ; D0B3: A0 05
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; FindForwardSequenceFrame
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D0B5.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
FindForwardSequenceFrame:
|
|
LDA sequence_position ; D0B5: A5 32
|
|
CMP ForwardSequenceThresholds,Y ; D0B7: D9 24 D1
|
|
BCC ApplyForwardSequenceFrame ; D0BA: 90 03
|
|
DEY ; D0BC: 88
|
|
BNE FindForwardSequenceFrame ; D0BD: D0 F6
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ApplyForwardSequenceFrame
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D0BF.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
ApplyForwardSequenceFrame:
|
|
STY sequence_frame_index ; D0BF: 84 15
|
|
LDA ForwardSequenceFrameLimits,Y ; D0C1: B9 38 D1
|
|
STA sequence_frame_limit ; D0C4: 85 20
|
|
JSR RefreshSequenceSpriteLayout ; D0C6: 20 A8 CA
|
|
JMP GameplayDisplayNmiCallback ; D0C9: 4C C8 C6
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SelectTerminalSequenceFrame
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D0CC.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SelectTerminalSequenceFrame:
|
|
LDY #nmi_vector_lo ; D0CC: A0 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; FindTerminalSequenceFrame
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D0CE.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
FindTerminalSequenceFrame:
|
|
LDA sequence_position ; D0CE: A5 32
|
|
CMP TerminalSequenceThresholds,Y ; D0D0: D9 2A D1
|
|
BCC ApplyTerminalSequenceFrame ; D0D3: 90 03
|
|
DEY ; D0D5: 88
|
|
BNE FindTerminalSequenceFrame ; D0D6: D0 F6
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ApplyTerminalSequenceFrame
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D0D8.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
ApplyTerminalSequenceFrame:
|
|
STY sequence_frame_index ; D0D8: 84 15
|
|
JSR RefreshSequenceSpriteLayout ; D0DA: 20 A8 CA
|
|
JMP GameplayDisplayNmiCallback ; D0DD: 4C C8 C6
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SelectReturnSequenceFrame
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D0E0.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SelectReturnSequenceFrame:
|
|
LDA sequence_return_complete ; D0E0: A5 35
|
|
BNE FinishSequenceNmi ; D0E2: D0 3D
|
|
LDA $17 ; D0E4: A5 17
|
|
CMP #$0D ; D0E6: C9 0D
|
|
BCS FindFinalSequenceFrame ; D0E8: B0 20
|
|
LDY #$00 ; D0EA: A0 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; FindReturnSequenceFrame
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D0EC.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
FindReturnSequenceFrame:
|
|
LDA sequence_position ; D0EC: A5 32
|
|
CMP ReturnSequenceThresholds,Y ; D0EE: D9 2D D1
|
|
BCC ClampReturnSequenceFrame ; D0F1: 90 05
|
|
INY ; D0F3: C8
|
|
CPY #$07 ; D0F4: C0 07
|
|
BCC FindReturnSequenceFrame ; D0F6: 90 F4
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ClampReturnSequenceFrame
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D0F8.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
ClampReturnSequenceFrame:
|
|
TYA ; D0F8: 98
|
|
CLC ; D0F9: 18
|
|
ADC #$05 ; D0FA: 69 05
|
|
CMP sequence_frame_limit ; D0FC: C5 20
|
|
BCC Label_D102 ; D0FE: 90 02
|
|
LDA sequence_frame_limit ; D100: A5 20
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D102
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D102.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D102:
|
|
STA sequence_frame_index ; D102: 85 15
|
|
JSR RefreshSequenceSpriteLayout ; D104: 20 A8 CA
|
|
JMP GameplayDisplayNmiCallback ; D107: 4C C8 C6
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; FindFinalSequenceFrame
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D10A.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
FindFinalSequenceFrame:
|
|
LDY #$00 ; D10A: A0 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D10C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D10C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D10C:
|
|
LDA sequence_position ; D10C: A5 32
|
|
CMP FinalSequenceThresholds,Y ; D10E: D9 35 D1
|
|
BCC Label_D118 ; D111: 90 05
|
|
INY ; D113: C8
|
|
CPY #nmi_vector_lo ; D114: C0 02
|
|
BCC Label_D10C ; D116: 90 F4
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D118
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D118.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D118:
|
|
TYA ; D118: 98
|
|
CLC ; D119: 18
|
|
ADC #nmi_vector_hi ; D11A: 69 03
|
|
STA sequence_frame_index ; D11C: 85 15
|
|
JSR RefreshSequenceSpriteLayout ; D11E: 20 A8 CA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; FinishSequenceNmi
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D121.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
FinishSequenceNmi:
|
|
JMP GameplayDisplayNmiCallback ; D121: 4C C8 C6
|
|
; Position thresholds used to select the visible sequence frame.
|
|
ForwardSequenceThresholds:
|
|
.byte $4E,$46,$3E,$36,$2E,$26 ; D124-D129: 4E 46 3E 36 2E 26
|
|
TerminalSequenceThresholds:
|
|
.byte $4E,$46,$36 ; D12A-D12C: 4E 46 36
|
|
ReturnSequenceThresholds:
|
|
.byte $26,$2E,$36,$3E,$4D,$54,$5E,$70 ; D12D-D134: 26 2E 36 3E 4D 54 5E 70
|
|
FinalSequenceThresholds:
|
|
.byte $36,$4D,$50 ; D135-D137: 36 4D 50
|
|
ForwardSequenceFrameLimits:
|
|
.byte $0A,$0A,$0A,$0B,$0B,$0C ; D138-D13D: 0A 0A 0A 0B 0B 0C
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD13E
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D13E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD13E:
|
|
LDY #$04 ; D13E: A0 04
|
|
LDX #$D3 ; D140: A2 D3
|
|
JSR WaitForFramePreservingY ; D142: 20 81 C8
|
|
LDA $54 ; D145: A5 54
|
|
BEQ Label_D14D ; D147: F0 04
|
|
LDA #$00 ; D149: A9 00
|
|
STA animation_frame_index ; D14B: 85 8F
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D14D
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D14D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D14D:
|
|
STA $89 ; D14D: 85 89
|
|
STA $39 ; D14F: 85 39
|
|
STA $3C ; D151: 85 3C
|
|
STA $42 ; D153: 85 42
|
|
STA $43 ; D155: 85 43
|
|
STA $4F ; D157: 85 4F
|
|
STA $76 ; D159: 85 76
|
|
STA $2A ; D15B: 85 2A
|
|
STA $81 ; D15D: 85 81
|
|
STA $0100 ; D15F: 8D 00 01
|
|
LDA $17 ; D162: A5 17
|
|
BNE Label_D17C ; D164: D0 16
|
|
LDA $027B ; D166: AD 7B 02
|
|
CMP #$1D ; D169: C9 1D
|
|
BNE Label_D17C ; D16B: D0 0F
|
|
LDA $027F ; D16D: AD 7F 02
|
|
CMP #$4C ; D170: C9 4C
|
|
BNE Label_D17C ; D172: D0 08
|
|
LDA #$01 ; D174: A9 01
|
|
STA $4D ; D176: 85 4D
|
|
LDA #$D2 ; D178: A9 D2
|
|
STA $4E ; D17A: 85 4E
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D17C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D17C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D17C:
|
|
JSR RestorePpuCtrlShadow ; D17C: 20 B5 C8
|
|
LDY $17 ; D17F: A4 17
|
|
LDA $D63C,Y ; D181: B9 3C D6
|
|
SEC ; D184: 38
|
|
SBC $027F ; D185: ED 7F 02
|
|
BMI Label_D190 ; D188: 30 06
|
|
CMP #$08 ; D18A: C9 08
|
|
BCC Label_D190 ; D18C: 90 02
|
|
LDA #$08 ; D18E: A9 08
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D190
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D190.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D190:
|
|
STA $48 ; D190: 85 48
|
|
LDA $027F ; D192: AD 7F 02
|
|
SEC ; D195: 38
|
|
SBC $D64B,Y ; D196: F9 4B D6
|
|
BMI Label_D1A1 ; D199: 30 06
|
|
CMP #$08 ; D19B: C9 08
|
|
BCC Label_D1A1 ; D19D: 90 02
|
|
LDA #$08 ; D19F: A9 08
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D1A1
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D1A1.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D1A1:
|
|
STA $47 ; D1A1: 85 47
|
|
LDX #$00 ; D1A3: A2 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D1A5
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D1A5.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D1A5:
|
|
LDA $17 ; D1A5: A5 17
|
|
CMP #$0D ; D1A7: C9 0D
|
|
BCS Label_D1B0 ; D1A9: B0 05
|
|
LDA $D61A,X ; D1AB: BD 1A D6
|
|
BNE Label_D1B3 ; D1AE: D0 03
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D1B0
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D1B0.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D1B0:
|
|
LDA $D622,X ; D1B0: BD 22 D6
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D1B3
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D1B3.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D1B3:
|
|
CMP $027B ; D1B3: CD 7B 02
|
|
BEQ Label_D1BA ; D1B6: F0 02
|
|
BCS Label_D1BF ; D1B8: B0 05
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D1BA
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D1BA.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D1BA:
|
|
INX ; D1BA: E8
|
|
CPX #$08 ; D1BB: E0 08
|
|
BCC Label_D1A5 ; D1BD: 90 E6
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D1BF
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D1BF.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D1BF:
|
|
LDA $49 ; D1BF: A5 49
|
|
BNE Label_D1CA ; D1C1: D0 07
|
|
LDA $44 ; D1C3: A5 44
|
|
JSR MultiplyBy32 ; D1C5: 20 BC C8
|
|
STA $45 ; D1C8: 85 45
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D1CA
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D1CA.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D1CA:
|
|
LDA #$00 ; D1CA: A9 00
|
|
STA $1C ; D1CC: 85 1C
|
|
LDA $D62A,X ; D1CE: BD 2A D6
|
|
STA $5F ; D1D1: 85 5F
|
|
LDY $17 ; D1D3: A4 17
|
|
LDA $D5E4,Y ; D1D5: B9 E4 D5
|
|
STA $1A ; D1D8: 85 1A
|
|
LDA $D5FE,Y ; D1DA: B9 FE D5
|
|
JSR SubCD505 ; D1DD: 20 05 D5
|
|
STA $19 ; D1E0: 85 19
|
|
LDA $D60B,Y ; D1E2: B9 0B D6
|
|
JSR SubCD505 ; D1E5: 20 05 D5
|
|
STA $09 ; D1E8: 85 09
|
|
LDA $49 ; D1EA: A5 49
|
|
BEQ Label_D1F1 ; D1EC: F0 03
|
|
JMP SubCD515 ; D1EE: 4C 15 D5
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D1F1
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D1F1.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D1F1:
|
|
LDA $17 ; D1F1: A5 17
|
|
CMP #$0D ; D1F3: C9 0D
|
|
BCC Label_D1FA ; D1F5: 90 03
|
|
JMP SubCD2C2 ; D1F7: 4C C2 D2
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D1FA
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D1FA.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D1FA:
|
|
LDA $D5F1,Y ; D1FA: B9 F1 D5
|
|
JSR SubCD505 ; D1FD: 20 05 D5
|
|
TAX ; D200: AA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D201
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D201.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D201:
|
|
JSR SubCD48B ; D201: 20 8B D4
|
|
JSR SubCD4F7 ; D204: 20 F7 D4
|
|
LDA $4F ; D207: A5 4F
|
|
ORA $76 ; D209: 05 76
|
|
BNE Label_D214 ; D20B: D0 07
|
|
JSR SubCD3B7 ; D20D: 20 B7 D3
|
|
LDA $81 ; D210: A5 81
|
|
BEQ Label_D217 ; D212: F0 03
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D214
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D214.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D214:
|
|
JMP SubCD2EE ; D214: 4C EE D2
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D217
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D217.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D217:
|
|
JSR WaitForFrame ; D217: 20 F3 C8
|
|
DEX ; D21A: CA
|
|
BNE Label_D201 ; D21B: D0 E4
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD21D
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D21D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD21D:
|
|
JSR SubCD48B ; D21D: 20 8B D4
|
|
JSR SubCD4F7 ; D220: 20 F7 D4
|
|
LDA $19 ; D223: A5 19
|
|
SEC ; D225: 38
|
|
SBC $1A ; D226: E5 1A
|
|
STA $19 ; D228: 85 19
|
|
LDA $1C ; D22A: A5 1C
|
|
SBC #$00 ; D22C: E9 00
|
|
STA $1C ; D22E: 85 1C
|
|
LDA $42 ; D230: A5 42
|
|
CMP #$F0 ; D232: C9 F0
|
|
BCC Label_D239 ; D234: 90 03
|
|
JMP SubCD2C2 ; D236: 4C C2 D2
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D239
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D239.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D239:
|
|
LDY $47 ; D239: A4 47
|
|
BMI Label_D24C ; D23B: 30 0F
|
|
INC $4B ; D23D: E6 4B
|
|
LDA $4B ; D23F: A5 4B
|
|
CMP $D633,Y ; D241: D9 33 D6
|
|
BCC Label_D24C ; D244: 90 06
|
|
DEC $45 ; D246: C6 45
|
|
LDA #$00 ; D248: A9 00
|
|
STA $4B ; D24A: 85 4B
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D24C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D24C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D24C:
|
|
LDY $48 ; D24C: A4 48
|
|
BMI Label_D25F ; D24E: 30 0F
|
|
INC $4C ; D250: E6 4C
|
|
LDA $4C ; D252: A5 4C
|
|
CMP $D633,Y ; D254: D9 33 D6
|
|
BCC Label_D25F ; D257: 90 06
|
|
INC $45 ; D259: E6 45
|
|
LDA #$00 ; D25B: A9 00
|
|
STA $4C ; D25D: 85 4C
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D25F
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D25F.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D25F:
|
|
LDA $8C ; D25F: A5 8C
|
|
AND #$78 ; D261: 29 78
|
|
BEQ Label_D2AF ; D263: F0 4A
|
|
LSR A ; D265: 4A
|
|
LSR A ; D266: 4A
|
|
TAX ; D267: AA
|
|
LDA #$80 ; D268: A9 80
|
|
STA $3D ; D26A: 85 3D
|
|
STA $3A ; D26C: 85 3A
|
|
LDA $8C ; D26E: A5 8C
|
|
JSR MultiplyABy32 ; D270: 20 BB C8
|
|
STA $25 ; D273: 85 25
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D275
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D275.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D275:
|
|
LDY $25 ; D275: A4 25
|
|
JSR SubCD2F8 ; D277: 20 F8 D2
|
|
LDA $3D ; D27A: A5 3D
|
|
CLC ; D27C: 18
|
|
ADC $0600,Y ; D27D: 79 00 06
|
|
STA $3D ; D280: 85 3D
|
|
LDA $3C ; D282: A5 3C
|
|
ADC $0700,Y ; D284: 79 00 07
|
|
STA $3C ; D287: 85 3C
|
|
LDA $3B ; D289: A5 3B
|
|
ADC $26 ; D28B: 65 26
|
|
STA $3B ; D28D: 85 3B
|
|
TYA ; D28F: 98
|
|
CLC ; D290: 18
|
|
ADC #$40 ; D291: 69 40
|
|
TAY ; D293: A8
|
|
JSR SubCD2F8 ; D294: 20 F8 D2
|
|
LDA $3A ; D297: A5 3A
|
|
CLC ; D299: 18
|
|
ADC $0600,Y ; D29A: 79 00 06
|
|
STA $3A ; D29D: 85 3A
|
|
LDA $39 ; D29F: A5 39
|
|
ADC $0700,Y ; D2A1: 79 00 07
|
|
STA $39 ; D2A4: 85 39
|
|
LDA $38 ; D2A6: A5 38
|
|
ADC $26 ; D2A8: 65 26
|
|
STA $38 ; D2AA: 85 38
|
|
DEX ; D2AC: CA
|
|
BNE Label_D275 ; D2AD: D0 C6
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D2AF
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D2AF.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D2AF:
|
|
LDA $4F ; D2AF: A5 4F
|
|
ORA $76 ; D2B1: 05 76
|
|
BNE SubCD2EE ; D2B3: D0 39
|
|
JSR SubCD3B7 ; D2B5: 20 B7 D3
|
|
LDA $81 ; D2B8: A5 81
|
|
BNE SubCD2EE ; D2BA: D0 32
|
|
JSR WaitForFrame ; D2BC: 20 F3 C8
|
|
JMP SubCD21D ; D2BF: 4C 1D D2
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD2C2
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D2C2.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD2C2:
|
|
LDA #$00 ; D2C2: A9 00
|
|
STA $42 ; D2C4: 85 42
|
|
STA $43 ; D2C6: 85 43
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D2C8
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D2C8.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D2C8:
|
|
LDX $09 ; D2C8: A6 09
|
|
BEQ SubCD2EE ; D2CA: F0 22
|
|
JSR SubCD48B ; D2CC: 20 8B D4
|
|
LDA $4F ; D2CF: A5 4F
|
|
ORA $76 ; D2D1: 05 76
|
|
BNE SubCD2EE ; D2D3: D0 19
|
|
LDA $49 ; D2D5: A5 49
|
|
BNE Label_D2E0 ; D2D7: D0 07
|
|
JSR SubCD3B7 ; D2D9: 20 B7 D3
|
|
LDA $81 ; D2DC: A5 81
|
|
BNE SubCD2EE ; D2DE: D0 0E
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D2E0
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D2E0.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D2E0:
|
|
JSR WaitForFrame ; D2E0: 20 F3 C8
|
|
JSR SubCD65A ; D2E3: 20 5A D6
|
|
LDA $55 ; D2E6: A5 55
|
|
BNE SubCD2EE ; D2E8: D0 04
|
|
DEC $09 ; D2EA: C6 09
|
|
BNE Label_D2C8 ; D2EC: D0 DA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD2EE
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D2EE.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD2EE:
|
|
LDY #$8A ; D2EE: A0 8A
|
|
LDX #$D0 ; D2F0: A2 D0
|
|
JSR WaitForFramePreservingY ; D2F2: 20 81 C8
|
|
JMP RestorePpuCtrlShadow ; D2F5: 4C B5 C8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD2F8
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D2F8.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD2F8:
|
|
LDA $0700,Y ; D2F8: B9 00 07
|
|
CMP #$01 ; D2FB: C9 01
|
|
BNE Label_D301 ; D2FD: D0 02
|
|
LDA #$00 ; D2FF: A9 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D301
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D301.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D301:
|
|
STA $26 ; D301: 85 26
|
|
RTS ; D303: 60
|
|
.incbin "prg.bin", $1304, $00B3 ; D304-D3B6: unclassified/data
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD3B7
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D3B7.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD3B7:
|
|
TXA ; D3B7: 8A
|
|
PHA ; D3B8: 48
|
|
LDA #$00 ; D3B9: A9 00
|
|
STA $0100 ; D3BB: 8D 00 01
|
|
JSR SubCD65D ; D3BE: 20 5D D6
|
|
LDA $53 ; D3C1: A5 53
|
|
BEQ Label_D3C9 ; D3C3: F0 04
|
|
STA $2A ; D3C5: 85 2A
|
|
BNE Label_D419 ; D3C7: D0 50
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D3C9
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D3C9.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D3C9:
|
|
LDA $2A ; D3C9: A5 2A
|
|
BEQ Label_D419 ; D3CB: F0 4C
|
|
LDX $7A ; D3CD: A6 7A
|
|
LDA $42,X ; D3CF: B5 42
|
|
CMP #$03 ; D3D1: C9 03
|
|
BCS Label_D41C ; D3D3: B0 47
|
|
LDY #$8A ; D3D5: A0 8A
|
|
LDX #$D0 ; D3D7: A2 D0
|
|
JSR WaitForFramePreservingY ; D3D9: 20 81 C8
|
|
JSR RestorePpuCtrlShadow ; D3DC: 20 B5 C8
|
|
LDA $45 ; D3DF: A5 45
|
|
PHA ; D3E1: 48
|
|
CLC ; D3E2: 18
|
|
ADC #$80 ; D3E3: 69 80
|
|
STA $45 ; D3E5: 85 45
|
|
LDA #$01 ; D3E7: A9 01
|
|
STA $4D ; D3E9: 85 4D
|
|
STA $0100 ; D3EB: 8D 00 01
|
|
LDA #$00 ; D3EE: A9 00
|
|
STA $4E ; D3F0: 85 4E
|
|
STA $3C ; D3F2: 85 3C
|
|
STA $39 ; D3F4: 85 39
|
|
STA $42 ; D3F6: 85 42
|
|
STA $43 ; D3F8: 85 43
|
|
JSR SubCD48B ; D3FA: 20 8B D4
|
|
JSR SubCD48B ; D3FD: 20 8B D4
|
|
JSR SpriteOffsetForController ; D400: 20 94 C8
|
|
LDA $3B ; D403: A5 3B
|
|
STA $0200,X ; D405: 9D 00 02
|
|
LDA $38 ; D408: A5 38
|
|
STA $0203,X ; D40A: 9D 03 02
|
|
LDA #$FF ; D40D: A9 FF
|
|
STA $0208 ; D40F: 8D 08 02
|
|
PLA ; D412: 68
|
|
STA $45 ; D413: 85 45
|
|
LDA #$01 ; D415: A9 01
|
|
STA $81 ; D417: 85 81
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D419
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D419.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D419:
|
|
PLA ; D419: 68
|
|
TAX ; D41A: AA
|
|
RTS ; D41B: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D41C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D41C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D41C:
|
|
LDA #$00 ; D41C: A9 00
|
|
STA $2A ; D41E: 85 2A
|
|
BEQ Label_D419 ; D420: F0 F7
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD422
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D422.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD422:
|
|
LDA #$00 ; D422: A9 00
|
|
; Overlapping instruction idiom:
|
|
; D424: BIT $40A9 (2C A9 40)
|
|
; D425: LDA #$40 (A9 40)
|
|
Label_D424:
|
|
.byte $2C ; D424: 2C BIT absolute opcode
|
|
SubCD425:
|
|
.byte $A9,$40 ; D425-D426: A9 40 LDA #$40
|
|
CLC ; D427: 18
|
|
ADC $45 ; D428: 65 45
|
|
TAY ; D42A: A8
|
|
LDA #$00 ; D42B: A9 00
|
|
STA $25 ; D42D: 85 25
|
|
STA $26 ; D42F: 85 26
|
|
STA $27 ; D431: 85 27
|
|
LDA $0600,Y ; D433: B9 00 06
|
|
STA $28 ; D436: 85 28
|
|
LDA $0700,Y ; D438: B9 00 07
|
|
STA $29 ; D43B: 85 29
|
|
LDA $49 ; D43D: A5 49
|
|
BNE Label_D482 ; D43F: D0 41
|
|
LDA $29 ; D441: A5 29
|
|
PHA ; D443: 48
|
|
BPL SubCD453 ; D444: 10 0D
|
|
LDA #$00 ; D446: A9 00
|
|
SEC ; D448: 38
|
|
SBC $28 ; D449: E5 28
|
|
STA $28 ; D44B: 85 28
|
|
LDA #$00 ; D44D: A9 00
|
|
SBC $29 ; D44F: E5 29
|
|
STA $29 ; D451: 85 29
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD453
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D453.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD453:
|
|
LDA $27 ; D453: A5 27
|
|
SEC ; D455: 38
|
|
SBC $4E ; D456: E5 4E
|
|
STA $27 ; D458: 85 27
|
|
LDA $28 ; D45A: A5 28
|
|
SBC $4D ; D45C: E5 4D
|
|
STA $28 ; D45E: 85 28
|
|
LDA $29 ; D460: A5 29
|
|
SBC #$00 ; D462: E9 00
|
|
STA $29 ; D464: 85 29
|
|
BMI Label_D46D ; D466: 30 05
|
|
INC $25 ; D468: E6 25
|
|
JMP SubCD453 ; D46A: 4C 53 D4
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D46D
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D46D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D46D:
|
|
LDA $54 ; D46D: A5 54
|
|
BEQ Label_D473 ; D46F: F0 02
|
|
LSR $25 ; D471: 46 25
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D473
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D473.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D473:
|
|
PLA ; D473: 68
|
|
BPL Label_D481 ; D474: 10 0B
|
|
LDA #$00 ; D476: A9 00
|
|
SEC ; D478: 38
|
|
SBC $25 ; D479: E5 25
|
|
STA $25 ; D47B: 85 25
|
|
LDA #$FF ; D47D: A9 FF
|
|
STA $26 ; D47F: 85 26
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D481
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D481.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D481:
|
|
RTS ; D481: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D482
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D482.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D482:
|
|
LDA $28 ; D482: A5 28
|
|
STA $25 ; D484: 85 25
|
|
LDA $29 ; D486: A5 29
|
|
STA $26 ; D488: 85 26
|
|
RTS ; D48A: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD48B
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D48B.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD48B:
|
|
JSR SubCD422 ; D48B: 20 22 D4
|
|
LDA $3C ; D48E: A5 3C
|
|
CLC ; D490: 18
|
|
ADC $25 ; D491: 65 25
|
|
STA $3C ; D493: 85 3C
|
|
LDA $3B ; D495: A5 3B
|
|
ADC $26 ; D497: 65 26
|
|
STA $3B ; D499: 85 3B
|
|
JSR SubCD425 ; D49B: 20 25 D4
|
|
LDA $39 ; D49E: A5 39
|
|
CLC ; D4A0: 18
|
|
ADC $25 ; D4A1: 65 25
|
|
STA $39 ; D4A3: 85 39
|
|
LDA $38 ; D4A5: A5 38
|
|
ADC $26 ; D4A7: 65 26
|
|
STA $38 ; D4A9: 85 38
|
|
LDA $49 ; D4AB: A5 49
|
|
BNE Label_D4F0 ; D4AD: D0 41
|
|
LDA $0100 ; D4AF: AD 00 01
|
|
BNE Label_D4B9 ; D4B2: D0 05
|
|
INC $89 ; D4B4: E6 89
|
|
JMP SubCD4BB ; D4B6: 4C BB D4
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D4B9
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D4B9.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D4B9:
|
|
DEC $89 ; D4B9: C6 89
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD4BB
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D4BB.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD4BB:
|
|
LDA $89 ; D4BB: A5 89
|
|
LDY $54 ; D4BD: A4 54
|
|
BEQ Label_D4C2 ; D4BF: F0 01
|
|
LSR A ; D4C1: 4A
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D4C2
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D4C2.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D4C2:
|
|
STA $8A ; D4C2: 85 8A
|
|
TAY ; D4C4: A8
|
|
CMP #$64 ; D4C5: C9 64
|
|
BCS Label_D4DF ; D4C7: B0 16
|
|
CMP #$1D ; D4C9: C9 1D
|
|
BCC Label_D4D1 ; D4CB: 90 04
|
|
LDA #$9D ; D4CD: A9 9D
|
|
BNE Label_D4D6 ; D4CF: D0 05
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D4D1
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D4D1.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D4D1:
|
|
LDA #$BA ; D4D1: A9 BA
|
|
SEC ; D4D3: 38
|
|
SBC $8A ; D4D4: E5 8A
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D4D6
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D4D6.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D4D6:
|
|
SEC ; D4D6: 38
|
|
SBC $42 ; D4D7: E5 42
|
|
SBC $42 ; D4D9: E5 42
|
|
CMP #$60 ; D4DB: C9 60
|
|
BCS Label_D4E1 ; D4DD: B0 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D4DF
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D4DF.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D4DF:
|
|
LDA #$FF ; D4DF: A9 FF
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D4E1
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D4E1.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D4E1:
|
|
STA $0280 ; D4E1: 8D 80 02
|
|
LDY #$88 ; D4E4: A0 88
|
|
LDA $8A ; D4E6: A5 8A
|
|
CMP #$0E ; D4E8: C9 0E
|
|
BCC Label_D4ED ; D4EA: 90 01
|
|
INY ; D4EC: C8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D4ED
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D4ED.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D4ED:
|
|
STY $0281 ; D4ED: 8C 81 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D4F0
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D4F0.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D4F0:
|
|
RTS ; D4F0: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD4F1
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D4F1.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD4F1:
|
|
INY ; D4F1: C8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD4F2
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D4F2.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD4F2:
|
|
INX ; D4F2: E8
|
|
INX ; D4F3: E8
|
|
INX ; D4F4: E8
|
|
INX ; D4F5: E8
|
|
RTS ; D4F6: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD4F7
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D4F7.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD4F7:
|
|
LDA $43 ; D4F7: A5 43
|
|
CLC ; D4F9: 18
|
|
ADC $19 ; D4FA: 65 19
|
|
STA $43 ; D4FC: 85 43
|
|
LDA $42 ; D4FE: A5 42
|
|
ADC $1C ; D500: 65 1C
|
|
STA $42 ; D502: 85 42
|
|
RTS ; D504: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD505
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D505.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD505:
|
|
LDX $5F ; D505: A6 5F
|
|
BEQ Label_D514 ; D507: F0 0B
|
|
STA $5E ; D509: 85 5E
|
|
JSR SubCF906 ; D50B: 20 06 F9
|
|
LDA $61 ; D50E: A5 61
|
|
BNE Label_D514 ; D510: D0 02
|
|
LDA #$01 ; D512: A9 01
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D514
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D514.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D514:
|
|
RTS ; D514: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD515
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D515.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD515:
|
|
LDA $09 ; D515: A5 09
|
|
STA $95 ; D517: 85 95
|
|
LDA $45 ; D519: A5 45
|
|
STA $94 ; D51B: 85 94
|
|
LDA $95 ; D51D: A5 95
|
|
STA $5E ; D51F: 85 5E
|
|
LDA $94 ; D521: A5 94
|
|
JSR SubCFC24 ; D523: 20 24 FC
|
|
STA $90 ; D526: 85 90
|
|
LDA $94 ; D528: A5 94
|
|
JSR SubCFC27 ; D52A: 20 27 FC
|
|
STA $91 ; D52D: 85 91
|
|
LDA #$80 ; D52F: A9 80
|
|
STA $92 ; D531: 85 92
|
|
STA $93 ; D533: 85 93
|
|
STA $39 ; D535: 85 39
|
|
STA $3C ; D537: 85 3C
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D539
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D539.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D539:
|
|
JSR SubCFD67 ; D539: 20 67 FD
|
|
LDA $76 ; D53C: A5 76
|
|
BEQ Label_D551 ; D53E: F0 11
|
|
LDA #$FF ; D540: A9 FF
|
|
STA $0280 ; D542: 8D 80 02
|
|
LDA $95 ; D545: A5 95
|
|
CMP #$3C ; D547: C9 3C
|
|
BCC Label_D562 ; D549: 90 17
|
|
LDA #$00 ; D54B: A9 00
|
|
STA $76 ; D54D: 85 76
|
|
BEQ Label_D539 ; D54F: F0 E8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D551
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D551.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D551:
|
|
LDA $4F ; D551: A5 4F
|
|
ORA $81 ; D553: 05 81
|
|
BNE Label_D562 ; D555: D0 0B
|
|
LDY #$02 ; D557: A0 02
|
|
JSR SubCC8F5 ; D559: 20 F5 C8
|
|
LDA $95 ; D55C: A5 95
|
|
CMP #$05 ; D55E: C9 05
|
|
BCS Label_D539 ; D560: B0 D7
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D562
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D562.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D562:
|
|
RTS ; D562: 60
|
|
.incbin "prg.bin", $1563, $00F7 ; D563-D659: unclassified/data
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD65A
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D65A.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD65A:
|
|
JSR SubCD6FC ; D65A: 20 FC D6
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD65D
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D65D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD65D:
|
|
LDY #$00 ; D65D: A0 00
|
|
STY $52 ; D65F: 84 52
|
|
STY $53 ; D661: 84 53
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD663
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D663.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD663:
|
|
LDA $029D,Y ; D663: B9 9D 02
|
|
CMP #$8F ; D666: C9 8F
|
|
BEQ Label_D6E3 ; D668: F0 79
|
|
CMP #$E0 ; D66A: C9 E0
|
|
BCC Label_D6E9 ; D66C: 90 7B
|
|
LDA $38 ; D66E: A5 38
|
|
SEC ; D670: 38
|
|
SBC $029F,Y ; D671: F9 9F 02
|
|
CMP #$08 ; D674: C9 08
|
|
BCS Label_D6E9 ; D676: B0 71
|
|
STA $50 ; D678: 85 50
|
|
LDA $3B ; D67A: A5 3B
|
|
SEC ; D67C: 38
|
|
SBC $029C,Y ; D67D: F9 9C 02
|
|
CMP #$08 ; D680: C9 08
|
|
BCS Label_D6E9 ; D682: B0 65
|
|
STA $51 ; D684: 85 51
|
|
LDA $029D,Y ; D686: B9 9D 02
|
|
SEC ; D689: 38
|
|
SBC #$E0 ; D68A: E9 E0
|
|
CMP #$15 ; D68C: C9 15
|
|
BCS Label_D6A0 ; D68E: B0 10
|
|
ASL A ; D690: 0A
|
|
ASL A ; D691: 0A
|
|
ASL A ; D692: 0A
|
|
ADC #$00 ; D693: 69 00
|
|
STA $23 ; D695: 85 23
|
|
LDX #$05 ; D697: A2 05
|
|
BCC Label_D69C ; D699: 90 01
|
|
INX ; D69B: E8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D69C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D69C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D69C:
|
|
STX $24 ; D69C: 86 24
|
|
BNE Label_D6B0 ; D69E: D0 10
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D6A0
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D6A0.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D6A0:
|
|
SBC #$15 ; D6A0: E9 15
|
|
ASL A ; D6A2: 0A
|
|
ASL A ; D6A3: 0A
|
|
ASL A ; D6A4: 0A
|
|
ADC #$98 ; D6A5: 69 98
|
|
STA $23 ; D6A7: 85 23
|
|
LDX #$05 ; D6A9: A2 05
|
|
BCC Label_D6AE ; D6AB: 90 01
|
|
INX ; D6AD: E8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D6AE
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D6AE.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D6AE:
|
|
STX $24 ; D6AE: 86 24
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D6B0
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D6B0.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D6B0:
|
|
LDA $029E,Y ; D6B0: B9 9E 02
|
|
PHA ; D6B3: 48
|
|
AND #$80 ; D6B4: 29 80
|
|
BEQ Label_D6BF ; D6B6: F0 07
|
|
LDA #$07 ; D6B8: A9 07
|
|
SEC ; D6BA: 38
|
|
SBC $51 ; D6BB: E5 51
|
|
STA $51 ; D6BD: 85 51
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D6BF
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D6BF.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D6BF:
|
|
PLA ; D6BF: 68
|
|
AND #$40 ; D6C0: 29 40
|
|
BEQ Label_D6CB ; D6C2: F0 07
|
|
LDA #$07 ; D6C4: A9 07
|
|
SEC ; D6C6: 38
|
|
SBC $50 ; D6C7: E5 50
|
|
STA $50 ; D6C9: 85 50
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D6CB
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D6CB.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D6CB:
|
|
TYA ; D6CB: 98
|
|
PHA ; D6CC: 48
|
|
LDX $50 ; D6CD: A6 50
|
|
LDY $51 ; D6CF: A4 51
|
|
LDA ($23),Y ; D6D1: B1 23
|
|
AND $D6F4,X ; D6D3: 3D F4 D6
|
|
BEQ Label_D6E7 ; D6D6: F0 0F
|
|
PLA ; D6D8: 68
|
|
TAY ; D6D9: A8
|
|
LDA $029D,Y ; D6DA: B9 9D 02
|
|
CMP #$F5 ; D6DD: C9 F5
|
|
BCS Label_D6E4 ; D6DF: B0 03
|
|
INC $53 ; D6E1: E6 53
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D6E3
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D6E3.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D6E3:
|
|
RTS ; D6E3: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D6E4
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D6E4.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D6E4:
|
|
INC $52 ; D6E4: E6 52
|
|
RTS ; D6E6: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D6E7
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D6E7.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D6E7:
|
|
PLA ; D6E7: 68
|
|
TAY ; D6E8: A8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D6E9
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D6E9.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D6E9:
|
|
INY ; D6E9: C8
|
|
INY ; D6EA: C8
|
|
INY ; D6EB: C8
|
|
INY ; D6EC: C8
|
|
CPY #$5C ; D6ED: C0 5C
|
|
BEQ Label_D6E3 ; D6EF: F0 F2
|
|
JMP SubCD663 ; D6F1: 4C 63 D6
|
|
; BitMaskTable: 8 descending bit masks ($80,$40,$20,$10,$08,$04,$02,$01),
|
|
; indexed by ($3B AND #$07) in SubCD6FC ($D6FC) and consumed via
|
|
; AND $D6F4,X at $D6D3/$D7EF.
|
|
BitMaskTable:
|
|
.byte $80,$40,$20,$10,$08,$04,$02,$01 ; D6F4-D6FB: 80 40 20 10 08 04 02 01
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD6FC
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D6FC.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD6FC:
|
|
LDY #$00 ; D6FC: A0 00
|
|
STY $56 ; D6FE: 84 56
|
|
STY $55 ; D700: 84 55
|
|
LDA $3B ; D702: A5 3B
|
|
AND #$07 ; D704: 29 07
|
|
STA $51 ; D706: 85 51
|
|
LDX #$00 ; D708: A2 00
|
|
LDA $3B ; D70A: A5 3B
|
|
AND #$F8 ; D70C: 29 F8
|
|
ASL A ; D70E: 0A
|
|
STA $19 ; D70F: 85 19
|
|
BCC Label_D714 ; D711: 90 01
|
|
INX ; D713: E8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D714
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D714.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D714:
|
|
STX $1A ; D714: 86 1A
|
|
LDA $38 ; D716: A5 38
|
|
AND #$07 ; D718: 29 07
|
|
STA $50 ; D71A: 85 50
|
|
LDA $38 ; D71C: A5 38
|
|
SEC ; D71E: 38
|
|
SBC #$80 ; D71F: E9 80
|
|
LSR A ; D721: 4A
|
|
LSR A ; D722: 4A
|
|
LSR A ; D723: 4A
|
|
CLC ; D724: 18
|
|
ADC $19 ; D725: 65 19
|
|
STA $19 ; D727: 85 19
|
|
LDA $1A ; D729: A5 1A
|
|
ADC #$03 ; D72B: 69 03
|
|
STA $1A ; D72D: 85 1A
|
|
LDA ($19),Y ; D72F: B1 19
|
|
STA $1B ; D731: 85 1B
|
|
CMP #$EF ; D733: C9 EF
|
|
BEQ Label_D774 ; D735: F0 3D
|
|
CMP #$FD ; D737: C9 FD
|
|
BEQ Label_D774 ; D739: F0 39
|
|
TAX ; D73B: AA
|
|
LDA $D80D,X ; D73C: BD 0D D8
|
|
BEQ Label_D773 ; D73F: F0 32
|
|
CMP #$10 ; D741: C9 10
|
|
BEQ Label_D771 ; D743: F0 2C
|
|
CMP #$20 ; D745: C9 20
|
|
BEQ Label_D774 ; D747: F0 2B
|
|
CMP #$40 ; D749: C9 40
|
|
BEQ Label_D79E ; D74B: F0 51
|
|
CMP #$FF ; D74D: C9 FF
|
|
BEQ Label_D7A8 ; D74F: F0 57
|
|
LDA #$01 ; D751: A9 01
|
|
STA $1B ; D753: 85 1B
|
|
LDA $50 ; D755: A5 50
|
|
AND #$04 ; D757: 29 04
|
|
BEQ Label_D75D ; D759: F0 02
|
|
ASL $1B ; D75B: 06 1B
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D75D
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D75D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D75D:
|
|
LDA $51 ; D75D: A5 51
|
|
AND #$04 ; D75F: 29 04
|
|
BEQ Label_D767 ; D761: F0 04
|
|
ASL $1B ; D763: 06 1B
|
|
ASL $1B ; D765: 06 1B
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D767
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D767.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D767:
|
|
LDA $1B ; D767: A5 1B
|
|
AND $D80D,X ; D769: 3D 0D D8
|
|
BNE Label_D771 ; D76C: D0 03
|
|
JMP SubCD7F5 ; D76E: 4C F5 D7
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D771
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D771.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D771:
|
|
INC $56 ; D771: E6 56
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D773
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D773.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D773:
|
|
RTS ; D773: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D774
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D774.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D774:
|
|
LDA $3B ; D774: A5 3B
|
|
AND #$E0 ; D776: 29 E0
|
|
LSR A ; D778: 4A
|
|
LSR A ; D779: 4A
|
|
STA $1B ; D77A: 85 1B
|
|
LDA $38 ; D77C: A5 38
|
|
JSR SubCDA1D ; D77E: 20 1D DA
|
|
CLC ; D781: 18
|
|
ADC $1B ; D782: 65 1B
|
|
TAY ; D784: A8
|
|
LDX #$00 ; D785: A2 00
|
|
LDA $3B ; D787: A5 3B
|
|
AND #$10 ; D789: 29 10
|
|
BEQ Label_D78F ; D78B: F0 02
|
|
INX ; D78D: E8
|
|
INX ; D78E: E8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D78F
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D78F.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D78F:
|
|
LDA $38 ; D78F: A5 38
|
|
AND #$10 ; D791: 29 10
|
|
BEQ Label_D796 ; D793: F0 01
|
|
INX ; D795: E8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D796
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D796.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D796:
|
|
LDA $0100,Y ; D796: B9 00 01
|
|
AND $D823,X ; D799: 3D 23 D8
|
|
BEQ Label_D771 ; D79C: F0 D3
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D79E
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D79E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D79E:
|
|
LDX $2B ; D79E: A6 2B
|
|
LDA $E20D,X ; D7A0: BD 0D E2
|
|
BMI Label_D771 ; D7A3: 30 CC
|
|
INC $55 ; D7A5: E6 55
|
|
RTS ; D7A7: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D7A8
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D7A8.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D7A8:
|
|
STX $19 ; D7A8: 86 19
|
|
LDA #$00 ; D7AA: A9 00
|
|
ASL $19 ; D7AC: 06 19
|
|
ROL A ; D7AE: 2A
|
|
ASL $19 ; D7AF: 06 19
|
|
ROL A ; D7B1: 2A
|
|
ASL $19 ; D7B2: 06 19
|
|
ROL A ; D7B4: 2A
|
|
ASL $19 ; D7B5: 06 19
|
|
ROL A ; D7B7: 2A
|
|
ORA #$10 ; D7B8: 09 10
|
|
TAX ; D7BA: AA
|
|
LDA $19 ; D7BB: A5 19
|
|
ADC $51 ; D7BD: 65 51
|
|
PHA ; D7BF: 48
|
|
LDA ppu_ctrl_shadow ; D7C0: A5 00
|
|
AND #$7F ; D7C2: 29 7F
|
|
STA PPUCTRL ; D7C4: 8D 00 20
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D7C7
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D7C7.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D7C7:
|
|
LDA PPUSTATUS ; D7C7: AD 02 20
|
|
BPL Label_D7C7 ; D7CA: 10 FB
|
|
PLA ; D7CC: 68
|
|
JSR SetPpuAddress ; D7CD: 20 C1 C8
|
|
LDY PPUDATA ; D7D0: AC 07 20
|
|
LDY PPUDATA ; D7D3: AC 07 20
|
|
STY $69 ; D7D6: 84 69
|
|
ADC #$08 ; D7D8: 69 08
|
|
JSR SetPpuAddress ; D7DA: 20 C1 C8
|
|
LDY PPUDATA ; D7DD: AC 07 20
|
|
LDA PPUDATA ; D7E0: AD 07 20
|
|
PHA ; D7E3: 48
|
|
JSR SetPpuScrollAndMask ; D7E4: 20 9D C8
|
|
JSR RestorePpuCtrlShadow ; D7E7: 20 B5 C8
|
|
PLA ; D7EA: 68
|
|
ORA $69 ; D7EB: 05 69
|
|
LDX $50 ; D7ED: A6 50
|
|
AND $D6F4,X ; D7EF: 3D F4 D6
|
|
BNE Label_D774 ; D7F2: D0 80
|
|
RTS ; D7F4: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD7F5
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D7F5.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD7F5:
|
|
LDY $D80D,X ; D7F5: BC 0D D8
|
|
LDA $D82E,Y ; D7F8: B9 2E D8
|
|
STA $1C ; D7FB: 85 1C
|
|
LDX #$03 ; D7FD: A2 03
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D7FF
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D7FF.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D7FF:
|
|
LSR $1C ; D7FF: 46 1C
|
|
BCC Label_D81D ; D801: 90 1A
|
|
LDA $19 ; D803: A5 19
|
|
ADC $D827,X ; D805: 7D 27 D8
|
|
STA $1D ; D808: 85 1D
|
|
LDA $1A ; D80A: A5 1A
|
|
ADC $D82B,X ; D80C: 7D 2B D8
|
|
STA $1E ; D80F: 85 1E
|
|
LDY #$00 ; D811: A0 00
|
|
LDA ($1D),Y ; D813: B1 1D
|
|
TAY ; D815: A8
|
|
LDA $D80D,Y ; D816: B9 0D D8
|
|
CMP #$10 ; D819: C9 10
|
|
BCC Label_D822 ; D81B: 90 05
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D81D
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D81D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D81D:
|
|
DEX ; D81D: CA
|
|
BPL Label_D7FF ; D81E: 10 DF
|
|
INC $56 ; D820: E6 56
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D822
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D822.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D822:
|
|
RTS ; D822: 60
|
|
.incbin "prg.bin", $1823, $00CA ; D823-D8EC: unclassified/data
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD8ED
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D8ED.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD8ED:
|
|
PHA ; D8ED: 48
|
|
LDA $78 ; D8EE: A5 78
|
|
LSR A ; D8F0: 4A
|
|
STA $6C ; D8F1: 85 6C
|
|
PLA ; D8F3: 68
|
|
LSR A ; D8F4: 4A
|
|
SEC ; D8F5: 38
|
|
SBC $6C ; D8F6: E5 6C
|
|
STA $6C ; D8F8: 85 6C
|
|
LDA $79 ; D8FA: A5 79
|
|
LSR A ; D8FC: 4A
|
|
STA $6B ; D8FD: 85 6B
|
|
TXA ; D8FF: 8A
|
|
LSR A ; D900: 4A
|
|
SEC ; D901: 38
|
|
SBC $6B ; D902: E5 6B
|
|
STA $6B ; D904: 85 6B
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD906
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D906.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD906:
|
|
LDA $6C ; D906: A5 6C
|
|
ASL A ; D908: 0A
|
|
LDA $6B ; D909: A5 6B
|
|
ROL A ; D90B: 2A
|
|
ROL A ; D90C: 2A
|
|
AND #$03 ; D90D: 29 03
|
|
PHA ; D90F: 48
|
|
LDA $6C ; D910: A5 6C
|
|
JSR SubCD9B1 ; D912: 20 B1 D9
|
|
STA $6C ; D915: 85 6C
|
|
LDA $6B ; D917: A5 6B
|
|
JSR SubCD9B1 ; D919: 20 B1 D9
|
|
STA $6B ; D91C: 85 6B
|
|
LDY #$00 ; D91E: A0 00
|
|
LDA $6C ; D920: A5 6C
|
|
CMP $6B ; D922: C5 6B
|
|
BCC Label_D92D ; D924: 90 07
|
|
LDX $6B ; D926: A6 6B
|
|
STA $6B ; D928: 85 6B
|
|
STX $6C ; D92A: 86 6C
|
|
DEY ; D92C: 88
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D92D
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D92D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D92D:
|
|
STY $1A ; D92D: 84 1A
|
|
LDA $6B ; D92F: A5 6B
|
|
BNE Label_D937 ; D931: D0 04
|
|
PLA ; D933: 68
|
|
LDA #$40 ; D934: A9 40
|
|
RTS ; D936: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D937
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D937.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D937:
|
|
CMP $6C ; D937: C5 6C
|
|
BNE Label_D93F ; D939: D0 04
|
|
LDA #$20 ; D93B: A9 20
|
|
BNE Label_D974 ; D93D: D0 35
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D93F
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D93F.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D93F:
|
|
LDA $6C ; D93F: A5 6C
|
|
LDX #$00 ; D941: A2 00
|
|
STX $6C ; D943: 86 6C
|
|
LDX #$08 ; D945: A2 08
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D947
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D947.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D947:
|
|
ASL A ; D947: 0A
|
|
BCS Label_D94E ; D948: B0 04
|
|
CMP $6B ; D94A: C5 6B
|
|
BCC Label_D951 ; D94C: 90 03
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D94E
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D94E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D94E:
|
|
SBC $6B ; D94E: E5 6B
|
|
SEC ; D950: 38
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D951
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D951.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D951:
|
|
ROL $6C ; D951: 26 6C
|
|
DEX ; D953: CA
|
|
BNE Label_D947 ; D954: D0 F1
|
|
LDA $6C ; D956: A5 6C
|
|
AND #$C0 ; D958: 29 C0
|
|
JSR SubCDA1E ; D95A: 20 1E DA
|
|
TAX ; D95D: AA
|
|
LDA $6C ; D95E: A5 6C
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D960
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D960.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D960:
|
|
CMP $D990,X ; D960: DD 90 D9
|
|
BCC Label_D968 ; D963: 90 03
|
|
INX ; D965: E8
|
|
BNE Label_D960 ; D966: D0 F8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D968
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D968.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D968:
|
|
TXA ; D968: 8A
|
|
LDX $1A ; D969: A6 1A
|
|
BNE Label_D974 ; D96B: D0 07
|
|
STA $19 ; D96D: 85 19
|
|
LDA #$40 ; D96F: A9 40
|
|
SEC ; D971: 38
|
|
SBC $19 ; D972: E5 19
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D974
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D974.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D974:
|
|
STA $19 ; D974: 85 19
|
|
PLA ; D976: 68
|
|
TAX ; D977: AA
|
|
LDA $D988,X ; D978: BD 88 D9
|
|
LDY $D98C,X ; D97B: BC 8C D9
|
|
BNE Label_D984 ; D97E: D0 04
|
|
CLC ; D980: 18
|
|
ADC $19 ; D981: 65 19
|
|
RTS ; D983: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D984
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D984.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D984:
|
|
SEC ; D984: 38
|
|
SBC $19 ; D985: E5 19
|
|
RTS ; D987: 60
|
|
; D988ScoreAdjustTable: 41-byte table accessed two ways from Label_D974:
|
|
; LDA $D988,X -> entry at offset X
|
|
; LDY $D98C,X -> entry at offset X+4 (overlaps the same byte region)
|
|
; X is loaded from the stack (PLA; TAX) at $D976-$D977.
|
|
D988ScoreAdjustTable:
|
|
.byte $80,$80,$00,$00,$ff,$00,$00,$ff,$04,$0a,$10,$17,$1d,$23,$2a,$30 ; D988-D997
|
|
.byte $37,$3d,$44,$4b,$52,$59,$60,$67,$6e,$76,$7d,$85,$8d,$96,$9e,$a7 ; D998-D9A7
|
|
.byte $b0,$ba,$c3,$cd,$d8,$e3,$ee,$fa,$ff ; D9A8-D9B0
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD9B1
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D9B1.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD9B1:
|
|
BPL Label_D9B8 ; D9B1: 10 05
|
|
EOR #$FF ; D9B3: 49 FF
|
|
CLC ; D9B5: 18
|
|
ADC #$01 ; D9B6: 69 01
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D9B8
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D9B8.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D9B8:
|
|
RTS ; D9B8: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD9B9
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D9B9.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD9B9:
|
|
LDA $44 ; D9B9: A5 44
|
|
JSR MultiplyBy32 ; D9BB: 20 BC C8
|
|
STA $45 ; D9BE: 85 45
|
|
LDA $65 ; D9C0: A5 65
|
|
LDX $66 ; D9C2: A6 66
|
|
CLC ; D9C4: 18
|
|
BCC Label_D9CC ; D9C5: 90 05
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD9C7
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D9C7.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD9C7:
|
|
LDA $67 ; D9C7: A5 67
|
|
LDX $68 ; D9C9: A6 68
|
|
SEC ; D9CB: 38
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D9CC
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D9CC.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D9CC:
|
|
PHP ; D9CC: 08
|
|
SEC ; D9CD: 38
|
|
SBC $78 ; D9CE: E5 78
|
|
STA $6C ; D9D0: 85 6C
|
|
TXA ; D9D2: 8A
|
|
SEC ; D9D3: 38
|
|
SBC $79 ; D9D4: E5 79
|
|
STA $6B ; D9D6: 85 6B
|
|
; Overlapping instruction idiom:
|
|
; D9D8: BIT $0838 (2C 38 08)
|
|
; D9D9: SEC (38)
|
|
; $D9DA is only the high operand byte, not an independent PHP entry.
|
|
Label_D9D8:
|
|
.byte $2C ; D9D8: 2C BIT absolute opcode
|
|
SubCD9D9:
|
|
.byte $38,$08 ; D9D9-D9DA: 38 08 SEC / BIT operand
|
|
JSR SubCD906 ; D9DB: 20 06 D9
|
|
STA $71 ; D9DE: 85 71
|
|
SEC ; D9E0: 38
|
|
SBC $45 ; D9E1: E5 45
|
|
PLP ; D9E3: 28
|
|
BCC Label_D9EA ; D9E4: 90 04
|
|
TAY ; D9E6: A8
|
|
ASL A ; D9E7: 0A
|
|
TYA ; D9E8: 98
|
|
ROR A ; D9E9: 6A
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D9EA
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D9EA.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D9EA:
|
|
STA $72 ; D9EA: 85 72
|
|
BPL Label_D9F2 ; D9EC: 10 04
|
|
CMP #$C0 ; D9EE: C9 C0
|
|
BCS Label_D9F6 ; D9F0: B0 04
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D9F2
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D9F2.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D9F2:
|
|
CMP #$1A ; D9F2: C9 1A
|
|
BCS Label_D9FA ; D9F4: B0 04
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_D9F6
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D9F6.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_D9F6:
|
|
CLC ; D9F6: 18
|
|
ADC #$50 ; D9F7: 69 50
|
|
; Overlapping instruction idiom:
|
|
; D9F9: BIT $FFA9 (2C A9 FF)
|
|
; D9FA: LDA #$FF (A9 FF)
|
|
Label_D9F9:
|
|
.byte $2C ; D9F9: 2C BIT absolute opcode
|
|
Label_D9FA:
|
|
.byte $A9,$FF ; D9FA-D9FB: A9 FF LDA #$FF
|
|
STA $74 ; D9FC: 85 74
|
|
RTS ; D9FE: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCD9FF
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $D9FF.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCD9FF:
|
|
LDA $49 ; D9FF: A5 49
|
|
BNE Label_DA15 ; DA01: D0 12
|
|
LDX $66 ; DA03: A6 66
|
|
LDA $65 ; DA05: A5 65
|
|
JSR SubCD8ED ; DA07: 20 ED D8
|
|
CLC ; DA0A: 18
|
|
ADC #$07 ; DA0B: 69 07
|
|
JSR SubCDA1E ; DA0D: 20 1E DA
|
|
STA $44 ; DA10: 85 44
|
|
JMP SubCDA1C ; DA12: 4C 1C DA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DA15
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DA15.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DA15:
|
|
JSR SubCD9C7 ; DA15: 20 C7 D9
|
|
LDA $71 ; DA18: A5 71
|
|
STA $45 ; DA1A: 85 45
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCDA1C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DA1C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCDA1C:
|
|
RTS ; DA1C: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCDA1D
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DA1D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCDA1D:
|
|
LSR A ; DA1D: 4A
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCDA1E
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DA1E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCDA1E:
|
|
LSR A ; DA1E: 4A
|
|
LSR A ; DA1F: 4A
|
|
LSR A ; DA20: 4A
|
|
LSR A ; DA21: 4A
|
|
RTS ; DA22: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; InitializeTitleAndGame
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DA23.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
InitializeTitleAndGame:
|
|
LDY #$A2 ; DA23: A0 A2
|
|
LDX #$DA ; DA25: A2 DA
|
|
JSR InstallNmiCallback ; DA27: 20 88 C8
|
|
LDA #$00 ; DA2A: A9 00
|
|
STA $0140 ; DA2C: 8D 40 01
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCDA2F
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DA2F.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCDA2F:
|
|
LDY #$02 ; DA2F: A0 02
|
|
STY $09 ; DA31: 84 09
|
|
DEY ; DA33: 88
|
|
STY menu_input_latch ; DA34: 84 0A
|
|
STY $82 ; DA36: 84 82
|
|
DEY ; DA38: 88
|
|
STY PPUMASK ; DA39: 8C 01 20
|
|
STY APUSTATUS ; DA3C: 8C 15 40
|
|
JSR RestorePpuCtrlShadow ; DA3F: 20 B5 C8
|
|
JSR SubCDB10 ; DA42: 20 10 DB
|
|
JSR SubCC89A ; DA45: 20 9A C8
|
|
LDA #$00 ; DA48: A9 00
|
|
STA $09 ; DA4A: 85 09
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCDA4C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DA4C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCDA4C:
|
|
LDY #$05 ; DA4C: A0 05
|
|
JSR WaitFrameGroups ; DA4E: 20 09 C9
|
|
LDA #$01 ; DA51: A9 01
|
|
STA $09 ; DA53: 85 09
|
|
LDY $0140 ; DA55: AC 40 01
|
|
STY $2B ; DA58: 84 2B
|
|
INY ; DA5A: C8
|
|
CPY #$12 ; DA5B: C0 12
|
|
BCC Label_DA61 ; DA5D: 90 02
|
|
LDY #$00 ; DA5F: A0 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DA61
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DA61.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DA61:
|
|
STY $0140 ; DA61: 8C 40 01
|
|
LDY #$00 ; DA64: A0 00
|
|
STY $49 ; DA66: 84 49
|
|
STY $15 ; DA68: 84 15
|
|
STY $17 ; DA6A: 84 17
|
|
STY $7A ; DA6C: 84 7A
|
|
STY $87 ; DA6E: 84 87
|
|
STY $44 ; DA70: 84 44
|
|
STY $45 ; DA72: 84 45
|
|
INY ; DA74: C8
|
|
STY $4A ; DA75: 84 4A
|
|
JSR ClearNametableAndOam ; DA77: 20 C8 C8
|
|
JSR DecodeCoursePackage ; DA7A: 20 78 DD
|
|
JSR WaitForFrame ; DA7D: 20 F3 C8
|
|
JSR SubCFCF1 ; DA80: 20 F1 FC
|
|
JSR WaitForFrame ; DA83: 20 F3 C8
|
|
JSR SubCC84D ; DA86: 20 4D C8
|
|
JSR RefreshSequenceSpriteLayout ; DA89: 20 A8 CA
|
|
JSR SubCC916 ; DA8C: 20 16 C9
|
|
LDA $7E ; DA8F: A5 7E
|
|
STA $3B ; DA91: 85 3B
|
|
LDA $7D ; DA93: A5 7D
|
|
STA $38 ; DA95: 85 38
|
|
JSR UploadGeneratedCourseGrid ; DA97: 20 98 FC
|
|
LDY #$05 ; DA9A: A0 05
|
|
JSR WaitFrameGroups ; DA9C: 20 09 C9
|
|
JMP SubCDA2F ; DA9F: 4C 2F DA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; TitleAndAttractNmi
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DAA2.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
TitleAndAttractNmi:
|
|
JSR StrobeAndReadController ; DAA2: 20 7B C5
|
|
LDA JOY1 ; DAA5: AD 16 40
|
|
LDA JOY1 ; DAA8: AD 16 40
|
|
LDA title_input_mode ; DAAB: A5 09
|
|
BNE Label_DAEC ; DAAD: D0 3D
|
|
LDY menu_selection ; DAAF: A4 0D
|
|
LDA MenuCursorYPositions,Y ; DAB1: B9 0D DB
|
|
STA $0200 ; DAB4: 8D 00 02
|
|
LDA #$BA ; DAB7: A9 BA
|
|
STA $0201 ; DAB9: 8D 01 02
|
|
LDA #$00 ; DABC: A9 00
|
|
STA $0202 ; DABE: 8D 02 02
|
|
LDA #$28 ; DAC1: A9 28
|
|
STA $0203 ; DAC3: 8D 03 02
|
|
LDA JOY1 ; DAC6: AD 16 40
|
|
AND #$01 ; DAC9: 29 01
|
|
BEQ ReleaseMenuInputLatch ; DACB: F0 19
|
|
LDA menu_input_latch ; DACD: A5 0A
|
|
BNE LatchMenuInput ; DACF: D0 0B
|
|
LDY menu_selection ; DAD1: A4 0D
|
|
INY ; DAD3: C8
|
|
CPY #$03 ; DAD4: C0 03
|
|
BCC StoreMenuSelection ; DAD6: 90 02
|
|
LDY #$00 ; DAD8: A0 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; StoreMenuSelection
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DADA.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
StoreMenuSelection:
|
|
STY menu_selection ; DADA: 84 0D
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; LatchMenuInput
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DADC.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
LatchMenuInput:
|
|
LDA #$01 ; DADC: A9 01
|
|
STA menu_input_latch ; DADE: 85 0A
|
|
LDX #$FF ; DAE0: A2 FF
|
|
TXS ; DAE2: 9A
|
|
JMP SubCDA4C ; DAE3: 4C 4C DA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ReleaseMenuInputLatch
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DAE6.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
ReleaseMenuInputLatch:
|
|
LDA #$00 ; DAE6: A9 00
|
|
STA menu_input_latch ; DAE8: 85 0A
|
|
BEQ Label_DAFD ; DAEA: F0 11
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DAEC
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DAEC.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DAEC:
|
|
CMP #$02 ; DAEC: C9 02
|
|
BEQ Label_DB0A ; DAEE: F0 1A
|
|
LDA JOY1 ; DAF0: AD 16 40
|
|
AND #$01 ; DAF3: 29 01
|
|
BEQ Label_DAFD ; DAF5: F0 06
|
|
LDX #$FF ; DAF7: A2 FF
|
|
TXS ; DAF9: 9A
|
|
JMP SubCDA2F ; DAFA: 4C 2F DA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DAFD
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DAFD.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DAFD:
|
|
LDA JOY1 ; DAFD: AD 16 40
|
|
AND #$01 ; DB00: 29 01
|
|
BEQ Label_DB0A ; DB02: F0 06
|
|
LDX #$FF ; DB04: A2 FF
|
|
TXS ; DB06: 9A
|
|
JMP InitializeRuntimeState ; DB07: 4C C7 C0
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DB0A
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DB0A.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DB0A:
|
|
JMP NmiEpilogue ; DB0A: 4C B8 C0
|
|
; Menu cursor Y coordinates for the three selectable title entries.
|
|
MenuCursorYPositions:
|
|
.byte $78,$88,$98 ; DB0D-DB0F: 78 88 98
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCDB10
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DB10.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCDB10:
|
|
LDX #$20 ; DB10: A2 20
|
|
LDA #$00 ; DB12: A9 00
|
|
JSR SetPpuAddress ; DB14: 20 C1 C8
|
|
TAY ; DB17: A8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DB18
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DB18.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DB18:
|
|
LDA #$B8 ; DB18: A9 B8
|
|
STA PPUDATA ; DB1A: 8D 07 20
|
|
STA PPUDATA ; DB1D: 8D 07 20
|
|
STA PPUDATA ; DB20: 8D 07 20
|
|
STA PPUDATA ; DB23: 8D 07 20
|
|
LDA #$FF ; DB26: A9 FF
|
|
STA $0200,Y ; DB28: 99 00 02
|
|
INY ; DB2B: C8
|
|
BNE Label_DB18 ; DB2C: D0 EA
|
|
LDA #$20 ; DB2E: A9 20
|
|
STA $04 ; DB30: 85 04
|
|
LDA #$85 ; DB32: A9 85
|
|
STA $05 ; DB34: 85 05
|
|
LDX #$00 ; DB36: A2 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DB38
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DB38.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DB38:
|
|
LDY #$00 ; DB38: A0 00
|
|
LDA $04 ; DB3A: A5 04
|
|
STA PPUADDR ; DB3C: 8D 06 20
|
|
LDA $05 ; DB3F: A5 05
|
|
STA PPUADDR ; DB41: 8D 06 20
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DB44
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DB44.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DB44:
|
|
LDA $DC59,X ; DB44: BD 59 DC
|
|
STA PPUDATA ; DB47: 8D 07 20
|
|
INX ; DB4A: E8
|
|
INY ; DB4B: C8
|
|
CPY #$17 ; DB4C: C0 17
|
|
BCC Label_DB44 ; DB4E: 90 F4
|
|
LDA $05 ; DB50: A5 05
|
|
CLC ; DB52: 18
|
|
ADC #$20 ; DB53: 69 20
|
|
STA $05 ; DB55: 85 05
|
|
BCC Label_DB5B ; DB57: 90 02
|
|
INC $04 ; DB59: E6 04
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DB5B
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DB5B.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DB5B:
|
|
CPX #$CF ; DB5B: E0 CF
|
|
BCC Label_DB38 ; DB5D: 90 D9
|
|
LDX #$23 ; DB5F: A2 23
|
|
LDA #$C0 ; DB61: A9 C0
|
|
JSR SetPpuAddress ; DB63: 20 C1 C8
|
|
LDA #$00 ; DB66: A9 00
|
|
TAX ; DB68: AA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DB69
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DB69.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DB69:
|
|
STA PPUDATA ; DB69: 8D 07 20
|
|
CPX #$18 ; DB6C: E0 18
|
|
BNE Label_DB72 ; DB6E: D0 02
|
|
LDA #$50 ; DB70: A9 50
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DB72
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DB72.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DB72:
|
|
CPX #$20 ; DB72: E0 20
|
|
BNE Label_DB78 ; DB74: D0 02
|
|
LDA #$55 ; DB76: A9 55
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DB78
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DB78.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DB78:
|
|
CPX #$28 ; DB78: E0 28
|
|
BNE Label_DB7E ; DB7A: D0 02
|
|
LDA #$AF ; DB7C: A9 AF
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DB7E
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DB7E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DB7E:
|
|
CPX #$30 ; DB7E: E0 30
|
|
BNE Label_DB84 ; DB80: D0 02
|
|
LDA #$FF ; DB82: A9 FF
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DB84
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DB84.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DB84:
|
|
INX ; DB84: E8
|
|
CPX #$40 ; DB85: E0 40
|
|
BCC Label_DB69 ; DB87: 90 E0
|
|
JSR WaitForFrame ; DB89: 20 F3 C8
|
|
LDX #$3F ; DB8C: A2 3F
|
|
LDA #$00 ; DB8E: A9 00
|
|
JSR SetPpuAddress ; DB90: 20 C1 C8
|
|
TAX ; DB93: AA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DB94
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DB94.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DB94:
|
|
LDA $DD28,X ; DB94: BD 28 DD
|
|
STA PPUDATA ; DB97: 8D 07 20
|
|
INX ; DB9A: E8
|
|
CPX #$14 ; DB9B: E0 14
|
|
BCC Label_DB94 ; DB9D: 90 F5
|
|
LDX #$21 ; DB9F: A2 21
|
|
LDA #$E7 ; DBA1: A9 E7
|
|
JSR SetPpuAddress ; DBA3: 20 C1 C8
|
|
LDX #$01 ; DBA6: A2 01
|
|
STX PPUDATA ; DBA8: 8E 07 20
|
|
DEX ; DBAB: CA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DBAC
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DBAC.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DBAC:
|
|
LDA $DD3C,X ; DBAC: BD 3C DD
|
|
STA PPUDATA ; DBAF: 8D 07 20
|
|
INX ; DBB2: E8
|
|
CPX #$13 ; DBB3: E0 13
|
|
BCC Label_DBAC ; DBB5: 90 F5
|
|
LDX #$22 ; DBB7: A2 22
|
|
LDA #$27 ; DBB9: A9 27
|
|
JSR SetPpuAddress ; DBBB: 20 C1 C8
|
|
LDA #$02 ; DBBE: A9 02
|
|
STA PPUDATA ; DBC0: 8D 07 20
|
|
LDX #$00 ; DBC3: A2 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DBC5
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DBC5.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DBC5:
|
|
LDA $DD3C,X ; DBC5: BD 3C DD
|
|
STA PPUDATA ; DBC8: 8D 07 20
|
|
INX ; DBCB: E8
|
|
CPX #$13 ; DBCC: E0 13
|
|
BCC Label_DBC5 ; DBCE: 90 F5
|
|
LDX #$22 ; DBD0: A2 22
|
|
LDA #$67 ; DBD2: A9 67
|
|
JSR SetPpuAddress ; DBD4: 20 C1 C8
|
|
LDA #$02 ; DBD7: A9 02
|
|
STA PPUDATA ; DBD9: 8D 07 20
|
|
LDX #$00 ; DBDC: A2 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DBDE
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DBDE.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DBDE:
|
|
LDA $DD4F,X ; DBDE: BD 4F DD
|
|
STA PPUDATA ; DBE1: 8D 07 20
|
|
INX ; DBE4: E8
|
|
CPX #$13 ; DBE5: E0 13
|
|
BCC Label_DBDE ; DBE7: 90 F5
|
|
LDX #$22 ; DBE9: A2 22
|
|
LDA #$CA ; DBEB: A9 CA
|
|
JSR SetPpuAddress ; DBED: 20 C1 C8
|
|
LDA #$1D ; DBF0: A9 1D
|
|
STA PPUDATA ; DBF2: 8D 07 20
|
|
LDX #$18 ; DBF5: A2 18
|
|
STX PPUDATA ; DBF7: 8E 07 20
|
|
INX ; DBFA: E8
|
|
STX PPUDATA ; DBFB: 8E 07 20
|
|
LDX #$23 ; DBFE: A2 23
|
|
LDA #$25 ; DC00: A9 25
|
|
JSR SetPpuAddress ; DC02: 20 C1 C8
|
|
LDX #$00 ; DC05: A2 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DC07
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DC07.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DC07:
|
|
LDA $DD62,X ; DC07: BD 62 DD
|
|
STA PPUDATA ; DC0A: 8D 07 20
|
|
INX ; DC0D: E8
|
|
CPX #$16 ; DC0E: E0 16
|
|
BCC Label_DC07 ; DC10: 90 F5
|
|
LDX #$22 ; DC12: A2 22
|
|
LDA #$D3 ; DC14: A9 D3
|
|
JSR SetPpuAddress ; DC16: 20 C1 C8
|
|
LDA $0E ; DC19: A5 0E
|
|
STA $19 ; DC1B: 85 19
|
|
LDA #$00 ; DC1D: A9 00
|
|
STA $1A ; DC1F: 85 1A
|
|
JSR SubCCA30 ; DC21: 20 30 CA
|
|
LDX #$22 ; DC24: A2 22
|
|
LDA #$CF ; DC26: A9 CF
|
|
JSR SetPpuAddress ; DC28: 20 C1 C8
|
|
LDA #$00 ; DC2B: A9 00
|
|
STA $1A ; DC2D: 85 1A
|
|
LDA $0E ; DC2F: A5 0E
|
|
CMP #$48 ; DC31: C9 48
|
|
BNE Label_DC3D ; DC33: D0 08
|
|
LDA #$00 ; DC35: A9 00
|
|
STA $19 ; DC37: 85 19
|
|
LDA #$A8 ; DC39: A9 A8
|
|
BNE Label_DC53 ; DC3B: D0 16
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DC3D
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DC3D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DC3D:
|
|
LDA $0E ; DC3D: A5 0E
|
|
SEC ; DC3F: 38
|
|
SBC #$48 ; DC40: E9 48
|
|
STA $19 ; DC42: 85 19
|
|
BCC Label_DC4A ; DC44: 90 04
|
|
LDA #$A1 ; DC46: A9 A1
|
|
BNE Label_DC53 ; DC48: D0 09
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DC4A
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DC4A.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DC4A:
|
|
LDA #$48 ; DC4A: A9 48
|
|
SEC ; DC4C: 38
|
|
SBC $0E ; DC4D: E5 0E
|
|
STA $19 ; DC4F: 85 19
|
|
LDA #$A2 ; DC51: A9 A2
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DC53
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DC53.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DC53:
|
|
STA PPUDATA ; DC53: 8D 07 20
|
|
JMP SubCCA30 ; DC56: 4C 30 CA
|
|
.incbin "prg.bin", $1C59, $011F ; DC59-DD77: unclassified/data
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; DecodeCoursePackage
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DD78.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
DecodeCoursePackage:
|
|
LDA $49 ; DD78: A5 49
|
|
CMP $4A ; DD7A: C5 4A
|
|
BNE Label_DD7F ; DD7C: D0 01
|
|
RTS ; DD7E: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DD7F
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DD7F.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DD7F:
|
|
JSR ClearOamShadowLoop ; DD7F: 20 E8 C8
|
|
LDA #$9D ; DD82: A9 9D
|
|
LDY #$00 ; DD84: A0 00
|
|
STY PPUMASK ; DD86: 8C 01 20
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DD89
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DD89.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DD89:
|
|
STA $0300,Y ; DD89: 99 00 03
|
|
STA $0400,Y ; DD8C: 99 00 04
|
|
INY ; DD8F: C8
|
|
BNE Label_DD89 ; DD90: D0 F7
|
|
LDY #$3F ; DD92: A0 3F
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DD94
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DD94.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DD94:
|
|
LDA $E243,Y ; DD94: B9 43 E2
|
|
STA $0100,Y ; DD97: 99 00 01
|
|
DEY ; DD9A: 88
|
|
BPL Label_DD94 ; DD9B: 10 F7
|
|
LDA $49 ; DD9D: A5 49
|
|
BEQ Label_DDA4 ; DD9F: F0 03
|
|
JMP SubCE3FC ; DDA1: 4C FC E3
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DDA4
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DDA4.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DDA4:
|
|
LDY $2B ; DDA4: A4 2B
|
|
LDA $E6C3,Y ; DDA6: B9 C3 E6
|
|
STA $04 ; DDA9: 85 04
|
|
LDA $E6D5,Y ; DDAB: B9 D5 E6
|
|
STA $05 ; DDAE: 85 05
|
|
LDA #$00 ; DDB0: A9 00
|
|
STA $06 ; DDB2: 85 06
|
|
LDA #$03 ; DDB4: A9 03
|
|
STA $07 ; DDB6: 85 07
|
|
JSR SubCDE35 ; DDB8: 20 35 DE
|
|
TAY ; DDBB: A8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DDBC
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DDBC.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DDBC:
|
|
LDA ($04),Y ; DDBC: B1 04
|
|
STA a:$0019,Y ; DDBE: 99 19 00
|
|
INY ; DDC1: C8
|
|
CPY #$03 ; DDC2: C0 03
|
|
BCC Label_DDBC ; DDC4: 90 F6
|
|
JSR SubCE1AB ; DDC6: 20 AB E1
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DDC9
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DDC9.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DDC9:
|
|
LDY $1C ; DDC9: A4 1C
|
|
INC $1C ; DDCB: E6 1C
|
|
LDA ($04),Y ; DDCD: B1 04
|
|
CMP #$FF ; DDCF: C9 FF
|
|
BEQ Label_DE3C ; DDD1: F0 69
|
|
CMP #$30 ; DDD3: C9 30
|
|
BCC Label_DDE7 ; DDD5: 90 10
|
|
AND #$F0 ; DDD7: 29 F0
|
|
CMP #$A0 ; DDD9: C9 A0
|
|
BEQ Label_DDE7 ; DDDB: F0 0A
|
|
LDA ($04),Y ; DDDD: B1 04
|
|
LDY $1D ; DDDF: A4 1D
|
|
STA ($06),Y ; DDE1: 91 06
|
|
INY ; DDE3: C8
|
|
JMP SubCDE1A ; DDE4: 4C 1A DE
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DDE7
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DDE7.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DDE7:
|
|
LDA ($04),Y ; DDE7: B1 04
|
|
AND #$0F ; DDE9: 29 0F
|
|
TAX ; DDEB: AA
|
|
LDA ($04),Y ; DDEC: B1 04
|
|
JSR SubCDA1E ; DDEE: 20 1E DA
|
|
CMP #$0A ; DDF1: C9 0A
|
|
BNE Label_DE0E ; DDF3: D0 19
|
|
LDY $1D ; DDF5: A4 1D
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DDF7
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DDF7.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DDF7:
|
|
INC $8D ; DDF7: E6 8D
|
|
LDA $8D ; DDF9: A5 8D
|
|
CMP #$03 ; DDFB: C9 03
|
|
BCC Label_DE03 ; DDFD: 90 04
|
|
LDA #$00 ; DDFF: A9 00
|
|
STA $8D ; DE01: 85 8D
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DE03
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DE03.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DE03:
|
|
CLC ; DE03: 18
|
|
ADC #$AB ; DE04: 69 AB
|
|
STA ($06),Y ; DE06: 91 06
|
|
INY ; DE08: C8
|
|
DEX ; DE09: CA
|
|
BPL Label_DDF7 ; DE0A: 10 EB
|
|
BMI SubCDE1A ; DE0C: 30 0C
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DE0E
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DE0E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DE0E:
|
|
TAY ; DE0E: A8
|
|
LDA a:$0019,Y ; DE0F: B9 19 00
|
|
LDY $1D ; DE12: A4 1D
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DE14
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DE14.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DE14:
|
|
STA ($06),Y ; DE14: 91 06
|
|
INY ; DE16: C8
|
|
DEX ; DE17: CA
|
|
BPL Label_DE14 ; DE18: 10 FA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCDE1A
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DE1A.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCDE1A:
|
|
STY $1D ; DE1A: 84 1D
|
|
CPY #$10 ; DE1C: C0 10
|
|
BCC Label_DDC9 ; DE1E: 90 A9
|
|
LDY $1C ; DE20: A4 1C
|
|
JSR SubCE1AB ; DE22: 20 AB E1
|
|
LDA $06 ; DE25: A5 06
|
|
CLC ; DE27: 18
|
|
ADC #$10 ; DE28: 69 10
|
|
STA $06 ; DE2A: 85 06
|
|
BCC Label_DE30 ; DE2C: 90 02
|
|
INC $07 ; DE2E: E6 07
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DE30
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DE30.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DE30:
|
|
JSR SubCDE35 ; DE30: 20 35 DE
|
|
BEQ Label_DDC9 ; DE33: F0 94
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCDE35
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DE35.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCDE35:
|
|
LDA #$00 ; DE35: A9 00
|
|
STA $1C ; DE37: 85 1C
|
|
STA $1D ; DE39: 85 1D
|
|
RTS ; DE3B: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DE3C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DE3C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DE3C:
|
|
INY ; DE3C: C8
|
|
JSR SubCE1AB ; DE3D: 20 AB E1
|
|
LDA ($04),Y ; DE40: B1 04
|
|
INY ; DE42: C8
|
|
CMP #$55 ; DE43: C9 55
|
|
BEQ ParseHoleObjectPackage ; DE45: F0 17
|
|
LDY #$00 ; DE47: A0 00
|
|
LDX #$04 ; DE49: A2 04
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DE4B
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DE4B.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DE4B:
|
|
LDA ($04),Y ; DE4B: B1 04
|
|
STA $0100,X ; DE4D: 9D 00 01
|
|
INY ; DE50: C8
|
|
INX ; DE51: E8
|
|
TXA ; DE52: 8A
|
|
AND #$07 ; DE53: 29 07
|
|
BNE Label_DE4B ; DE55: D0 F4
|
|
JSR SubCD4F2 ; DE57: 20 F2 D4
|
|
CPX #$44 ; DE5A: E0 44
|
|
BCC Label_DE4B ; DE5C: 90 ED
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ParseHoleObjectPackage
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DE5E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
ParseHoleObjectPackage:
|
|
JSR SubCE1AB ; DE5E: 20 AB E1
|
|
LDX #$98 ; DE61: A2 98
|
|
LDA ($04),Y ; DE63: B1 04
|
|
STA $0200,X ; DE65: 9D 00 02
|
|
CLC ; DE68: 18
|
|
ADC #$07 ; DE69: 69 07
|
|
STA $65 ; DE6B: 85 65
|
|
INY ; DE6D: C8
|
|
INX ; DE6E: E8
|
|
LDA #$DA ; DE6F: A9 DA
|
|
STA $0200,X ; DE71: 9D 00 02
|
|
INX ; DE74: E8
|
|
LDA #$01 ; DE75: A9 01
|
|
STA $0200,X ; DE77: 9D 00 02
|
|
INX ; DE7A: E8
|
|
LDA ($04),Y ; DE7B: B1 04
|
|
STA $0200,X ; DE7D: 9D 00 02
|
|
CLC ; DE80: 18
|
|
ADC #$02 ; DE81: 69 02
|
|
STA $66 ; DE83: 85 66
|
|
INY ; DE85: C8
|
|
INX ; DE86: E8
|
|
LDA ($04),Y ; DE87: B1 04
|
|
PHA ; DE89: 48
|
|
LSR A ; DE8A: 4A
|
|
STA $57 ; DE8B: 85 57
|
|
INY ; DE8D: C8
|
|
LDA ($04),Y ; DE8E: B1 04
|
|
STA $1A ; DE90: 85 1A
|
|
INY ; DE92: C8
|
|
LDA ($04),Y ; DE93: B1 04
|
|
STA $1B ; DE95: 85 1B
|
|
INY ; DE97: C8
|
|
STY $1C ; DE98: 84 1C
|
|
PLA ; DE9A: 68
|
|
TAY ; DE9B: A8
|
|
LDA $E37E,Y ; DE9C: B9 7E E3
|
|
STA $19 ; DE9F: 85 19
|
|
LDA $E37D,Y ; DEA1: B9 7D E3
|
|
TAY ; DEA4: A8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DEA5
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DEA5.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DEA5:
|
|
LDA $E384,Y ; DEA5: B9 84 E3
|
|
CLC ; DEA8: 18
|
|
ADC $1A ; DEA9: 65 1A
|
|
STA $0200,X ; DEAB: 9D 00 02
|
|
INX ; DEAE: E8
|
|
LDA $E3A2,Y ; DEAF: B9 A2 E3
|
|
STA $0200,X ; DEB2: 9D 00 02
|
|
INX ; DEB5: E8
|
|
LDA $E3C0,Y ; DEB6: B9 C0 E3
|
|
STA $0200,X ; DEB9: 9D 00 02
|
|
INX ; DEBC: E8
|
|
LDA $E3DE,Y ; DEBD: B9 DE E3
|
|
CLC ; DEC0: 18
|
|
ADC $1B ; DEC1: 65 1B
|
|
STA $0200,X ; DEC3: 9D 00 02
|
|
INX ; DEC6: E8
|
|
INY ; DEC7: C8
|
|
CPY $19 ; DEC8: C4 19
|
|
BCC Label_DEA5 ; DECA: 90 D9
|
|
LDY $1C ; DECC: A4 1C
|
|
LDA ($04),Y ; DECE: B1 04
|
|
STA $0200,X ; DED0: 9D 00 02
|
|
STA $0204,X ; DED3: 9D 04 02
|
|
CLC ; DED6: 18
|
|
ADC #$06 ; DED7: 69 06
|
|
STA $7E ; DED9: 85 7E
|
|
INX ; DEDB: E8
|
|
LDA #$8C ; DEDC: A9 8C
|
|
STA $0200,X ; DEDE: 9D 00 02
|
|
STA $0204,X ; DEE1: 9D 04 02
|
|
INX ; DEE4: E8
|
|
LDA #$00 ; DEE5: A9 00
|
|
STA $0200,X ; DEE7: 9D 00 02
|
|
STA $0204,X ; DEEA: 9D 04 02
|
|
INY ; DEED: C8
|
|
INX ; DEEE: E8
|
|
LDA ($04),Y ; DEEF: B1 04
|
|
STA $0200,X ; DEF1: 9D 00 02
|
|
CLC ; DEF4: 18
|
|
ADC #$0B ; DEF5: 69 0B
|
|
STA $7D ; DEF7: 85 7D
|
|
CLC ; DEF9: 18
|
|
ADC #$05 ; DEFA: 69 05
|
|
STA $0204,X ; DEFC: 9D 04 02
|
|
JSR SubCD4F1 ; DEFF: 20 F1 D4
|
|
INX ; DF02: E8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ParseHoleObjectList
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DF03.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
ParseHoleObjectList:
|
|
LDA ($04),Y ; DF03: B1 04
|
|
CMP #$FF ; DF05: C9 FF
|
|
BEQ Label_DF54 ; DF07: F0 4B
|
|
STA $19 ; DF09: 85 19
|
|
INY ; DF0B: C8
|
|
LDA ($04),Y ; DF0C: B1 04
|
|
STA $1A ; DF0E: 85 1A
|
|
INY ; DF10: C8
|
|
LDA ($04),Y ; DF11: B1 04
|
|
STA $1B ; DF13: 85 1B
|
|
INY ; DF15: C8
|
|
STY $1C ; DF16: 84 1C
|
|
LDY $19 ; DF18: A4 19
|
|
LDA $E284,Y ; DF1A: B9 84 E2
|
|
STA $1D ; DF1D: 85 1D
|
|
LDA $E283,Y ; DF1F: B9 83 E2
|
|
TAY ; DF22: A8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DF23
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DF23.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DF23:
|
|
LDA $E2EB,Y ; DF23: B9 EB E2
|
|
CLC ; DF26: 18
|
|
ADC $1A ; DF27: 65 1A
|
|
STA $0200,X ; DF29: 9D 00 02
|
|
INX ; DF2C: E8
|
|
LDA $E2A2,Y ; DF2D: B9 A2 E2
|
|
STA $0200,X ; DF30: 9D 00 02
|
|
INX ; DF33: E8
|
|
CPY #$2B ; DF34: C0 2B
|
|
BCC Label_DF3B ; DF36: 90 03
|
|
LDA #$42 ; DF38: A9 42
|
|
; Overlapping instruction idiom:
|
|
; DF3A: BIT $02A9 (2C A9 02)
|
|
; DF3B: LDA #$02 (A9 02)
|
|
Label_DF3A:
|
|
.byte $2C ; DF3A: 2C BIT absolute opcode
|
|
Label_DF3B:
|
|
.byte $A9,$02 ; DF3B-DF3C: A9 02 LDA #$02
|
|
STA $0200,X ; DF3D: 9D 00 02
|
|
INX ; DF40: E8
|
|
LDA $E334,Y ; DF41: B9 34 E3
|
|
CLC ; DF44: 18
|
|
ADC $1B ; DF45: 65 1B
|
|
STA $0200,X ; DF47: 9D 00 02
|
|
INX ; DF4A: E8
|
|
INY ; DF4B: C8
|
|
CPY $1D ; DF4C: C4 1D
|
|
BCC Label_DF23 ; DF4E: 90 D3
|
|
LDY $1C ; DF50: A4 1C
|
|
BNE ParseHoleObjectList ; DF52: D0 AF
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DF54
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DF54.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DF54:
|
|
LDA $0D ; DF54: A5 0D
|
|
BEQ SubCDFB8 ; DF56: F0 60
|
|
LDA $7B ; DF58: A5 7B
|
|
CMP #$03 ; DF5A: C9 03
|
|
BEQ SubCDFB8 ; DF5C: F0 5A
|
|
LDA $7C ; DF5E: A5 7C
|
|
CMP #$03 ; DF60: C9 03
|
|
BEQ SubCDFB8 ; DF62: F0 54
|
|
LDA $7F ; DF64: A5 7F
|
|
BNE Label_DF6C ; DF66: D0 04
|
|
LDA $80 ; DF68: A5 80
|
|
BEQ SubCDFB8 ; DF6A: F0 4C
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DF6C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DF6C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DF6C:
|
|
LDA #$DD ; DF6C: A9 DD
|
|
STA $0201 ; DF6E: 8D 01 02
|
|
LDA #$F3 ; DF71: A9 F3
|
|
STA $0205 ; DF73: 8D 05 02
|
|
LDA #$01 ; DF76: A9 01
|
|
STA $0202 ; DF78: 8D 02 02
|
|
STA $0206 ; DF7B: 8D 06 02
|
|
LDA $7F ; DF7E: A5 7F
|
|
BEQ Label_DF91 ; DF80: F0 0F
|
|
LDA $65 ; DF82: A5 65
|
|
STA $0200 ; DF84: 8D 00 02
|
|
LDY $66 ; DF87: A4 66
|
|
DEY ; DF89: 88
|
|
DEY ; DF8A: 88
|
|
STY $0203 ; DF8B: 8C 03 02
|
|
JMP SubCDF9B ; DF8E: 4C 9B DF
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DF91
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DF91.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DF91:
|
|
LDA $40 ; DF91: A5 40
|
|
STA $0200 ; DF93: 8D 00 02
|
|
LDA $3E ; DF96: A5 3E
|
|
STA $0203 ; DF98: 8D 03 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCDF9B
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DF9B.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCDF9B:
|
|
LDA $80 ; DF9B: A5 80
|
|
BEQ Label_DFAE ; DF9D: F0 0F
|
|
LDA $65 ; DF9F: A5 65
|
|
STA $0204 ; DFA1: 8D 04 02
|
|
LDY $66 ; DFA4: A4 66
|
|
DEY ; DFA6: 88
|
|
DEY ; DFA7: 88
|
|
STY $0207 ; DFA8: 8C 07 02
|
|
JMP SubCDFB8 ; DFAB: 4C B8 DF
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DFAE
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DFAE.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DFAE:
|
|
LDA $41 ; DFAE: A5 41
|
|
STA $0204 ; DFB0: 8D 04 02
|
|
LDA $3F ; DFB3: A5 3F
|
|
STA $0207 ; DFB5: 8D 07 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCDFB8
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DFB8.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCDFB8:
|
|
JSR WaitForFrame ; DFB8: 20 F3 C8
|
|
LDA #$20 ; DFBB: A9 20
|
|
STA $06 ; DFBD: 85 06
|
|
LDA #$10 ; DFBF: A9 10
|
|
STA $07 ; DFC1: 85 07
|
|
LDA #$00 ; DFC3: A9 00
|
|
STA $04 ; DFC5: 85 04
|
|
LDA #$03 ; DFC7: A9 03
|
|
STA $05 ; DFC9: 85 05
|
|
LDX #$1D ; DFCB: A2 1D
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DFCD
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DFCD.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DFCD:
|
|
LDY #$00 ; DFCD: A0 00
|
|
LDA $06 ; DFCF: A5 06
|
|
STA PPUADDR ; DFD1: 8D 06 20
|
|
LDA $07 ; DFD4: A5 07
|
|
STA PPUADDR ; DFD6: 8D 06 20
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DFD9
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DFD9.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DFD9:
|
|
LDA ($04),Y ; DFD9: B1 04
|
|
STA PPUDATA ; DFDB: 8D 07 20
|
|
INY ; DFDE: C8
|
|
CPY #$10 ; DFDF: C0 10
|
|
BCC Label_DFD9 ; DFE1: 90 F6
|
|
JSR SubCE1AB ; DFE3: 20 AB E1
|
|
LDA $07 ; DFE6: A5 07
|
|
CLC ; DFE8: 18
|
|
ADC #$20 ; DFE9: 69 20
|
|
STA $07 ; DFEB: 85 07
|
|
BCC Label_DFF1 ; DFED: 90 02
|
|
INC $06 ; DFEF: E6 06
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DFF1
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DFF1.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DFF1:
|
|
DEX ; DFF1: CA
|
|
BPL Label_DFCD ; DFF2: 10 D9
|
|
INX ; DFF4: E8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_DFF5
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $DFF5.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_DFF5:
|
|
LDA $0100,X ; DFF5: BD 00 01
|
|
STA PPUDATA ; DFF8: 8D 07 20
|
|
INX ; DFFB: E8
|
|
CPX #$40 ; DFFC: E0 40
|
|
BCC Label_DFF5 ; DFFE: 90 F5
|
|
JSR WaitForFrame ; E000: 20 F3 C8
|
|
LDX #$20 ; E003: A2 20
|
|
LDA #$61 ; E005: A9 61
|
|
JSR SetPpuAddress ; E007: 20 C1 C8
|
|
LDA ppu_ctrl_shadow ; E00A: A5 00
|
|
ORA #$04 ; E00C: 09 04
|
|
STA PPUCTRL ; E00E: 8D 00 20
|
|
LDY #$D1 ; E011: A0 D1
|
|
JSR SubCC589 ; E013: 20 89 C5
|
|
LDX #$20 ; E016: A2 20
|
|
LDA #$6F ; E018: A9 6F
|
|
JSR SubCC586 ; E01A: 20 86 C5
|
|
JSR RestorePpuCtrlShadow ; E01D: 20 B5 C8
|
|
LDX #$20 ; E020: A2 20
|
|
LDA #$C2 ; E022: A9 C2
|
|
JSR SubCE1A1 ; E024: 20 A1 E1
|
|
LDX #$21 ; E027: A2 21
|
|
LDA #$02 ; E029: A9 02
|
|
JSR SubCE1A1 ; E02B: 20 A1 E1
|
|
LDX #$20 ; E02E: A2 20
|
|
LDA #$E2 ; E030: A9 E2
|
|
JSR SetPpuAddress ; E032: 20 C1 C8
|
|
LDA #$0C ; E035: A9 0C
|
|
STA $19 ; E037: 85 19
|
|
LDA $0D ; E039: A5 0D
|
|
CMP #$02 ; E03B: C9 02
|
|
BNE Label_E043 ; E03D: D0 04
|
|
LDA #$04 ; E03F: A9 04
|
|
STA $19 ; E041: 85 19
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E043
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E043.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E043:
|
|
LDY #$00 ; E043: A0 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E045
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E045.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E045:
|
|
LDA $E1F9,Y ; E045: B9 F9 E1
|
|
STA PPUDATA ; E048: 8D 07 20
|
|
INY ; E04B: C8
|
|
CPY $19 ; E04C: C4 19
|
|
BCC Label_E045 ; E04E: 90 F5
|
|
LDY #$03 ; E050: A0 03
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E052
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E052.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E052:
|
|
LDX $E1D8,Y ; E052: BE D8 E1
|
|
LDA $E1DC,Y ; E055: B9 DC E1
|
|
JSR SetPpuAddress ; E058: 20 C1 C8
|
|
LDA $E1E0,Y ; E05B: B9 E0 E1
|
|
STA PPUDATA ; E05E: 8D 07 20
|
|
DEY ; E061: 88
|
|
BPL Label_E052 ; E062: 10 EE
|
|
LDX #$20 ; E064: A2 20
|
|
LDA #$43 ; E066: A9 43
|
|
JSR SetPpuAddress ; E068: 20 C1 C8
|
|
LDY #$00 ; E06B: A0 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E06D
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E06D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E06D:
|
|
LDA $0D ; E06D: A5 0D
|
|
CMP #$02 ; E06F: C9 02
|
|
BEQ Label_E079 ; E071: F0 06
|
|
LDA $DD44,Y ; E073: B9 44 DD
|
|
JMP SubCE07C ; E076: 4C 7C E0
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E079
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E079.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E079:
|
|
LDA $DD57,Y ; E079: B9 57 DD
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCE07C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E07C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCE07C:
|
|
STA PPUDATA ; E07C: 8D 07 20
|
|
INY ; E07F: C8
|
|
CPY #$0B ; E080: C0 0B
|
|
BCC Label_E06D ; E082: 90 E9
|
|
LDX #$21 ; E084: A2 21
|
|
LDA #$22 ; E086: A9 22
|
|
JSR SetPpuAddress ; E088: 20 C1 C8
|
|
LDA #$A9 ; E08B: A9 A9
|
|
STA PPUDATA ; E08D: 8D 07 20
|
|
LDA #$2D ; E090: A9 2D
|
|
STA PPUDATA ; E092: 8D 07 20
|
|
LDA $82 ; E095: A5 82
|
|
BEQ Label_E0A0 ; E097: F0 07
|
|
LDA $0143 ; E099: AD 43 01
|
|
BEQ Label_E0B5 ; E09C: F0 17
|
|
BNE Label_E0A4 ; E09E: D0 04
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E0A0
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E0A0.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E0A0:
|
|
LDA $0D ; E0A0: A5 0D
|
|
BEQ Label_E0B5 ; E0A2: F0 11
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E0A4
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E0A4.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E0A4:
|
|
LDX #$21 ; E0A4: A2 21
|
|
LDA #$62 ; E0A6: A9 62
|
|
JSR SetPpuAddress ; E0A8: 20 C1 C8
|
|
LDA #$AA ; E0AB: A9 AA
|
|
STA PPUDATA ; E0AD: 8D 07 20
|
|
LDA #$2D ; E0B0: A9 2D
|
|
STA PPUDATA ; E0B2: 8D 07 20
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E0B5
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E0B5.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E0B5:
|
|
LDX #$20 ; E0B5: A2 20
|
|
LDA #$62 ; E0B7: A9 62
|
|
JSR SetPpuAddress ; E0B9: 20 C1 C8
|
|
LDY #$00 ; E0BC: A0 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCE0BE
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E0BE.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCE0BE:
|
|
LDA $2B ; E0BE: A5 2B
|
|
CMP #$09 ; E0C0: C9 09
|
|
BCS Label_E0CA ; E0C2: B0 06
|
|
LDA $E1EC,Y ; E0C4: B9 EC E1
|
|
JMP SubCE0CD ; E0C7: 4C CD E0
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E0CA
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E0CA.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E0CA:
|
|
LDA $E1F0,Y ; E0CA: B9 F0 E1
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCE0CD
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E0CD.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCE0CD:
|
|
CMP #$FF ; E0CD: C9 FF
|
|
BEQ Label_E0D8 ; E0CF: F0 07
|
|
STA PPUDATA ; E0D1: 8D 07 20
|
|
INY ; E0D4: C8
|
|
JMP SubCE0BE ; E0D5: 4C BE E0
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E0D8
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E0D8.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E0D8:
|
|
LDA #$9D ; E0D8: A9 9D
|
|
STA PPUDATA ; E0DA: 8D 07 20
|
|
LDA $2B ; E0DD: A5 2B
|
|
CMP #$09 ; E0DF: C9 09
|
|
BCC Label_E0ED ; E0E1: 90 0A
|
|
LDA #$01 ; E0E3: A9 01
|
|
STA PPUDATA ; E0E5: 8D 07 20
|
|
LDA $2B ; E0E8: A5 2B
|
|
SEC ; E0EA: 38
|
|
SBC #$0A ; E0EB: E9 0A
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E0ED
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E0ED.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E0ED:
|
|
CLC ; E0ED: 18
|
|
ADC #$01 ; E0EE: 69 01
|
|
STA PPUDATA ; E0F0: 8D 07 20
|
|
LDX #$20 ; E0F3: A2 20
|
|
LDA #$82 ; E0F5: A9 82
|
|
JSR SetPpuAddress ; E0F7: 20 C1 C8
|
|
LDX $2B ; E0FA: A6 2B
|
|
LDA $E21F,X ; E0FC: BD 1F E2
|
|
STA PPUDATA ; E0FF: 8D 07 20
|
|
LDA $E231,X ; E102: BD 31 E2
|
|
JSR SubCDA1E ; E105: 20 1E DA
|
|
STA PPUDATA ; E108: 8D 07 20
|
|
LDA $E231,X ; E10B: BD 31 E2
|
|
AND #$0F ; E10E: 29 0F
|
|
STA PPUDATA ; E110: 8D 07 20
|
|
LDA #$A4 ; E113: A9 A4
|
|
STA PPUDATA ; E115: 8D 07 20
|
|
LDX #$20 ; E118: A2 20
|
|
LDA #$A2 ; E11A: A9 A2
|
|
JSR SetPpuAddress ; E11C: 20 C1 C8
|
|
LDY #$00 ; E11F: A0 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E121
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E121.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E121:
|
|
LDA $E1E8,Y ; E121: B9 E8 E1
|
|
STA PPUDATA ; E124: 8D 07 20
|
|
INY ; E127: C8
|
|
CPY #$04 ; E128: C0 04
|
|
BCC Label_E121 ; E12A: 90 F5
|
|
LDX $2B ; E12C: A6 2B
|
|
LDA $E20D,X ; E12E: BD 0D E2
|
|
AND #$0F ; E131: 29 0F
|
|
STA PPUDATA ; E133: 8D 07 20
|
|
STA $83 ; E136: 85 83
|
|
LDX #$23 ; E138: A2 23
|
|
LDA #$45 ; E13A: A9 45
|
|
JSR SetPpuAddress ; E13C: 20 C1 C8
|
|
LDY #$00 ; E13F: A0 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E141
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E141.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E141:
|
|
LDA $E1E4,Y ; E141: B9 E4 E1
|
|
STA PPUDATA ; E144: 8D 07 20
|
|
INY ; E147: C8
|
|
CPY #$04 ; E148: C0 04
|
|
BCC Label_E141 ; E14A: 90 F5
|
|
LDA #$21 ; E14C: A9 21
|
|
STA $04 ; E14E: 85 04
|
|
LDA #$82 ; E150: A9 82
|
|
STA $05 ; E152: 85 05
|
|
LDX #$0B ; E154: A2 0B
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E156
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E156.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E156:
|
|
LDY #$0B ; E156: A0 0B
|
|
LDA $04 ; E158: A5 04
|
|
STA PPUADDR ; E15A: 8D 06 20
|
|
LDA $05 ; E15D: A5 05
|
|
STA PPUADDR ; E15F: 8D 06 20
|
|
CPX #$04 ; E162: E0 04
|
|
BCC Label_E16A ; E164: 90 04
|
|
LDA #$9D ; E166: A9 9D
|
|
BNE Label_E16C ; E168: D0 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E16A
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E16A.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E16A:
|
|
LDA #$B8 ; E16A: A9 B8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E16C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E16C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E16C:
|
|
STA PPUDATA ; E16C: 8D 07 20
|
|
DEY ; E16F: 88
|
|
BPL Label_E16C ; E170: 10 FA
|
|
LDA $05 ; E172: A5 05
|
|
CLC ; E174: 18
|
|
ADC #$20 ; E175: 69 20
|
|
STA $05 ; E177: 85 05
|
|
LDA $04 ; E179: A5 04
|
|
ADC #$00 ; E17B: 69 00
|
|
STA $04 ; E17D: 85 04
|
|
DEX ; E17F: CA
|
|
BPL Label_E156 ; E180: 10 D4
|
|
LDX #$3F ; E182: A2 3F
|
|
LDA #$00 ; E184: A9 00
|
|
JSR SetPpuAddress ; E186: 20 C1 C8
|
|
LDY #$00 ; E189: A0 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E18B
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E18B.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E18B:
|
|
LDA $E1B8,Y ; E18B: B9 B8 E1
|
|
STA PPUDATA ; E18E: 8D 07 20
|
|
INY ; E191: C8
|
|
CPY #$20 ; E192: C0 20
|
|
BCC Label_E18B ; E194: 90 F5
|
|
JSR SpriteOffsetForController ; E196: 20 94 C8
|
|
LDA #$FF ; E199: A9 FF
|
|
STA $0200,X ; E19B: 9D 00 02
|
|
JMP SubCC89A ; E19E: 4C 9A C8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCE1A1
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E1A1.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCE1A1:
|
|
JSR SetPpuAddress ; E1A1: 20 C1 C8
|
|
LDA #$A0 ; E1A4: A9 A0
|
|
LDY #$0C ; E1A6: A0 0C
|
|
JMP SubCC599 ; E1A8: 4C 99 C5
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCE1AB
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E1AB.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCE1AB:
|
|
TYA ; E1AB: 98
|
|
CLC ; E1AC: 18
|
|
ADC $04 ; E1AD: 65 04
|
|
STA $04 ; E1AF: 85 04
|
|
BCC Label_E1B5 ; E1B1: 90 02
|
|
INC $05 ; E1B3: E6 05
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E1B5
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E1B5.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E1B5:
|
|
LDY #$00 ; E1B5: A0 00
|
|
RTS ; E1B7: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; GameplayPpuPalette
|
|
|
|
; Thirty-two PPU palette bytes uploaded to $3F00-$3F1F.
|
|
; Range: $E1B8-$E1D7 (32 bytes)
|
|
; ---------------------------------------------------------------------------
|
|
GameplayPpuPalette:
|
|
.byte $29,$19,$07,$0F,$29,$19,$36,$0F,$29,$21,$30,$0F,$29,$19,$07,$21 ; E1B8-E1C7: 29 19 07 0F 29 19 36 0F 29 21 30 0F 29 19 07 21
|
|
.byte $29,$01,$30,$27,$29,$25,$30,$0F,$29,$1A,$36,$0F,$29,$10,$30,$07 ; E1C8-E1D7: 29 01 30 27 29 25 30 0F 29 1A 36 0F 29 10 30 07
|
|
.incbin "prg.bin", $21D8, $00AA ; E1D8-E281: audited separately / remaining data
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ObjectSpanStartZero
|
|
|
|
; Implicit zero start boundary for object selector zero.
|
|
; Range: $E282-$E282 (1 bytes)
|
|
; ---------------------------------------------------------------------------
|
|
ObjectSpanStartZero:
|
|
.byte $00 ; E282-E282: 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ObjectSpanEnds
|
|
|
|
; Exclusive end offsets for object sprite slices.
|
|
; Range: $E283-$E2A1 (31 bytes)
|
|
; ---------------------------------------------------------------------------
|
|
ObjectSpanEnds:
|
|
.byte $00,$03,$07,$09,$0B,$0E,$10,$12,$14,$16,$19,$1B,$1E,$20,$23,$25 ; E283-E292: 00 03 07 09 0B 0E 10 12 14 16 19 1B 1E 20 23 25
|
|
.byte $27,$29,$2B,$2E,$31,$34,$38,$3A,$3C,$3E,$40,$43,$45,$47,$49 ; E293-E2A1: 27 29 2B 2E 31 34 38 3A 3C 3E 40 43 45 47 49
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ObjectTileTable
|
|
|
|
; Seventy-three CHR tile values for variable object expansion.
|
|
; Range: $E2A2-$E2EA (73 bytes)
|
|
; ---------------------------------------------------------------------------
|
|
ObjectTileTable:
|
|
.byte $E0,$E1,$E2,$E3,$E4,$E5,$E6,$E7,$E8,$E9,$EA,$E5,$EB,$EC,$ED,$EE ; E2A2-E2B1: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA E5 EB EC ED EE
|
|
.byte $F2,$E8,$EF,$F0,$F1,$EE,$E0,$E1,$E2,$E7,$E8,$E7,$E1,$E2,$E7,$E8 ; E2B2-E2C1: F2 E8 EF F0 F1 EE E0 E1 E2 E7 E8 E7 E1 E2 E7 E8
|
|
.byte $E5,$EB,$EC,$E9,$EA,$F1,$EE,$ED,$EE,$EF,$F0,$E0,$E1,$E2,$E0,$E1 ; E2C2-E2D1: E5 EB EC E9 EA F1 EE ED EE EF F0 E0 E1 E2 E0 E1
|
|
.byte $E2,$E0,$E1,$E2,$E4,$E3,$E6,$E5,$E7,$E8,$EA,$E9,$F0,$EF,$EE,$ED ; E2D2-E2E1: E2 E0 E1 E2 E4 E3 E6 E5 E7 E8 EA E9 F0 EF EE ED
|
|
.byte $E0,$E1,$E2,$E7,$E8,$EE,$F1,$F2,$E8 ; E2E2-E2EA: E0 E1 E2 E7 E8 EE F1 F2 E8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ObjectXOffsetTable
|
|
|
|
; Seventy-three X offsets parallel to ObjectTileTable.
|
|
; Range: $E2EB-$E333 (73 bytes)
|
|
; ---------------------------------------------------------------------------
|
|
ObjectXOffsetTable:
|
|
.byte $00,$08,$10,$00,$00,$08,$08,$00,$08,$03,$00,$00,$01,$00,$00,$00 ; E2EB-E2FA: 00 08 10 00 00 08 08 00 08 03 00 00 01 00 00 00
|
|
.byte $00,$08,$00,$00,$00,$00,$00,$08,$10,$00,$08,$00,$08,$10,$00,$08 ; E2FB-E30A: 00 08 00 00 00 00 00 08 10 00 08 00 08 10 00 08
|
|
.byte $00,$01,$01,$01,$00,$00,$01,$00,$01,$00,$01,$00,$08,$10,$00,$08 ; E30B-E31A: 00 01 01 01 00 00 01 00 01 00 01 00 08 10 00 08
|
|
.byte $10,$00,$08,$10,$00,$00,$08,$08,$00,$08,$00,$03,$00,$00,$00,$00 ; E31B-E32A: 10 00 08 10 00 00 08 08 00 08 00 03 00 00 00 00
|
|
.byte $00,$08,$10,$00,$08,$00,$00,$00,$08 ; E32B-E333: 00 08 10 00 08 00 00 00 08
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; ObjectYOffsetTable
|
|
|
|
; Seventy-three Y offsets parallel to ObjectTileTable.
|
|
; Range: $E334-$E37C (73 bytes)
|
|
; ---------------------------------------------------------------------------
|
|
ObjectYOffsetTable:
|
|
.byte $03,$01,$00,$08,$10,$00,$08,$00,$00,$00,$08,$00,$08,$10,$00,$08 ; E334-E343: 03 01 00 08 10 00 08 00 00 00 08 00 08 10 00 08
|
|
.byte $00,$00,$00,$08,$00,$08,$01,$00,$00,$02,$00,$03,$01,$00,$01,$00 ; E344-E353: 00 00 00 08 00 08 01 00 00 02 00 03 01 00 01 00
|
|
.byte $00,$08,$10,$00,$08,$00,$08,$00,$08,$00,$08,$00,$02,$04,$00,$01 ; E354-E363: 00 08 10 00 08 00 08 00 08 00 08 00 02 04 00 01
|
|
.byte $02,$00,$01,$01,$00,$08,$08,$10,$00,$02,$00,$08,$00,$08,$00,$08 ; E364-E373: 02 00 01 01 00 08 08 10 00 02 00 08 00 08 00 08
|
|
.byte $00,$02,$03,$00,$00,$00,$08,$00,$00 ; E374-E37C: 00 02 03 00 00 00 08 00 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; FixedObjectSpanBounds
|
|
|
|
; Prefix boundaries for fixed setup sprite groups.
|
|
; Range: $E37D-$E383 (7 bytes)
|
|
; ---------------------------------------------------------------------------
|
|
FixedObjectSpanBounds:
|
|
.byte $00,$03,$06,$0B,$10,$17,$1E ; E37D-E383: 00 03 06 0B 10 17 1E
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; FixedObjectXOffsets
|
|
|
|
; Thirty X offsets for fixed setup objects.
|
|
; Range: $E384-$E3A1 (30 bytes)
|
|
; ---------------------------------------------------------------------------
|
|
FixedObjectXOffsets:
|
|
.byte $00,$08,$04,$00,$08,$04,$00,$00,$08,$08,$04,$00,$00,$08,$08,$04 ; E384-E393: 00 08 04 00 08 04 00 00 08 08 04 00 00 08 08 04
|
|
.byte $00,$00,$00,$08,$08,$08,$04,$00,$00,$00,$08,$08,$08,$04 ; E394-E3A1: 00 00 00 08 08 08 04 00 00 00 08 08 08 04
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; FixedObjectTileTable
|
|
|
|
; Thirty CHR tiles for fixed setup objects.
|
|
; Range: $E3A2-$E3BF (30 bytes)
|
|
; ---------------------------------------------------------------------------
|
|
FixedObjectTileTable:
|
|
.byte $FA,$F5,$F7,$FA,$F5,$F7,$F8,$F9,$FB,$FC,$F7,$F9,$F8,$FC,$FB,$F7 ; E3A2-E3B1: FA F5 F7 FA F5 F7 F8 F9 FB FC F7 F9 F8 FC FB F7
|
|
.byte $F8,$F6,$F9,$FB,$F6,$FC,$F7,$F9,$F6,$F8,$FC,$F6,$FB,$F7 ; E3B2-E3BF: F8 F6 F9 FB F6 FC F7 F9 F6 F8 FC F6 FB F7
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; FixedObjectAttributeTable
|
|
|
|
; Thirty OAM attributes for fixed setup objects.
|
|
; Range: $E3C0-$E3DD (30 bytes)
|
|
; ---------------------------------------------------------------------------
|
|
FixedObjectAttributeTable:
|
|
.byte $02,$02,$02,$42,$42,$42,$02,$02,$02,$02,$02,$42,$42,$42,$42,$42 ; E3C0-E3CF: 02 02 02 42 42 42 02 02 02 02 02 42 42 42 42 42
|
|
.byte $02,$02,$02,$02,$82,$02,$02,$42,$42,$42,$42,$C2,$42,$42 ; E3D0-E3DD: 02 02 02 02 82 02 02 42 42 42 42 C2 42 42
|
|
.incbin "prg.bin", $23DE, $001E ; E3DE-E3FB: following unaudited table
|
|
; ---------------------------------------------------------------------------
|
|
; SubCE3FC
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E3FC.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCE3FC:
|
|
LDA #$01 ; E3FC: A9 01
|
|
STA $7F ; E3FE: 85 7F
|
|
STA $80 ; E400: 85 80
|
|
LDA #$B1 ; E402: A9 B1
|
|
STA $04 ; E404: 85 04
|
|
LDA #$03 ; E406: A9 03
|
|
STA $05 ; E408: 85 05
|
|
LDX $2B ; E40A: A6 2B
|
|
LDA $E58B,X ; E40C: BD 8B E5
|
|
JSR SubCDA1E ; E40F: 20 1E DA
|
|
STA $19 ; E412: 85 19
|
|
LDA #$0E ; E414: A9 0E
|
|
SEC ; E416: 38
|
|
SBC $19 ; E417: E5 19
|
|
STA $86 ; E419: 85 86
|
|
LDA $E58B,X ; E41B: BD 8B E5
|
|
AND #$0F ; E41E: 29 0F
|
|
PHA ; E420: 48
|
|
CLC ; E421: 18
|
|
ADC #$D5 ; E422: 69 D5
|
|
STA $1A ; E424: 85 1A
|
|
PLA ; E426: 68
|
|
JSR MultiplyABy32 ; E427: 20 BB C8
|
|
STA $85 ; E42A: 85 85
|
|
LDA $E59D,X ; E42C: BD 9D E5
|
|
AND #$0F ; E42F: 29 0F
|
|
STA $1B ; E431: 85 1B
|
|
LDX #$00 ; E433: A2 00
|
|
STX $1C ; E435: 86 1C
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E437
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E437.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E437:
|
|
LDY #$00 ; E437: A0 00
|
|
LDA $19 ; E439: A5 19
|
|
CMP #$05 ; E43B: C9 05
|
|
BCS Label_E447 ; E43D: B0 08
|
|
INC $1C ; E43F: E6 1C
|
|
CMP #$04 ; E441: C9 04
|
|
BCC Label_E447 ; E443: 90 02
|
|
INC $1C ; E445: E6 1C
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E447
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E447.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E447:
|
|
LDA $1C ; E447: A5 1C
|
|
CMP $19 ; E449: C5 19
|
|
BCC Label_E458 ; E44B: 90 0B
|
|
LDA $1C ; E44D: A5 1C
|
|
SEC ; E44F: 38
|
|
SBC $19 ; E450: E5 19
|
|
STA $1C ; E452: 85 1C
|
|
LDA $1A ; E454: A5 1A
|
|
BNE Label_E45A ; E456: D0 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E458
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E458.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E458:
|
|
LDA #$84 ; E458: A9 84
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E45A
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E45A.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E45A:
|
|
STA ($04),Y ; E45A: 91 04
|
|
INC $1C ; E45C: E6 1C
|
|
INY ; E45E: C8
|
|
CPY #$0C ; E45F: C0 0C
|
|
BCC Label_E447 ; E461: 90 E4
|
|
LDA $04 ; E463: A5 04
|
|
CLC ; E465: 18
|
|
ADC #$10 ; E466: 69 10
|
|
STA $04 ; E468: 85 04
|
|
BCC Label_E46E ; E46A: 90 02
|
|
INC $05 ; E46C: E6 05
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E46E
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E46E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E46E:
|
|
INX ; E46E: E8
|
|
CPX #$0A ; E46F: E0 0A
|
|
BCC Label_E437 ; E471: 90 C4
|
|
LDA #$80 ; E473: A9 80
|
|
STA $04 ; E475: 85 04
|
|
LDA #$03 ; E477: A9 03
|
|
STA $05 ; E479: 85 05
|
|
LDY $1B ; E47B: A4 1B
|
|
LDA $E5AF,Y ; E47D: B9 AF E5
|
|
STA $06 ; E480: 85 06
|
|
LDA $E5B2,Y ; E482: B9 B2 E5
|
|
STA $07 ; E485: 85 07
|
|
LDA #$00 ; E487: A9 00
|
|
STA $1A ; E489: 85 1A
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCE48B
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E48B.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCE48B:
|
|
LDY #$00 ; E48B: A0 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCE48D
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E48D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCE48D:
|
|
STY $19 ; E48D: 84 19
|
|
CPY #$10 ; E48F: C0 10
|
|
BCC Label_E4A1 ; E491: 90 0E
|
|
LDA $04 ; E493: A5 04
|
|
CLC ; E495: 18
|
|
ADC #$10 ; E496: 69 10
|
|
STA $04 ; E498: 85 04
|
|
BCC SubCE48B ; E49A: 90 EF
|
|
INC $05 ; E49C: E6 05
|
|
JMP SubCE48B ; E49E: 4C 8B E4
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E4A1
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E4A1.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E4A1:
|
|
LDY $1A ; E4A1: A4 1A
|
|
INC $1A ; E4A3: E6 1A
|
|
LDA ($06),Y ; E4A5: B1 06
|
|
CMP #$40 ; E4A7: C9 40
|
|
BEQ Label_E4DF ; E4A9: F0 34
|
|
BCC Label_E4B5 ; E4AB: 90 08
|
|
LDY $19 ; E4AD: A4 19
|
|
STA ($04),Y ; E4AF: 91 04
|
|
INY ; E4B1: C8
|
|
JMP SubCE48D ; E4B2: 4C 8D E4
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E4B5
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E4B5.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E4B5:
|
|
JSR SubCDA1E ; E4B5: 20 1E DA
|
|
CMP #$03 ; E4B8: C9 03
|
|
BEQ Label_E4D4 ; E4BA: F0 18
|
|
TAX ; E4BC: AA
|
|
LDA $E588,X ; E4BD: BD 88 E5
|
|
STA $1B ; E4C0: 85 1B
|
|
LDA ($06),Y ; E4C2: B1 06
|
|
AND #$0F ; E4C4: 29 0F
|
|
TAX ; E4C6: AA
|
|
LDY $19 ; E4C7: A4 19
|
|
LDA $1B ; E4C9: A5 1B
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E4CB
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E4CB.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E4CB:
|
|
STA ($04),Y ; E4CB: 91 04
|
|
INY ; E4CD: C8
|
|
DEX ; E4CE: CA
|
|
BPL Label_E4CB ; E4CF: 10 FA
|
|
JMP SubCE48D ; E4D1: 4C 8D E4
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E4D4
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E4D4.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E4D4:
|
|
LDA ($06),Y ; E4D4: B1 06
|
|
AND #$0F ; E4D6: 29 0F
|
|
SEC ; E4D8: 38
|
|
ADC $19 ; E4D9: 65 19
|
|
TAY ; E4DB: A8
|
|
JMP SubCE48D ; E4DC: 4C 8D E4
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E4DF
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E4DF.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E4DF:
|
|
LDY $67 ; E4DF: A4 67
|
|
DEY ; E4E1: 88
|
|
STY $0298 ; E4E2: 8C 98 02
|
|
LDA #$FF ; E4E5: A9 FF
|
|
STA $0299 ; E4E7: 8D 99 02
|
|
LDA #$01 ; E4EA: A9 01
|
|
STA $029A ; E4EC: 8D 9A 02
|
|
LDX $68 ; E4EF: A6 68
|
|
DEX ; E4F1: CA
|
|
DEX ; E4F2: CA
|
|
STX $029B ; E4F3: 8E 9B 02
|
|
LDA $0D ; E4F6: A5 0D
|
|
BEQ Label_E52C ; E4F8: F0 32
|
|
LDA $7B ; E4FA: A5 7B
|
|
CMP #$03 ; E4FC: C9 03
|
|
BEQ Label_E52C ; E4FE: F0 2C
|
|
LDA $7C ; E500: A5 7C
|
|
CMP #$03 ; E502: C9 03
|
|
BEQ Label_E52C ; E504: F0 26
|
|
LDA $40 ; E506: A5 40
|
|
STA $0200 ; E508: 8D 00 02
|
|
LDA $3E ; E50B: A5 3E
|
|
STA $0203 ; E50D: 8D 03 02
|
|
LDA $41 ; E510: A5 41
|
|
STA $0204 ; E512: 8D 04 02
|
|
LDA $3F ; E515: A5 3F
|
|
STA $0207 ; E517: 8D 07 02
|
|
LDA #$DD ; E51A: A9 DD
|
|
STA $0201 ; E51C: 8D 01 02
|
|
LDA #$F3 ; E51F: A9 F3
|
|
STA $0205 ; E521: 8D 05 02
|
|
LDA #$01 ; E524: A9 01
|
|
STA $0202 ; E526: 8D 02 02
|
|
STA $0206 ; E529: 8D 06 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E52C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E52C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E52C:
|
|
JMP SubCDFB8 ; E52C: 4C B8 DF
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCE52F
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E52F.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCE52F:
|
|
LDY $57 ; E52F: A4 57
|
|
LDA $E6AA,Y ; E531: B9 AA E6
|
|
STA $5F ; E534: 85 5F
|
|
LDA $65 ; E536: A5 65
|
|
SEC ; E538: 38
|
|
SBC $3B ; E539: E5 3B
|
|
BMI Label_E54A ; E53B: 30 0D
|
|
STA $5E ; E53D: 85 5E
|
|
JSR SubCF906 ; E53F: 20 06 F9
|
|
LDA $67 ; E542: A5 67
|
|
SEC ; E544: 38
|
|
SBC $60 ; E545: E5 60
|
|
JMP SubCE559 ; E547: 4C 59 E5
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E54A
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E54A.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E54A:
|
|
LDA $3B ; E54A: A5 3B
|
|
SEC ; E54C: 38
|
|
SBC $65 ; E54D: E5 65
|
|
STA $5E ; E54F: 85 5E
|
|
JSR SubCF906 ; E551: 20 06 F9
|
|
LDA $67 ; E554: A5 67
|
|
CLC ; E556: 18
|
|
ADC $60 ; E557: 65 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCE559
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E559.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCE559:
|
|
STA $3B ; E559: 85 3B
|
|
LDY $57 ; E55B: A4 57
|
|
LDA $E6AD,Y ; E55D: B9 AD E6
|
|
STA $5F ; E560: 85 5F
|
|
LDA $66 ; E562: A5 66
|
|
SEC ; E564: 38
|
|
SBC $38 ; E565: E5 38
|
|
BMI Label_E576 ; E567: 30 0D
|
|
STA $5E ; E569: 85 5E
|
|
JSR SubCF906 ; E56B: 20 06 F9
|
|
LDA $68 ; E56E: A5 68
|
|
SEC ; E570: 38
|
|
SBC $60 ; E571: E5 60
|
|
JMP SubCE585 ; E573: 4C 85 E5
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_E576
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E576.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_E576:
|
|
LDA $38 ; E576: A5 38
|
|
SEC ; E578: 38
|
|
SBC $66 ; E579: E5 66
|
|
STA $5E ; E57B: 85 5E
|
|
JSR SubCF906 ; E57D: 20 06 F9
|
|
LDA $68 ; E580: A5 68
|
|
CLC ; E582: 18
|
|
ADC $60 ; E583: 65 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCE585
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E585.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCE585:
|
|
STA $38 ; E585: 85 38
|
|
RTS ; E587: 60
|
|
.incbin "prg.bin", $2588, $0128 ; E588-E6AF: unclassified/data
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCE6B0
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $E6B0.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCE6B0:
|
|
LDY $2B ; E6B0: A4 2B
|
|
LDA $E59D,Y ; E6B2: B9 9D E5
|
|
JSR SubCDA1E ; E6B5: 20 1E DA
|
|
TAY ; E6B8: A8
|
|
LDA #$81 ; E6B9: A9 81
|
|
STA $67 ; E6BB: 85 67
|
|
LDA $E6A7,Y ; E6BD: B9 A7 E6
|
|
STA $68 ; E6C0: 85 68
|
|
RTS ; E6C2: 60
|
|
|
|
; Primary course-stream pointer table (split lo/hi), 18 entries.
|
|
; Entry i = (CourseLayoutPointerHi[i] << 8) | CourseLayoutPointerLo[i],
|
|
; resolving to the stream start labels in course_streams.inc:
|
|
; 0 $E6E7 Stream01 1 $EAAF Stream02 2 $F2E8 Stream03 3 $F4BC Stream04
|
|
; 4 $E991 Stream05 5 $EEF3 Stream06 6 $F0C5 Stream07 7 $F7BC Stream08
|
|
; 8 $F6BA Stream09 9 $EFE3 Stream10 10 $EDEC Stream11 11 $ED09 Stream12
|
|
; 12 $E7BA Stream13 13 $E8CF Stream14 14 $F3D3 Stream15 15 $EBAC Stream16
|
|
; 16 $F5C7 Stream17 17 $F1EA Stream18
|
|
CourseLayoutPointerLo:
|
|
.byte $E7,$AF,$E8,$BC,$91,$F3,$C5,$BC,$BA,$E3,$EC,$09,$BA,$CF,$D3,$AC,$C7,$EA ; E6C3-E6D4
|
|
CourseLayoutPointerHi:
|
|
.byte $E6,$EA,$F2,$F4,$E9,$EE,$F0,$F7,$F6,$EF,$ED,$ED,$E7,$E8,$F3,$EB,$F5,$F1 ; E6D5-E6E6
|
|
.incbin "prg.bin", $26E7, $121F ; E6E7-F905: remaining course/stream data
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCF906
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $F906.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCF906:
|
|
LDA #$00 ; F906: A9 00
|
|
STA $60 ; F908: 85 60
|
|
STA $61 ; F90A: 85 61
|
|
STA $63 ; F90C: 85 63
|
|
LDA $5E ; F90E: A5 5E
|
|
STA $62 ; F910: 85 62
|
|
LDA $5F ; F912: A5 5F
|
|
STA $64 ; F914: 85 64
|
|
LDX #$08 ; F916: A2 08
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_F918
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $F918.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_F918:
|
|
LSR $64 ; F918: 46 64
|
|
BCC Label_F929 ; F91A: 90 0D
|
|
LDA $60 ; F91C: A5 60
|
|
CLC ; F91E: 18
|
|
ADC $62 ; F91F: 65 62
|
|
STA $60 ; F921: 85 60
|
|
LDA $61 ; F923: A5 61
|
|
ADC $63 ; F925: 65 63
|
|
STA $61 ; F927: 85 61
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_F929
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $F929.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_F929:
|
|
ASL $62 ; F929: 06 62
|
|
ROL $63 ; F92B: 26 63
|
|
DEX ; F92D: CA
|
|
BNE Label_F918 ; F92E: D0 E8
|
|
RTS ; F930: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCF931
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $F931.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCF931:
|
|
LDA $49 ; F931: A5 49
|
|
BNE Label_F93B ; F933: D0 06
|
|
LDA $65 ; F935: A5 65
|
|
LDX $66 ; F937: A6 66
|
|
BNE Label_F93F ; F939: D0 04
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_F93B
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $F93B.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_F93B:
|
|
LDA $67 ; F93B: A5 67
|
|
LDX $68 ; F93D: A6 68
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_F93F
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $F93F.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_F93F:
|
|
STA $58 ; F93F: 85 58
|
|
SEC ; F941: 38
|
|
SBC $3B ; F942: E5 3B
|
|
BCS Label_F94B ; F944: B0 05
|
|
LDA $3B ; F946: A5 3B
|
|
SEC ; F948: 38
|
|
SBC $58 ; F949: E5 58
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_F94B
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $F94B.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_F94B:
|
|
TAY ; F94B: A8
|
|
TXA ; F94C: 8A
|
|
SEC ; F94D: 38
|
|
SBC $38 ; F94E: E5 38
|
|
JSR SubCD9B1 ; F950: 20 B1 D9
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCF953
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $F953.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCF953:
|
|
STA $5F ; F953: 85 5F
|
|
STA $5E ; F955: 85 5E
|
|
STA $5A ; F957: 85 5A
|
|
JSR SubCF906 ; F959: 20 06 F9
|
|
LDA $60 ; F95C: A5 60
|
|
STA $58 ; F95E: 85 58
|
|
LDA $61 ; F960: A5 61
|
|
STA $59 ; F962: 85 59
|
|
STY $5F ; F964: 84 5F
|
|
STY $5E ; F966: 84 5E
|
|
STY $5B ; F968: 84 5B
|
|
JSR SubCF906 ; F96A: 20 06 F9
|
|
LDA $60 ; F96D: A5 60
|
|
CLC ; F96F: 18
|
|
ADC $58 ; F970: 65 58
|
|
STA $58 ; F972: 85 58
|
|
LDA $61 ; F974: A5 61
|
|
ADC $59 ; F976: 65 59
|
|
STA $59 ; F978: 85 59
|
|
LDA $5A ; F97A: A5 5A
|
|
CMP $5B ; F97C: C5 5B
|
|
BCS Label_F982 ; F97E: B0 02
|
|
LDA $5B ; F980: A5 5B
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_F982
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $F982.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_F982:
|
|
TAY ; F982: A8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCF983
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $F983.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCF983:
|
|
STY $5E ; F983: 84 5E
|
|
STY $5F ; F985: 84 5F
|
|
JSR SubCF906 ; F987: 20 06 F9
|
|
LDA $58 ; F98A: A5 58
|
|
SEC ; F98C: 38
|
|
SBC $60 ; F98D: E5 60
|
|
LDA $59 ; F98F: A5 59
|
|
SBC $61 ; F991: E5 61
|
|
BCC Label_F99B ; F993: 90 06
|
|
LDY $5E ; F995: A4 5E
|
|
INY ; F997: C8
|
|
JMP SubCF983 ; F998: 4C 83 F9
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_F99B
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $F99B.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_F99B:
|
|
DEC $5E ; F99B: C6 5E
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_F99D
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $F99D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_F99D:
|
|
RTS ; F99D: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCF99E
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $F99E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCF99E:
|
|
LDX #$03 ; F99E: A2 03
|
|
LDA #$55 ; F9A0: A9 55
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_F9A2
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $F9A2.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_F9A2:
|
|
STA $FC,X ; F9A2: 95 FC
|
|
DEX ; F9A4: CA
|
|
BPL Label_F9A2 ; F9A5: 10 FB
|
|
LDX #$0B ; F9A7: A2 0B
|
|
LDA #$FF ; F9A9: A9 FF
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_F9AB
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $F9AB.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_F9AB:
|
|
STA $F0,X ; F9AB: 95 F0
|
|
DEX ; F9AD: CA
|
|
BPL Label_F9AB ; F9AE: 10 FB
|
|
LDX #$2F ; F9B0: A2 2F
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_F9B2
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $F9B2.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_F9B2:
|
|
LDA #$9D ; F9B2: A9 9D
|
|
STA $90,X ; F9B4: 95 90
|
|
LDA #$84 ; F9B6: A9 84
|
|
STA $C0,X ; F9B8: 95 C0
|
|
DEX ; F9BA: CA
|
|
BPL Label_F9B2 ; F9BB: 10 F5
|
|
LDA $49 ; F9BD: A5 49
|
|
BNE Label_F99D ; F9BF: D0 DC
|
|
LDA $38 ; F9C1: A5 38
|
|
STA $6D ; F9C3: 85 6D
|
|
LDA $3B ; F9C5: A5 3B
|
|
STA $6E ; F9C7: 85 6E
|
|
LDA $44 ; F9C9: A5 44
|
|
JSR MultiplyBy32 ; F9CB: 20 BC C8
|
|
STA $71 ; F9CE: 85 71
|
|
LDA #$03 ; F9D0: A9 03
|
|
STA $70 ; F9D2: 85 70
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_F9D4
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $F9D4.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_F9D4:
|
|
LDA #$0B ; F9D4: A9 0B
|
|
STA $6F ; F9D6: 85 6F
|
|
LDY $70 ; F9D8: A4 70
|
|
LDA $FBCB,Y ; F9DA: B9 CB FB
|
|
STA $5E ; F9DD: 85 5E
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_F9DF
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $F9DF.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_F9DF:
|
|
LDX $6F ; F9DF: A6 6F
|
|
LDA $FBBF,X ; F9E1: BD BF FB
|
|
CLC ; F9E4: 18
|
|
ADC $71 ; F9E5: 65 71
|
|
PHA ; F9E7: 48
|
|
JSR SubCFC24 ; F9E8: 20 24 FC
|
|
ADC $6D ; F9EB: 65 6D
|
|
STA $38 ; F9ED: 85 38
|
|
PLA ; F9EF: 68
|
|
JSR SubCFC27 ; F9F0: 20 27 FC
|
|
ADC $6E ; F9F3: 65 6E
|
|
STA $3B ; F9F5: 85 3B
|
|
LDA $38 ; F9F7: A5 38
|
|
CMP #$80 ; F9F9: C9 80
|
|
BCC Label_FA18 ; F9FB: 90 1B
|
|
JSR SubCD65A ; F9FD: 20 5A D6
|
|
LDY #$00 ; FA00: A0 00
|
|
LDA $52 ; FA02: A5 52
|
|
BEQ Label_FA08 ; FA04: F0 02
|
|
LDY #$01 ; FA06: A0 01
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FA08
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FA08.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FA08:
|
|
LDA $53 ; FA08: A5 53
|
|
BEQ Label_FA0E ; FA0A: F0 02
|
|
LDY #$02 ; FA0C: A0 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FA0E
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FA0E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FA0E:
|
|
LDA $55 ; FA0E: A5 55
|
|
BEQ Label_FA14 ; FA10: F0 02
|
|
LDY #$03 ; FA12: A0 03
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FA14
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FA14.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FA14:
|
|
LDA $56 ; FA14: A5 56
|
|
BEQ Label_FA1A ; FA16: F0 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FA18
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FA18.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FA18:
|
|
LDY #$04 ; FA18: A0 04
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FA1A
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FA1A.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FA1A:
|
|
JSR GetGridObjectIndex ; FA1A: 20 6E FC
|
|
STY $90,X ; FA1D: 94 90
|
|
DEC $6F ; FA1F: C6 6F
|
|
BPL Label_F9DF ; FA21: 10 BC
|
|
DEC $70 ; FA23: C6 70
|
|
BPL Label_F9D4 ; FA25: 10 AD
|
|
LDA $6D ; FA27: A5 6D
|
|
STA $38 ; FA29: 85 38
|
|
LDA $6E ; FA2B: A5 6E
|
|
STA $3B ; FA2D: 85 3B
|
|
JSR SubCD65D ; FA2F: 20 5D D6
|
|
JSR SubCD65A ; FA32: 20 5A D6
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; NormalizeCourseGrid
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FA35.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
NormalizeCourseGrid:
|
|
LDA #$02 ; FA35: A9 02
|
|
STA $70 ; FA37: 85 70
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FA39
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FA39.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FA39:
|
|
LDA #$0B ; FA39: A9 0B
|
|
STA $6F ; FA3B: 85 6F
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FA3D
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FA3D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FA3D:
|
|
JSR GetGridObjectIndex ; FA3D: 20 6E FC
|
|
LDA $90,X ; FA40: B5 90
|
|
CMP #$03 ; FA42: C9 03
|
|
BNE Label_FA80 ; FA44: D0 3A
|
|
LDA $6F ; FA46: A5 6F
|
|
AND #$FE ; FA48: 29 FE
|
|
STA $19 ; FA4A: 85 19
|
|
LDA $70 ; FA4C: A5 70
|
|
LSR A ; FA4E: 4A
|
|
ORA $19 ; FA4F: 05 19
|
|
TAX ; FA51: AA
|
|
LDY $FC03,X ; FA52: BC 03 FC
|
|
CLC ; FA55: 18
|
|
ADC #$02 ; FA56: 69 02
|
|
AND #$03 ; FA58: 29 03
|
|
TAX ; FA5A: AA
|
|
LDA a:$00FC,Y ; FA5B: B9 FC 00
|
|
AND $FC0F,X ; FA5E: 3D 0F FC
|
|
ORA $FC13,X ; FA61: 1D 13 FC
|
|
STA a:$00FC,Y ; FA64: 99 FC 00
|
|
LDA $70 ; FA67: A5 70
|
|
AND #$FE ; FA69: 29 FE
|
|
TAY ; FA6B: A8
|
|
LDA $6F ; FA6C: A5 6F
|
|
AND #$FE ; FA6E: 29 FE
|
|
CLC ; FA70: 18
|
|
ADC $FBCF,Y ; FA71: 79 CF FB
|
|
TAX ; FA74: AA
|
|
JSR NormalizeStatePair ; FA75: 20 AE FB
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FA78
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FA78.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FA78:
|
|
TXA ; FA78: 8A
|
|
CLC ; FA79: 18
|
|
ADC #$0B ; FA7A: 69 0B
|
|
TAX ; FA7C: AA
|
|
JSR NormalizeStatePair ; FA7D: 20 AE FB
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FA80
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FA80.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FA80:
|
|
DEC $6F ; FA80: C6 6F
|
|
BPL Label_FA3D ; FA82: 10 B9
|
|
DEC $70 ; FA84: C6 70
|
|
BPL Label_FA39 ; FA86: 10 B1
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FA88
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FA88.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FA88:
|
|
LDA #$00 ; FA88: A9 00
|
|
STA $70 ; FA8A: 85 70
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCFA8C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FA8C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCFA8C:
|
|
LDA #$0B ; FA8C: A9 0B
|
|
STA $6F ; FA8E: 85 6F
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCFA90
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FA90.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCFA90:
|
|
LDA #$00 ; FA90: A9 00
|
|
STA $19 ; FA92: 85 19
|
|
JSR GetGridObjectIndex ; FA94: 20 6E FC
|
|
LDA $70 ; FA97: A5 70
|
|
SEC ; FA99: 38
|
|
BEQ Label_FAA1 ; FA9A: F0 05
|
|
LDA $84,X ; FA9C: B5 84
|
|
JSR CompareObjectState ; FA9E: 20 66 FC
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FAA1
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FAA1.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FAA1:
|
|
ROL $19 ; FAA1: 26 19
|
|
LDA $70 ; FAA3: A5 70
|
|
CMP #$03 ; FAA5: C9 03
|
|
CLC ; FAA7: 18
|
|
BEQ Label_FAAF ; FAA8: F0 05
|
|
LDA $9C,X ; FAAA: B5 9C
|
|
JSR CompareObjectState ; FAAC: 20 66 FC
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FAAF
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FAAF.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FAAF:
|
|
ROL $19 ; FAAF: 26 19
|
|
LDA $6F ; FAB1: A5 6F
|
|
CLC ; FAB3: 18
|
|
BEQ Label_FABB ; FAB4: F0 05
|
|
LDA animation_frame_index,X ; FAB6: B5 8F
|
|
JSR CompareObjectState ; FAB8: 20 66 FC
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FABB
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FABB.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FABB:
|
|
ROL $19 ; FABB: 26 19
|
|
LDA $6F ; FABD: A5 6F
|
|
CMP #$0B ; FABF: C9 0B
|
|
CLC ; FAC1: 18
|
|
BEQ Label_FACA ; FAC2: F0 06
|
|
LDA $91,X ; FAC4: B5 91
|
|
TAY ; FAC6: A8
|
|
JSR CompareObjectState ; FAC7: 20 66 FC
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FACA
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FACA.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FACA:
|
|
ROL $19 ; FACA: 26 19
|
|
LDA $19 ; FACC: A5 19
|
|
AND #$03 ; FACE: 29 03
|
|
CMP #$03 ; FAD0: C9 03
|
|
BNE Label_FAE2 ; FAD2: D0 0E
|
|
LDA $90,X ; FAD4: B5 90
|
|
BEQ Label_FAE2 ; FAD6: F0 0A
|
|
TYA ; FAD8: 98
|
|
CMP animation_frame_index,X ; FAD9: D5 8F
|
|
BNE Label_FAE2 ; FADB: D0 05
|
|
STA $90,X ; FADD: 95 90
|
|
JMP NormalizeCourseGrid ; FADF: 4C 35 FA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FAE2
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FAE2.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FAE2:
|
|
LDA $90,X ; FAE2: B5 90
|
|
BEQ SubCFB25 ; FAE4: F0 3F
|
|
CMP #$04 ; FAE6: C9 04
|
|
BNE Label_FAED ; FAE8: D0 03
|
|
JMP StoreSpecialGridCoordinate ; FAEA: 4C A4 FB
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FAED
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FAED.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FAED:
|
|
LDA $19 ; FAED: A5 19
|
|
AND #$06 ; FAEF: 29 06
|
|
CMP #$06 ; FAF1: C9 06
|
|
BNE Label_FAFF ; FAF3: D0 0A
|
|
LDA $90,X ; FAF5: B5 90
|
|
CMP $9B,X ; FAF7: D5 9B
|
|
BNE Label_FAFF ; FAF9: D0 04
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FAFB
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FAFB.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FAFB:
|
|
STA $9C,X ; FAFB: 95 9C
|
|
BEQ Label_FA88 ; FAFD: F0 89
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FAFF
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FAFF.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FAFF:
|
|
LDA $19 ; FAFF: A5 19
|
|
AND #$05 ; FB01: 29 05
|
|
CMP #$05 ; FB03: C9 05
|
|
BNE Label_FB0D ; FB05: D0 06
|
|
LDA $90,X ; FB07: B5 90
|
|
CMP $9D,X ; FB09: D5 9D
|
|
BEQ Label_FAFB ; FB0B: F0 EE
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FB0D
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FB0D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FB0D:
|
|
LDY $90,X ; FB0D: B4 90
|
|
DEY ; FB0F: 88
|
|
TYA ; FB10: 98
|
|
JSR MultiplyBy32 ; FB11: 20 BC C8
|
|
ADC $19 ; FB14: 65 19
|
|
TAY ; FB16: A8
|
|
LDA $FBD3,Y ; FB17: B9 D3 FB
|
|
CMP #$AE ; FB1A: C9 AE
|
|
BNE Label_FB27 ; FB1C: D0 09
|
|
LDY $70 ; FB1E: A4 70
|
|
BEQ Label_FB27 ; FB20: F0 05
|
|
LDA #$82 ; FB22: A9 82
|
|
; Overlapping instruction idiom:
|
|
; FB24: BIT $B8A9 (2C A9 B8)
|
|
; FB25: LDA #$B8 (A9 B8)
|
|
Label_FB24:
|
|
.byte $2C ; FB24: 2C BIT absolute opcode
|
|
SubCFB25:
|
|
.byte $A9,$B8 ; FB25-FB26: A9 B8 LDA #$B8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FB27
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FB27.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FB27:
|
|
STA $C0,X ; FB27: 95 C0
|
|
DEC $6F ; FB29: C6 6F
|
|
BMI Label_FB30 ; FB2B: 30 03
|
|
JMP SubCFA90 ; FB2D: 4C 90 FA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FB30
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FB30.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FB30:
|
|
INC $70 ; FB30: E6 70
|
|
LDA $70 ; FB32: A5 70
|
|
CMP #$04 ; FB34: C9 04
|
|
BCS Label_FB3B ; FB36: B0 03
|
|
JMP SubCFA8C ; FB38: 4C 8C FA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FB3B
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FB3B.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FB3B:
|
|
LDX #$0B ; FB3B: A2 0B
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FB3D
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FB3D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FB3D:
|
|
LDY $F0,X ; FB3D: B4 F0
|
|
INY ; FB3F: C8
|
|
LDA $90,X ; FB40: B5 90
|
|
CMP #$03 ; FB42: C9 03
|
|
BNE Label_FB48 ; FB44: D0 02
|
|
LDY #$00 ; FB46: A0 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FB48
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FB48.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FB48:
|
|
LDA $FC17,Y ; FB48: B9 17 FC
|
|
STA $9C,X ; FB4B: 95 9C
|
|
LDA $FC1B,Y ; FB4D: B9 1B FC
|
|
STA $A8,X ; FB50: 95 A8
|
|
LDA $FC1F,Y ; FB52: B9 1F FC
|
|
STA $B4,X ; FB55: 95 B4
|
|
DEX ; FB57: CA
|
|
BPL Label_FB3D ; FB58: 10 E3
|
|
LDA $87 ; FB5A: A5 87
|
|
BNE Label_FB84 ; FB5C: D0 26
|
|
LDA #$84 ; FB5E: A9 84
|
|
LDX #$0B ; FB60: A2 0B
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FB62
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FB62.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FB62:
|
|
STA $E4,X ; FB62: 95 E4
|
|
DEX ; FB64: CA
|
|
BPL Label_FB62 ; FB65: 10 FB
|
|
LDA #$DF ; FB67: A9 DF
|
|
STA $0289 ; FB69: 8D 89 02
|
|
STA $028D ; FB6C: 8D 8D 02
|
|
LDA #$00 ; FB6F: A9 00
|
|
STA $028A ; FB71: 8D 8A 02
|
|
STA $028E ; FB74: 8D 8E 02
|
|
LDA #$18 ; FB77: A9 18
|
|
STA $028B ; FB79: 8D 8B 02
|
|
LDA #$60 ; FB7C: A9 60
|
|
STA $028F ; FB7E: 8D 8F 02
|
|
LDA #$B5 ; FB81: A9 B5
|
|
; Overlapping instruction idiom:
|
|
; FB83: BIT $FFA9 (2C A9 FF)
|
|
; FB84: LDA #$FF (A9 FF)
|
|
Label_FB83:
|
|
.byte $2C ; FB83: 2C BIT absolute opcode
|
|
Label_FB84:
|
|
.byte $A9,$FF ; FB84-FB85: A9 FF LDA #$FF
|
|
STA $0288 ; FB86: 8D 88 02
|
|
STA $028C ; FB89: 8D 8C 02
|
|
STA $0290 ; FB8C: 8D 90 02
|
|
JSR SubCF931 ; FB8F: 20 31 F9
|
|
LDA $5E ; FB92: A5 5E
|
|
CMP #$0C ; FB94: C9 0C
|
|
BCS Label_FBA3 ; FB96: B0 0B
|
|
ASL A ; FB98: 0A
|
|
PHA ; FB99: 48
|
|
JSR SubCD9B9 ; FB9A: 20 B9 D9
|
|
PLA ; FB9D: 68
|
|
LDY #$D7 ; FB9E: A0 D7
|
|
JSR SubCC752 ; FBA0: 20 52 C7
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FBA3
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FBA3.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FBA3:
|
|
RTS ; FBA3: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; StoreSpecialGridCoordinate
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FBA4.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
StoreSpecialGridCoordinate:
|
|
LDY $6F ; FBA4: A4 6F
|
|
LDA $70 ; FBA6: A5 70
|
|
STA a:$00F0,Y ; FBA8: 99 F0 00
|
|
JMP SubCFB25 ; FBAB: 4C 25 FB
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; NormalizeStatePair
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FBAE.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
NormalizeStatePair:
|
|
JSR NormalizeStateEntry ; FBAE: 20 B2 FB
|
|
INX ; FBB1: E8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; NormalizeStateEntry
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FBB2.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
NormalizeStateEntry:
|
|
LDA $90,X ; FBB2: B5 90
|
|
BEQ Label_FBBE ; FBB4: F0 08
|
|
CMP #$03 ; FBB6: C9 03
|
|
BEQ Label_FBBE ; FBB8: F0 04
|
|
LDA #$00 ; FBBA: A9 00
|
|
STA $90,X ; FBBC: 95 90
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FBBE
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FBBE.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FBBE:
|
|
RTS ; FBBE: 60
|
|
.incbin "prg.bin", $3BBF, $0065 ; FBBF-FC23: unclassified/data
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCFC24
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FC24.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCFC24:
|
|
CLC ; FC24: 18
|
|
ADC #$40 ; FC25: 69 40
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCFC27
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FC27.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCFC27:
|
|
TAX ; FC27: AA
|
|
LDA $0600,X ; FC28: BD 00 06
|
|
STA $5F ; FC2B: 85 5F
|
|
LDA $0700,X ; FC2D: BD 00 07
|
|
STA $73 ; FC30: 85 73
|
|
BEQ Label_FC43 ; FC32: F0 0F
|
|
BPL Label_FC3F ; FC34: 10 09
|
|
LDA #$FF ; FC36: A9 FF
|
|
SEC ; FC38: 38
|
|
SBC $5F ; FC39: E5 5F
|
|
STA $5F ; FC3B: 85 5F
|
|
BCS Label_FC43 ; FC3D: B0 04
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FC3F
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FC3F.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FC3F:
|
|
DEC $73 ; FC3F: C6 73
|
|
DEC $5F ; FC41: C6 5F
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FC43
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FC43.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FC43:
|
|
LDA $5E ; FC43: A5 5E
|
|
EOR $73 ; FC45: 45 73
|
|
STA $73 ; FC47: 85 73
|
|
LDA $5E ; FC49: A5 5E
|
|
JSR SubCD9B1 ; FC4B: 20 B1 D9
|
|
STA $5E ; FC4E: 85 5E
|
|
JSR SubCF906 ; FC50: 20 06 F9
|
|
LDX $61 ; FC53: A6 61
|
|
LDA $60 ; FC55: A5 60
|
|
BPL Label_FC5A ; FC57: 10 01
|
|
INX ; FC59: E8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FC5A
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FC5A.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FC5A:
|
|
TXA ; FC5A: 8A
|
|
LDX $73 ; FC5B: A6 73
|
|
BPL Label_FC64 ; FC5D: 10 05
|
|
LDA #$00 ; FC5F: A9 00
|
|
SEC ; FC61: 38
|
|
SBC $61 ; FC62: E5 61
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FC64
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FC64.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FC64:
|
|
CLC ; FC64: 18
|
|
RTS ; FC65: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; CompareObjectState
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FC66.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
CompareObjectState:
|
|
CMP $90,X ; FC66: D5 90
|
|
BEQ Label_FC6C ; FC68: F0 02
|
|
SEC ; FC6A: 38
|
|
; Overlapping instruction idiom:
|
|
; FC6B: BIT $18 (24 18), retaining carry set
|
|
; FC6C: CLC (18), alternate equality entry
|
|
Label_FC6B:
|
|
.byte $24 ; FC6B: 24 BIT zero-page opcode
|
|
Label_FC6C:
|
|
.byte $18 ; FC6C: 18 CLC / BIT operand
|
|
RTS ; FC6D: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; GetGridObjectIndex
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FC6E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
GetGridObjectIndex:
|
|
LDX $70 ; FC6E: A6 70
|
|
LDA $FBCF,X ; FC70: BD CF FB
|
|
CLC ; FC73: 18
|
|
ADC $6F ; FC74: 65 6F
|
|
TAX ; FC76: AA
|
|
RTS ; FC77: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCFC78
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FC78.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCFC78:
|
|
LDA $77 ; FC78: A5 77
|
|
BNE Label_FC7D ; FC7A: D0 01
|
|
RTS ; FC7C: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FC7D
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FC7D.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FC7D:
|
|
LDY #$B8 ; FC7D: A0 B8
|
|
LDX #$C0 ; FC7F: A2 C0
|
|
JSR WaitForFramePreservingY ; FC81: 20 81 C8
|
|
JSR RestorePpuCtrlShadow ; FC84: 20 B5 C8
|
|
JSR UploadGeneratedCourseGrid ; FC87: 20 98 FC
|
|
LDY #$A0 ; FC8A: A0 A0
|
|
LDX #$C5 ; FC8C: A2 C5
|
|
JSR InstallNmiCallback ; FC8E: 20 88 C8
|
|
LDA #$00 ; FC91: A9 00
|
|
STA $2E ; FC93: 85 2E
|
|
JMP RestorePpuCtrlShadow ; FC95: 4C B5 C8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; UploadGeneratedCourseGrid
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FC98.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
UploadGeneratedCourseGrid:
|
|
JSR SubCF99E ; FC98: 20 9E F9
|
|
JSR WaitForFrame ; FC9B: 20 F3 C8
|
|
LDA #$22 ; FC9E: A9 22
|
|
STA $04 ; FCA0: 85 04
|
|
LDA #$22 ; FCA2: A9 22
|
|
STA $05 ; FCA4: 85 05
|
|
LDX #$00 ; FCA6: A2 00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FCA8
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FCA8.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FCA8:
|
|
JSR WaitForFrame ; FCA8: 20 F3 C8
|
|
LDA $04 ; FCAB: A5 04
|
|
STA PPUADDR ; FCAD: 8D 06 20
|
|
LDA $05 ; FCB0: A5 05
|
|
STA PPUADDR ; FCB2: 8D 06 20
|
|
LDY #$0B ; FCB5: A0 0B
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FCB7
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FCB7.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FCB7:
|
|
LDA $9C,X ; FCB7: B5 9C
|
|
STA PPUDATA ; FCB9: 8D 07 20
|
|
INX ; FCBC: E8
|
|
DEY ; FCBD: 88
|
|
BPL Label_FCB7 ; FCBE: 10 F7
|
|
JSR SetPpuScrollAndMask ; FCC0: 20 9D C8
|
|
LDA $05 ; FCC3: A5 05
|
|
CLC ; FCC5: 18
|
|
ADC #$20 ; FCC6: 69 20
|
|
STA $05 ; FCC8: 85 05
|
|
BCC Label_FCCE ; FCCA: 90 02
|
|
INC $04 ; FCCC: E6 04
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FCCE
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FCCE.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FCCE:
|
|
CPX #$54 ; FCCE: E0 54
|
|
BCC Label_FCA8 ; FCD0: 90 D6
|
|
LDX #$23 ; FCD2: A2 23
|
|
LDA #$E8 ; FCD4: A9 E8
|
|
JSR SetPpuAddress ; FCD6: 20 C1 C8
|
|
LDX #$03 ; FCD9: A2 03
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FCDB
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FCDB.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FCDB:
|
|
LDA $FC,X ; FCDB: B5 FC
|
|
STA PPUDATA ; FCDD: 8D 07 20
|
|
DEX ; FCE0: CA
|
|
BPL Label_FCDB ; FCE1: 10 F8
|
|
JMP SetPpuScrollAndMask ; FCE3: 4C 9D C8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCFCE6
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FCE6.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCFCE6:
|
|
JSR SubCCA9D ; FCE6: 20 9D CA
|
|
LDA #$FF ; FCE9: A9 FF
|
|
STA $0280 ; FCEB: 8D 80 02
|
|
JSR SubCC907 ; FCEE: 20 07 C9
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCFCF1
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FCF1.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCFCF1:
|
|
LDX #$3F ; FCF1: A2 3F
|
|
LDA #$10 ; FCF3: A9 10
|
|
JSR SetPpuAddress ; FCF5: 20 C1 C8
|
|
JSR SpriteOffsetForController ; FCF8: 20 94 C8
|
|
LDY #$03 ; FCFB: A0 03
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FCFD
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FCFD.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FCFD:
|
|
LDA $FD0A,X ; FCFD: BD 0A FD
|
|
STA PPUDATA ; FD00: 8D 07 20
|
|
INX ; FD03: E8
|
|
DEY ; FD04: 88
|
|
BPL Label_FCFD ; FD05: 10 F6
|
|
JMP SetPpuScrollAndMask ; FD07: 4C 9D C8
|
|
; PpuTableFd0a: bytes written to PPUDATA via indexed load
|
|
; (LDA $FD0A,X / STA PPUDATA at $FCFD; consumer reads 4 bytes).
|
|
PpuTableFd0a:
|
|
.byte $29,$01,$30,$27,$29,$0f,$16,$27 ; FD0A-FD11: 29 01 30 27 29 0f 16 27
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCFD12
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FD12.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCFD12:
|
|
LDX $38 ; FD12: A6 38
|
|
LDA $3B ; FD14: A5 3B
|
|
JSR SubCD8ED ; FD16: 20 ED D8
|
|
CLC ; FD19: 18
|
|
ADC #$80 ; FD1A: 69 80
|
|
STA $71 ; FD1C: 85 71
|
|
LDA #$80 ; FD1E: A9 80
|
|
STA $6B ; FD20: 85 6B
|
|
STA $6C ; FD22: 85 6C
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FD24
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FD24.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FD24:
|
|
LDA $71 ; FD24: A5 71
|
|
CLC ; FD26: 18
|
|
ADC #$40 ; FD27: 69 40
|
|
TAX ; FD29: AA
|
|
LDA $0600,X ; FD2A: BD 00 06
|
|
CLC ; FD2D: 18
|
|
ADC $6B ; FD2E: 65 6B
|
|
STA $6B ; FD30: 85 6B
|
|
LDA $0700,X ; FD32: BD 00 07
|
|
ADC $38 ; FD35: 65 38
|
|
STA $38 ; FD37: 85 38
|
|
LDX $71 ; FD39: A6 71
|
|
LDA $0600,X ; FD3B: BD 00 06
|
|
CLC ; FD3E: 18
|
|
ADC $6C ; FD3F: 65 6C
|
|
STA $6C ; FD41: 85 6C
|
|
LDA $0700,X ; FD43: BD 00 07
|
|
ADC $3B ; FD46: 65 3B
|
|
STA $3B ; FD48: 85 3B
|
|
LDA $38 ; FD4A: A5 38
|
|
BPL Label_FD5E ; FD4C: 10 10
|
|
LDA $3B ; FD4E: A5 3B
|
|
CMP #$F0 ; FD50: C9 F0
|
|
BCS Label_FD5E ; FD52: B0 0A
|
|
JSR SubCD65A ; FD54: 20 5A D6
|
|
LDA $55 ; FD57: A5 55
|
|
ORA $56 ; FD59: 05 56
|
|
BNE Label_FD24 ; FD5B: D0 C7
|
|
RTS ; FD5D: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FD5E
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FD5E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FD5E:
|
|
LDA $79 ; FD5E: A5 79
|
|
STA $38 ; FD60: 85 38
|
|
LDA $78 ; FD62: A5 78
|
|
STA $3B ; FD64: 85 3B
|
|
RTS ; FD66: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCFD67
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FD67.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCFD67:
|
|
LDY #$02 ; FD67: A0 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FD69
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FD69.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FD69:
|
|
LDX #$00 ; FD69: A2 00
|
|
LDA $90 ; FD6B: A5 90
|
|
BPL Label_FD70 ; FD6D: 10 01
|
|
DEX ; FD6F: CA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FD70
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FD70.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FD70:
|
|
CLC ; FD70: 18
|
|
ADC $39 ; FD71: 65 39
|
|
STA $39 ; FD73: 85 39
|
|
TXA ; FD75: 8A
|
|
ADC $38 ; FD76: 65 38
|
|
STA $38 ; FD78: 85 38
|
|
LDX #$00 ; FD7A: A2 00
|
|
LDA $91 ; FD7C: A5 91
|
|
BPL Label_FD81 ; FD7E: 10 01
|
|
DEX ; FD80: CA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FD81
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FD81.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FD81:
|
|
CLC ; FD81: 18
|
|
ADC $3C ; FD82: 65 3C
|
|
STA $3C ; FD84: 85 3C
|
|
TXA ; FD86: 8A
|
|
ADC $3B ; FD87: 65 3B
|
|
STA $3B ; FD89: 85 3B
|
|
DEY ; FD8B: 88
|
|
BPL Label_FD69 ; FD8C: 10 DB
|
|
LDA #$12 ; FD8E: A9 12
|
|
STA $5E ; FD90: 85 5E
|
|
LDA $94 ; FD92: A5 94
|
|
CLC ; FD94: 18
|
|
ADC #$80 ; FD95: 69 80
|
|
PHA ; FD97: 48
|
|
JSR SubCFE50 ; FD98: 20 50 FE
|
|
PLA ; FD9B: 68
|
|
JSR SubCFE61 ; FD9C: 20 61 FE
|
|
LDA $86 ; FD9F: A5 86
|
|
STA $5E ; FDA1: 85 5E
|
|
LDA $85 ; FDA3: A5 85
|
|
JSR SubCFE50 ; FDA5: 20 50 FE
|
|
LDA $85 ; FDA8: A5 85
|
|
JSR SubCFE61 ; FDAA: 20 61 FE
|
|
LDA $90 ; FDAD: A5 90
|
|
STA $6B ; FDAF: 85 6B
|
|
JSR SubCD9B1 ; FDB1: 20 B1 D9
|
|
TAY ; FDB4: A8
|
|
LDA $91 ; FDB5: A5 91
|
|
STA $6C ; FDB7: 85 6C
|
|
JSR SubCD9B1 ; FDB9: 20 B1 D9
|
|
JSR SubCF953 ; FDBC: 20 53 F9
|
|
LDA $5E ; FDBF: A5 5E
|
|
STA $95 ; FDC1: 85 95
|
|
JSR SubCD906 ; FDC3: 20 06 D9
|
|
STA $94 ; FDC6: 85 94
|
|
LDA $38 ; FDC8: A5 38
|
|
SEC ; FDCA: 38
|
|
SBC $79 ; FDCB: E5 79
|
|
JSR SubCD9B1 ; FDCD: 20 B1 D9
|
|
TAY ; FDD0: A8
|
|
LDA $3B ; FDD1: A5 3B
|
|
SEC ; FDD3: 38
|
|
SBC $78 ; FDD4: E5 78
|
|
JSR SubCD9B1 ; FDD6: 20 B1 D9
|
|
JSR SubCF953 ; FDD9: 20 53 F9
|
|
LDA #$B6 ; FDDC: A9 B6
|
|
SEC ; FDDE: 38
|
|
SBC $5E ; FDDF: E5 5E
|
|
CMP #$98 ; FDE1: C9 98
|
|
BCS Label_FDE7 ; FDE3: B0 02
|
|
LDA #$FF ; FDE5: A9 FF
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FDE7
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FDE7.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FDE7:
|
|
CMP #$9C ; FDE7: C9 9C
|
|
BCS Label_FDED ; FDE9: B0 02
|
|
LDA #$9C ; FDEB: A9 9C
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FDED
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FDED.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FDED:
|
|
STA $0280 ; FDED: 8D 80 02
|
|
LDX #$88 ; FDF0: A2 88
|
|
CMP #$AC ; FDF2: C9 AC
|
|
BCS Label_FDF7 ; FDF4: B0 01
|
|
INX ; FDF6: E8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FDF7
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FDF7.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FDF7:
|
|
STX $0281 ; FDF7: 8E 81 02
|
|
LDA #$4C ; FDFA: A9 4C
|
|
LDX $5E ; FDFC: A6 5E
|
|
CPX #$03 ; FDFE: E0 03
|
|
BCC Label_FE35 ; FE00: 90 33
|
|
LDA $39 ; FE02: A5 39
|
|
STA $19 ; FE04: 85 19
|
|
LDA $38 ; FE06: A5 38
|
|
SEC ; FE08: 38
|
|
SBC $79 ; FE09: E5 79
|
|
STA $6B ; FE0B: 85 6B
|
|
ASL $19 ; FE0D: 06 19
|
|
ROL $6B ; FE0F: 26 6B
|
|
ASL $19 ; FE11: 06 19
|
|
ROL $6B ; FE13: 26 6B
|
|
LDA $3C ; FE15: A5 3C
|
|
STA $19 ; FE17: 85 19
|
|
LDA $3B ; FE19: A5 3B
|
|
SEC ; FE1B: 38
|
|
SBC $78 ; FE1C: E5 78
|
|
STA $6C ; FE1E: 85 6C
|
|
ASL $19 ; FE20: 06 19
|
|
ROL $6C ; FE22: 26 6C
|
|
ASL $19 ; FE24: 06 19
|
|
ROL $6C ; FE26: 26 6C
|
|
JSR SubCD9D9 ; FE28: 20 D9 D9
|
|
LDA $74 ; FE2B: A5 74
|
|
SEC ; FE2D: 38
|
|
SBC #$02 ; FE2E: E9 02
|
|
CLC ; FE30: 18
|
|
ADC $0283 ; FE31: 6D 83 02
|
|
LSR A ; FE34: 4A
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FE35
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FE35.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FE35:
|
|
STA $0283 ; FE35: 8D 83 02
|
|
LDA #$00 ; FE38: A9 00
|
|
STA $0282 ; FE3A: 8D 82 02
|
|
RTS ; FE3D: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCFE3E
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FE3E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCFE3E:
|
|
LDX #$00 ; FE3E: A2 00
|
|
TAY ; FE40: A8
|
|
BPL Label_FE44 ; FE41: 10 01
|
|
DEX ; FE43: CA
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FE44
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FE44.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FE44:
|
|
STX $1A ; FE44: 86 1A
|
|
LDX #$04 ; FE46: A2 04
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FE48
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FE48.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FE48:
|
|
ASL A ; FE48: 0A
|
|
ROL $1A ; FE49: 26 1A
|
|
DEX ; FE4B: CA
|
|
BNE Label_FE48 ; FE4C: D0 FA
|
|
CLC ; FE4E: 18
|
|
RTS ; FE4F: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCFE50
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FE50.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCFE50:
|
|
JSR SubCFC24 ; FE50: 20 24 FC
|
|
JSR SubCFE3E ; FE53: 20 3E FE
|
|
ADC $92 ; FE56: 65 92
|
|
STA $92 ; FE58: 85 92
|
|
LDA $1A ; FE5A: A5 1A
|
|
ADC $90 ; FE5C: 65 90
|
|
STA $90 ; FE5E: 85 90
|
|
RTS ; FE60: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCFE61
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FE61.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCFE61:
|
|
JSR SubCFC27 ; FE61: 20 27 FC
|
|
JSR SubCFE3E ; FE64: 20 3E FE
|
|
ADC $93 ; FE67: 65 93
|
|
STA $93 ; FE69: 85 93
|
|
LDA $1A ; FE6B: A5 1A
|
|
ADC $91 ; FE6D: 65 91
|
|
STA $91 ; FE6F: 85 91
|
|
RTS ; FE71: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCFE72
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FE72.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCFE72:
|
|
LDA #$FF ; FE72: A9 FF
|
|
STA $0210 ; FE74: 8D 10 02
|
|
JSR WaitForFrame ; FE77: 20 F3 C8
|
|
LDA $1A ; FE7A: A5 1A
|
|
CMP #$0F ; FE7C: C9 0F
|
|
BEQ Label_FE8E ; FE7E: F0 0E
|
|
CMP #$0D ; FE80: C9 0D
|
|
BCC Label_FE8E ; FE82: 90 0A
|
|
LDX #$21 ; FE84: A2 21
|
|
LDA #$24 ; FE86: A9 24
|
|
JSR SubCFEB5 ; FE88: 20 B5 FE
|
|
JMP SubCFE97 ; FE8B: 4C 97 FE
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FE8E
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FE8E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FE8E:
|
|
LDX #$20 ; FE8E: A2 20
|
|
LDA #$87 ; FE90: A9 87
|
|
LDY #$9D ; FE92: A0 9D
|
|
JSR SubCC586 ; FE94: 20 86 C5
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCFE97
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FE97.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCFE97:
|
|
LDA $1A ; FE97: A5 1A
|
|
CMP #$0F ; FE99: C9 0F
|
|
BEQ Label_FEAB ; FE9B: F0 0E
|
|
CMP #$0D ; FE9D: C9 0D
|
|
BCC Label_FEAB ; FE9F: 90 0A
|
|
LDX #$21 ; FEA1: A2 21
|
|
LDA #$64 ; FEA3: A9 64
|
|
JSR SubCFEB5 ; FEA5: 20 B5 FE
|
|
JMP SubCFEB2 ; FEA8: 4C B2 FE
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FEAB
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FEAB.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FEAB:
|
|
LDX #$20 ; FEAB: A2 20
|
|
LDA #$A7 ; FEAD: A9 A7
|
|
JSR SubCC586 ; FEAF: 20 86 C5
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCFEB2
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FEB2.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCFEB2:
|
|
JMP SetPpuScrollAndMask ; FEB2: 4C 9D C8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCFEB5
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FEB5.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCFEB5:
|
|
JSR SetPpuAddress ; FEB5: 20 C1 C8
|
|
LDA #$9D ; FEB8: A9 9D
|
|
LDY #$0A ; FEBA: A0 0A
|
|
JMP SubCC599 ; FEBC: 4C 99 C5
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCFEBF
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FEBF.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCFEBF:
|
|
STA $1A ; FEBF: 85 1A
|
|
LDY #$14 ; FEC1: A0 14
|
|
JSR SubCC8F5 ; FEC3: 20 F5 C8
|
|
JSR SubCFE72 ; FEC6: 20 72 FE
|
|
LDX #$02 ; FEC9: A2 02
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FECB
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FECB.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FECB:
|
|
STX $19 ; FECB: 86 19
|
|
JSR SubCFF2B ; FECD: 20 2B FF
|
|
LDA $1A ; FED0: A5 1A
|
|
CMP #$02 ; FED2: C9 02
|
|
BCS Label_FEDA ; FED4: B0 04
|
|
LDA #$F0 ; FED6: A9 F0
|
|
BNE Label_FF03 ; FED8: D0 29
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FEDA
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FEDA.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FEDA:
|
|
CMP #$06 ; FEDA: C9 06
|
|
BCS Label_FEE2 ; FEDC: B0 04
|
|
LDA #$20 ; FEDE: A9 20
|
|
BNE Label_FF03 ; FEE0: D0 21
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FEE2
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FEE2.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FEE2:
|
|
CMP #$08 ; FEE2: C9 08
|
|
BCS Label_FEEA ; FEE4: B0 04
|
|
LDA #$38 ; FEE6: A9 38
|
|
BNE Label_FF03 ; FEE8: D0 19
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FEEA
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FEEA.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FEEA:
|
|
CMP #$0B ; FEEA: C9 0B
|
|
BCS Label_FEF2 ; FEEC: B0 04
|
|
LDA #$D0 ; FEEE: A9 D0
|
|
BNE Label_FF03 ; FEF0: D0 11
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FEF2
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FEF2.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FEF2:
|
|
CMP #$0B ; FEF2: C9 0B
|
|
BNE Label_FEFA ; FEF4: D0 04
|
|
LDA #$A0 ; FEF6: A9 A0
|
|
BNE Label_FF03 ; FEF8: D0 09
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FEFA
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FEFA.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FEFA:
|
|
CMP #$0C ; FEFA: C9 0C
|
|
BEQ Label_FF01 ; FEFC: F0 03
|
|
LDA #$50 ; FEFE: A9 50
|
|
; Overlapping instruction idiom:
|
|
; FF00: BIT $00A9 (2C A9 00)
|
|
; FF01: LDA #$00 (A9 00)
|
|
Label_FF00:
|
|
.byte $2C ; FF00: 2C BIT absolute opcode
|
|
Label_FF01:
|
|
.byte $A9,$00 ; FF01-FF02: A9 00 LDA #$00
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FF03
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FF03.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FF03:
|
|
ASL A ; FF03: 0A
|
|
STA APUTRIANGLETIMERLO ; FF04: 8D 0A 40
|
|
LDA #$FF ; FF07: A9 FF
|
|
STA APUTRIANGLECTRL ; FF09: 8D 08 40
|
|
LDA #$00 ; FF0C: A9 00
|
|
ADC #$00 ; FF0E: 69 00
|
|
STA APUTRIANGLETIMERHI ; FF10: 8D 0B 40
|
|
LDY #$16 ; FF13: A0 16
|
|
JSR SubCC8F5 ; FF15: 20 F5 C8
|
|
JSR SubCFE72 ; FF18: 20 72 FE
|
|
LDA #$00 ; FF1B: A9 00
|
|
STA APUTRIANGLECTRL ; FF1D: 8D 08 40
|
|
LDY #$0F ; FF20: A0 0F
|
|
JSR SubCC8F5 ; FF22: 20 F5 C8
|
|
LDX $19 ; FF25: A6 19
|
|
DEX ; FF27: CA
|
|
BPL Label_FECB ; FF28: 10 A1
|
|
RTS ; FF2A: 60
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; SubCFF2B
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FF2B.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
SubCFF2B:
|
|
JSR WaitForFrame ; FF2B: 20 F3 C8
|
|
LDA $1A ; FF2E: A5 1A
|
|
CMP #$0F ; FF30: C9 0F
|
|
BEQ Label_FF3E ; FF32: F0 0A
|
|
CMP #$0D ; FF34: C9 0D
|
|
BCC Label_FF3E ; FF36: 90 06
|
|
LDX #$21 ; FF38: A2 21
|
|
LDA #$26 ; FF3A: A9 26
|
|
BNE Label_FF42 ; FF3C: D0 04
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FF3E
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FF3E.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FF3E:
|
|
LDX #$20 ; FF3E: A2 20
|
|
LDA #$88 ; FF40: A9 88
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FF42
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FF42.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FF42:
|
|
JSR SetPpuAddress ; FF42: 20 C1 C8
|
|
LDX $1A ; FF45: A6 1A
|
|
LDY $FF85,X ; FF47: BC 85 FF
|
|
LDX #$05 ; FF4A: A2 05
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FF4C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FF4C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FF4C:
|
|
LDA $FFA5,Y ; FF4C: B9 A5 FF
|
|
BEQ Label_FF58 ; FF4F: F0 07
|
|
STA PPUDATA ; FF51: 8D 07 20
|
|
INY ; FF54: C8
|
|
DEX ; FF55: CA
|
|
BPL Label_FF4C ; FF56: 10 F4
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FF58
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FF58.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FF58:
|
|
LDA $1A ; FF58: A5 1A
|
|
CMP #$0F ; FF5A: C9 0F
|
|
BEQ Label_FF68 ; FF5C: F0 0A
|
|
CMP #$0D ; FF5E: C9 0D
|
|
BCC Label_FF68 ; FF60: 90 06
|
|
LDX #$21 ; FF62: A2 21
|
|
LDA #$66 ; FF64: A9 66
|
|
BNE Label_FF6C ; FF66: D0 04
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FF68
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FF68.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FF68:
|
|
LDX #$20 ; FF68: A2 20
|
|
LDA #$A8 ; FF6A: A9 A8
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FF6C
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FF6C.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FF6C:
|
|
JSR SetPpuAddress ; FF6C: 20 C1 C8
|
|
LDX $1A ; FF6F: A6 1A
|
|
LDY $FF95,X ; FF71: BC 95 FF
|
|
LDX #$05 ; FF74: A2 05
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FF76
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FF76.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FF76:
|
|
LDA $FFA5,Y ; FF76: B9 A5 FF
|
|
BEQ Label_FF82 ; FF79: F0 07
|
|
STA PPUDATA ; FF7B: 8D 07 20
|
|
INY ; FF7E: C8
|
|
DEX ; FF7F: CA
|
|
BPL Label_FF76 ; FF80: 10 F4
|
|
|
|
; ---------------------------------------------------------------------------
|
|
; Label_FF82
|
|
|
|
; Global:
|
|
; Pass 1 reachable entry at $FF82.
|
|
; Local:
|
|
; Behavior is conservatively represented by the decoded instructions below;
|
|
; semantic naming will be refined in Pass 2 and Pass 3.
|
|
; Parameters:
|
|
; Entry register and RAM requirements are not yet fully determined.
|
|
; Returns:
|
|
; Determined by the terminating control-flow instruction.
|
|
; Clobbers:
|
|
; A, X, Y, and processor flags as used by the instructions below.
|
|
; ---------------------------------------------------------------------------
|
|
Label_FF82:
|
|
JMP SetPpuScrollAndMask ; FF82: 4C 9D C8
|
|
; FF85PpuValueTable: 117-byte table accessed two ways:
|
|
; LDY $FF85,X -> entry at offset X (used at $FF47)
|
|
; LDY $FF95,X -> entry at offset X+16 (used at $FF71, overlaps the same region)
|
|
; Index comes from $1A. Both routines set PPU address then write 6 bytes.
|
|
FF85PpuValueTable:
|
|
.byte $00,$06,$0c,$12,$18,$00,$12,$18,$1e,$24,$30,$46,$36,$47,$46,$4d ; FF85-FF94
|
|
.byte $06,$46,$46,$46,$46,$18,$42,$42,$46,$2a,$46,$46,$3c,$46,$47,$46 ; FF95-FFA4
|
|
.byte $0d,$18,$1e,$0b,$15,$0e,$0b,$18,$10,$0e,$22,$9d,$9d,$19,$0a,$1b ; FFA5-FFB4
|
|
.byte $9d,$9d,$0b,$12,$1b,$0d,$12,$0e,$0e,$0a,$10,$15,$0e,$9d,$9d,$9d ; FFB5-FFC4
|
|
.byte $18,$0b,$9d,$9d,$20,$0a,$1d,$0e,$1b,$9d,$11,$0a,$23,$0a,$1b,$0d ; FFC5-FFD4
|
|
.byte $0b,$1e,$17,$14,$0e,$1b,$9d,$11,$18,$15,$0e,$9d,$9d,$18,$1e,$1d ; FFD5-FFE4
|
|
.byte $9d,$9d,$9d,$1d,$1b,$22,$00,$20,$12,$17,$17,$0e,$1b,$9d,$20,$12 ; FFE5-FFF4
|
|
.byte $17,$0d,$9d,$ff,$ff ; FFF5-FFF9
|
|
.word NmiHandler ; FFFA-FFFB: A6 C0 NMI vector -> $C0A6
|
|
.word Reset ; FFFC-FFFD: 00 C0 RESET vector -> $C000
|
|
.word IrqLoop ; FFFE-FFFF: C4 C0 IRQ vector -> $C0C4
|