use log::debug;
use crate::computers::rom_only::RomOnlyComputer;
use crate::traits::backplane::Backplane;

impl Backplane for RomOnlyComputer {
    fn data_bus(&self) -> u8 { self.data_bus }
    fn address_bus(&self) -> u16 { self.address_bus }
    fn read_mode(&self) -> bool { self.read_mode }
    fn set_read_mode(&mut self, new_mode: bool) {
        self.read_mode = new_mode
    }
    fn set_data_bus(&mut self, new_value: u8) {
        self.data_bus = new_value
    }
    fn set_address_bus(&mut self, new_value: u16) {
        self.address_bus = new_value
    }

    fn tick(&mut self) {
//        println!("COMPUTER: Preparing to tick.");
        // do are we being addressed?
//        println!("COMPUTER: BUSSES PRE: 0x{:04x} 0x{:02x} {}", self.address_bus, self.data_bus, self.read_mode);
        let  new_data = self.rom.signal_tick(self.address_bus, self.data_bus, true, true, true);
            // tick(self.address_bus, self.data_bus, self.read_mode);
        self.set_address_bus(self.address_bus);
        self.set_data_bus(new_data);
//        println!("COMPUTER: BUSSES POST: 0x{:04x} 0x{:02x} {}", self.address_bus, self.data_bus, self.read_mode);
//        println!("COMPUTER: Done ticking.");
    }

    fn tick_ram(&mut self, address: u16, data: u8, cs: bool, oe: bool, we: bool) -> u8 {
        debug!("This system has no ram.  ROM only.");
        0x00
    }

    fn tick_rom(&mut self, address: u16, cs: bool, oe: bool) -> u8 {
        let data = self.rom.signal_tick(address, self.data_bus, cs, oe, true);
             data
    }

    fn tick_via(&mut self, address: u16, data: u8, cs0: bool, cs1: bool, rw: bool, rs0: bool, rs1: bool) -> (u8, bool, bool) {
            debug!("This system has no VIA controllers.  ROM only");
            (0,false,false)
    }
}
