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BUGFIX: Decoder now decodes instructions without parameters

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This commit is contained in:
Trevor Merritt 2025-06-29 10:43:41 -04:00
parent e5c2319803
commit 0c475127f6
9 changed files with 101 additions and 38 deletions
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5
.bad/.gitignore vendored Normal file
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@ -0,0 +1,5 @@
# Default ignored files
/shelf/
/workspace.xml
# Editor-based HTTP Client requests
/httpRequests/

8
.bad/modules.xml Normal file
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@ -0,0 +1,8 @@
<?xml version="1.0" encoding="UTF-8"?>
<project version="4">
<component name="ProjectModuleManager">
<modules>
<module fileurl="file://$PROJECT_DIR$/.idea/mos6502.iml" filepath="$PROJECT_DIR$/.idea/mos6502.iml" />
</modules>
</component>
</project>

13
.bad/mos6502.iml Normal file
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@ -0,0 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<module type="EMPTY_MODULE" version="4">
<component name="NewModuleRootManager">
<content url="file://$MODULE_DIR$">
<sourceFolder url="file://$MODULE_DIR$/cli/src" isTestSource="false" />
<sourceFolder url="file://$MODULE_DIR$/core/src" isTestSource="false" />
<sourceFolder url="file://$MODULE_DIR$/macroquad/src" isTestSource="false" />
<excludeFolder url="file://$MODULE_DIR$/target" />
</content>
<orderEntry type="inheritedJdk" />
<orderEntry type="sourceFolder" forTests="false" />
</component>
</module>

6
.bad/vcs.xml Normal file
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@ -0,0 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<project version="4">
<component name="VcsDirectoryMappings">
<mapping directory="" vcs="Git" />
</component>
</project>

2
.idea/mos6502.iml generated
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@ -6,6 +6,8 @@
<sourceFolder url="file://$MODULE_DIR$/core/src" isTestSource="false" />
<sourceFolder url="file://$MODULE_DIR$/macroquad/src" isTestSource="false" />
<sourceFolder url="file://$MODULE_DIR$/src" isTestSource="false" />
<sourceFolder url="file://$MODULE_DIR$/beneater/src" isTestSource="false" />
<sourceFolder url="file://$MODULE_DIR$/core/tests" isTestSource="true" />
<excludeFolder url="file://$MODULE_DIR$/target" />
</content>
<orderEntry type="inheritedJdk" />

17
cli/src/bin/decode.rs
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@ -1,11 +1,22 @@
use core::instruction::Instruction;
use core::address_mode::AddressMode;
use core::operand::Operand;
use core::operation::Operation;
fn main() {
println!("Taxation is Theft");
// Instruction::from_bytes(vec![0b11100011]);
let instructions = vec![(
Instruction {
op: Operation::NOP,
mode: AddressMode::Implied,
operand: Operand::None,
}, &[0xea]
)];
// let instruction = Instruction::ADC(AddressMode::Immediate);
// println!("Instruction = {:?}", instruction.to_string());
for (op, bytes) in instructions {
assert_eq!(Instruction::decode(bytes), Some(op));
}
// let instruction = Instruction::decode(&[0xea]);
// println!("NOP Decoded -> {:?}", instruction);
}

70
core/src/instruction.rs
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@ -15,6 +15,7 @@ pub struct Instruction {
impl Instruction {
pub fn decode(bytes: &[u8]) -> Option<Instruction> {
println!("DECODING : {bytes:?}");
let opcode = bytes.get(0).copied()?;
let info = INSTRUCTION_TABLE[opcode as usize]?;
@ -25,14 +26,18 @@ impl Instruction {
let hi = *bytes.get(2)?;
Operand::Word(u16::from_le_bytes([lo, hi]))
}
_ => return None,
_ => Operand::None,
};
Some(Instruction {
let return_value = Some(Instruction {
op: info.operation,
mode: info.mode,
operand,
})
});
println!("RETURNING: {:?}", return_value);
return_value
}
}
@ -41,7 +46,7 @@ impl Instruction {
mod test {
use crate::address_mode::AddressMode::*;
use crate::instruction::Instruction;
use crate::operation::Operation::ADC;
use crate::operation::Operation::{ADC, INY, LSR};
use super::*;
#[test]
@ -75,14 +80,14 @@ mod test {
(vec![0x24, 0xab], Instruction { op: BIT, mode: ZeroPage, operand: Operand::Byte(0xab) }),
(vec![0x2c, 0xcd, 0xab], Instruction { op: BIT, mode: Absolute, operand: Operand::Word(0xabcd) }),
// BCC, BCS, BEQ, BMI, BNE, BPL, BVC, BVS
(vec![0x10, 0xab], Instruction { op: BPL, mode: Immediate, operand: Operand::Byte(0xab) }),
(vec![0x30, 0xab], Instruction { op: BMI, mode: Immediate, operand: Operand::Byte(0xab) }),
(vec![0x50, 0xab], Instruction { op: BVC, mode: Immediate, operand: Operand::Byte(0xab) }),
(vec![0x70, 0xab], Instruction { op: BVS, mode: Immediate, operand: Operand::Byte(0xab) }),
(vec![0x90, 0xab], Instruction { op: BCC, mode: Immediate, operand: Operand::Byte(0xab) }),
(vec![0xb0, 0xab], Instruction { op: BCS, mode: Immediate, operand: Operand::Byte(0xab) }),
(vec![0xd0, 0xab], Instruction { op: BNE, mode: Immediate, operand: Operand::Byte(0xab) }),
(vec![0xf0, 0xab], Instruction { op: BEQ, mode: Immediate, operand: Operand::Byte(0xab) }),
(vec![0x10, 0xab], Instruction { op: BPL, mode: Implied, operand: Operand::Byte(0xab) }),
(vec![0x30, 0xab], Instruction { op: BMI, mode: Implied, operand: Operand::Byte(0xab) }),
(vec![0x50, 0xab], Instruction { op: BVC, mode: Implied, operand: Operand::Byte(0xab) }),
(vec![0x70, 0xab], Instruction { op: BVS, mode: Implied, operand: Operand::Byte(0xab) }),
(vec![0x90, 0xab], Instruction { op: BCC, mode: Implied, operand: Operand::Byte(0xab) }),
(vec![0xb0, 0xab], Instruction { op: BCS, mode: Implied, operand: Operand::Byte(0xab) }),
(vec![0xd0, 0xab], Instruction { op: BNE, mode: Implied, operand: Operand::Byte(0xab) }),
(vec![0xf0, 0xab], Instruction { op: BEQ, mode: Implied, operand: Operand::Byte(0xab) }),
// BRK
(vec![0x00], Instruction { op: BRK, mode: Implied, operand: Operand::None }),
// CLC, CLD, CLI, CLV
@ -129,7 +134,7 @@ mod test {
(vec![0xee, 0xcd, 0xab], Instruction { op: INC, mode: Absolute, operand: Operand::Word(0xabcd) }),
(vec![0xfe, 0xcd, 0xab], Instruction { op: INC, mode: AbsoluteX, operand: Operand::Word(0xabcd) }),
(vec![0xe8], Instruction { op: INX, mode: Implied, operand: Operand::None }),
(vec![0xc8], Instruction { op: INX, mode: Implied, operand: Operand::None }),
(vec![0xc8], Instruction { op: INY, mode: Implied, operand: Operand::None }),
// JMP, JSR
(vec![0x4c, 0xcd, 0xab], Instruction { op: JMP, mode: Absolute, operand: Operand::Word(0xabcd) }),
(vec![0x6c, 0xcd, 0xab], Instruction { op: JMP, mode: Indirect, operand: Operand::Word(0xabcd) }),
@ -146,21 +151,21 @@ mod test {
// LDX
(vec![0xa2, 0xab], Instruction { op: LDX, mode: Immediate, operand: Operand::Byte(0xab) }),
(vec![0xa6, 0xab], Instruction { op: LDX, mode: ZeroPage, operand: Operand::Byte(0xab) }),
(vec![0xb6, 0xab], Instruction { op: LDX, mode: ZeroPageX, operand: Operand::Byte(0xab) }),
(vec![0xb6, 0xab], Instruction { op: LDX, mode: ZeroPageY, operand: Operand::Byte(0xab) }),
(vec![0xae, 0xcd, 0xab], Instruction { op: LDX, mode: Absolute, operand: Operand::Word(0xabcd) }),
(vec![0xbe, 0xcd, 0xab], Instruction { op: LDX, mode: AbsoluteX, operand: Operand::Word(0xabcd) }),
(vec![0xbe, 0xcd, 0xab], Instruction { op: LDX, mode: AbsoluteY, operand: Operand::Word(0xabcd) }),
// LDY
(vec![0xa2, 0xab], Instruction { op: LDY, mode: Immediate, operand: Operand::Byte(0xab) }),
(vec![0xa6, 0xab], Instruction { op: LDY, mode: ZeroPage, operand: Operand::Byte(0xab) }),
(vec![0xb6, 0xab], Instruction { op: LDY, mode: ZeroPageX, operand: Operand::Byte(0xab) }),
(vec![0xae, 0xcd, 0xab], Instruction { op: LDY, mode: Absolute, operand: Operand::Word(0xabcd) }),
(vec![0xbe, 0xcd, 0xab], Instruction { op: LDY, mode: AbsoluteX, operand: Operand::Word(0xabcd) }),
(vec![0xa0, 0xab], Instruction { op: LDY, mode: Immediate, operand: Operand::Byte(0xab) }),
(vec![0xa4, 0xab], Instruction { op: LDY, mode: ZeroPage, operand: Operand::Byte(0xab) }),
(vec![0xb4, 0xab], Instruction { op: LDY, mode: ZeroPageX, operand: Operand::Byte(0xab) }),
(vec![0xac, 0xcd, 0xab], Instruction { op: LDY, mode: Absolute, operand: Operand::Word(0xabcd) }),
(vec![0xbc, 0xcd, 0xab], Instruction { op: LDY, mode: AbsoluteX, operand: Operand::Word(0xabcd) }),
// LSR
(vec![0x4a, 0xab], Instruction { op: LDY, mode: Accumulator, operand: Operand::Byte(0xab) }),
(vec![0x46, 0xab], Instruction { op: LDY, mode: ZeroPage, operand: Operand::Byte(0xab) }),
(vec![0x56, 0xab], Instruction { op: LDY, mode: ZeroPageX, operand: Operand::Byte(0xab) }),
(vec![0x4e, 0xcd, 0xab], Instruction { op: LDY, mode: Absolute, operand: Operand::Word(0xabcd) }),
(vec![0x5e, 0xcd, 0xab], Instruction { op: LDY, mode: AbsoluteX, operand: Operand::Word(0xabcd) }),
(vec![0x4a], Instruction { op: LSR, mode: Accumulator, operand: Operand::None }),
(vec![0x46, 0xab], Instruction { op: LSR, mode: ZeroPage, operand: Operand::Byte(0xab) }),
(vec![0x56, 0xab], Instruction { op: LSR, mode: ZeroPageX, operand: Operand::Byte(0xab) }),
(vec![0x4e, 0xcd, 0xab], Instruction { op: LSR, mode: Absolute, operand: Operand::Word(0xabcd) }),
(vec![0x5e, 0xcd, 0xab], Instruction { op: LSR, mode: AbsoluteX, operand: Operand::Word(0xabcd) }),
// NOP
(vec![0xea], Instruction { op: NOP, mode: Implied, operand: Operand::None }),
// ORA
@ -178,13 +183,13 @@ mod test {
(vec![0x68], Instruction { op: PLA, mode: Implied, operand: Operand::None }),
(vec![0x28], Instruction { op: PLP, mode: Implied, operand: Operand::None }),
// ROL
(vec![0x2a, 0xab], Instruction { op: ROL, mode: Accumulator, operand: Operand::Byte(0xab) }),
(vec![0x2a], Instruction { op: ROL, mode: Accumulator, operand: Operand::None }),
(vec![0x26, 0xab], Instruction { op: ROL, mode: ZeroPage, operand: Operand::Byte(0xab) }),
(vec![0x36, 0xab], Instruction { op: ROL, mode: ZeroPageX, operand: Operand::Byte(0xab) }),
(vec![0x2e, 0xcd, 0xab], Instruction { op: ROL, mode: Absolute, operand: Operand::Word(0xabcd) }),
(vec![0x3e, 0xcd, 0xab], Instruction { op: ROL, mode: AbsoluteX, operand: Operand::Word(0xabcd) }),
// ROR
(vec![0x6a, 0xab], Instruction { op: ROR, mode: Accumulator, operand: Operand::Byte(0xab) }),
(vec![0x6a], Instruction { op: ROR, mode: Accumulator, operand: Operand::None }),
(vec![0x66, 0xab], Instruction { op: ROR, mode: ZeroPage, operand: Operand::Byte(0xab) }),
(vec![0x76, 0xab], Instruction { op: ROR, mode: ZeroPageX, operand: Operand::Byte(0xab) }),
(vec![0x6e, 0xcd, 0xab], Instruction { op: ROR, mode: Absolute, operand: Operand::Word(0xabcd) }),
@ -215,7 +220,7 @@ mod test {
(vec![0x91, 0xab], Instruction { op: STA, mode: IndirectY, operand: Operand::Byte(0xab) }),
// STX
(vec![0x86, 0xab], Instruction { op: STX, mode: ZeroPage, operand: Operand::Byte(0xab) }),
(vec![0x96, 0xab], Instruction { op: STX, mode: ZeroPageX, operand: Operand::Byte(0xab) }),
(vec![0x96, 0xab], Instruction { op: STX, mode: ZeroPageY, operand: Operand::Byte(0xab) }),
(vec![0x8e, 0xcd, 0xab], Instruction { op: STX, mode: Absolute, operand: Operand::Word(0xabcd) }),
// STY
(vec![0x84, 0xab], Instruction { op: STY, mode: ZeroPage, operand: Operand::Byte(0xab) }),
@ -230,13 +235,12 @@ mod test {
(vec![0x98], Instruction { op: TYA, mode: Implied, operand: Operand::None })
];
for (bytes, instruction) in params {
let result = Instruction::decode(&bytes);
if let Some(instruction) = result {
assert_eq!(Instruction::decode(&bytes).unwrap(), instruction)
let result1 = Instruction::decode(&bytes);
if let Some(instruction1) = result1 {
assert_eq!(instruction, instruction1)
} else {
println!("Failed to decode {:?}", bytes);
}
}
}
}
}

4
core/src/instruction_table.rs
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@ -256,13 +256,13 @@ pub const INSTRUCTION_TABLE: [Option<OpInfo>; 256] = {
table[ISA_OP_CMP_ABSX as usize] = Some(OpInfo {
operation: CMP,
mode: AddressMode::AbsoluteX,
length: 2,
length: 3,
cycles: 4,
});
table[ISA_OP_CMP_ABSY as usize] = Some(OpInfo {
operation: CMP,
mode: AddressMode::AbsoluteY,
length: 2,
length: 3,
cycles: 4,
});
table[ISA_OP_CMP_INDX as usize] = Some(OpInfo {

14
core/src/mos6502cpu.rs
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@ -1,3 +1,4 @@
use crate::instruction::Instruction;
use crate::mos6502flags::{Mos6502Flag, Mos6502Flags};
pub const SIZE_1KB: usize = 1024 * 1024;
@ -103,6 +104,15 @@ impl Mos6502Cpu {
/// Returns
/// AddressBus, DataBus, RW flag
pub fn tick(&mut self) -> (u16, u8, bool) {
let num_microsteps_left = 0;
if num_microsteps_left == 0 {
// load the microstep buffer with what steps to run
// set the counter to the number of steps left
}
// run 1 microcode step
(0,0,false)
}
@ -114,4 +124,8 @@ impl Mos6502Cpu {
pub fn dump_data(&self) -> ( u16, u8, u8, u8, u16, u8) {
(self.pc, self.a, self.x, self.y, self.address_bus, self.data_bus)
}
fn run_microstep(&self, instruction: Instruction, step: u8) {
}
}