Lots of stuff.

core/src/computers/beneater/mod.rs

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+pub mod beneater;

core/src/computers/kim1/mod.rs

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+pub mod new;
+pub mod tick;
+pub mod reset;
+
+use std::fs;
+use std::path::Path;
+use crate::constants::constants_system::SIZE_1KB;
+use crate::mos6502cpu::cpu::Mos6502Cpu;
+use crate::periph::at28c256::At28C256;
+use crate::periph::hm62256::Hm62256;
+use crate::periph::kim1_keypad::Kim1Keypad;
+use crate::periph::mos6522::mos6522::Mos6522;
+use crate::periph::mos6530::mos6530::Mos6530;
+
+/// Represents a KIM-1
+///
+///
+pub struct Kim1 {
+    pub running: bool,
+    pub cpu: Mos6502Cpu,
+    rriot1: Mos6530,
+    rriot2: Mos6530,
+    ram: Hm62256,
+    pub(crate) keypad: Kim1Keypad,
+    address_bus: u16,
+    data_bus: u8,
+    cpu_read: bool
+}

core/src/computers/kim1/new.rs

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+use crate::computers::kim1::Kim1;
+use crate::periph::hm62256::Hm62256;
+use crate::periph::kim1_keypad::Kim1Keypad;
+use crate::periph::mos6530::mos6530::Mos6530;
+
+impl Kim1 {
+    pub fn dump(&self) {
+        println!("DUMPING KIM-1 PC STATE");
+        self.cpu.dump();
+        self.rriot1.dump();
+        self.rriot2.dump();
+        self.keypad.dump();
+    }
+
+    pub fn new() -> Self {
+        let rriot1_rom = include_bytes!("/home/tmerritt/Projects/mos6502/resources/kim1/6530-002_fillerbyte00-0x1c00.bin");
+        let rriot2_rom = include_bytes!("/home/tmerritt/Projects/mos6502/resources/kim1/6530-003_fillerbyte00-0x1800.bin");
+
+        Self {
+            cpu: Default::default(),
+            rriot1: Mos6530::new(0x1700, 0x1780, 0x1800, &rriot1_rom),
+            rriot2: Mos6530::new(0x1740, 0x17C0, 0x1C00, &rriot2_rom),
+            ram: Hm62256::new(0x0000),
+            keypad: Kim1Keypad::new(),
+            address_bus: 0,
+            data_bus: 0,
+            cpu_read: false,
+            running: false
+        }
+    }
+}

core/src/computers/kim1/reset.rs

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+use crate::computers::kim1::Kim1;
+use crate::periph::hm62256::Hm62256;
+use crate::periph::mos6530::mos6530::Mos6530;
+
+impl Kim1 {
+    pub fn reset(&mut self) {
+        let rriot1_rom = include_bytes!("/home/tmerritt/Projects/mos6502/resources/kim1/6530-002_fillerbyte00-0x1c00.bin");
+        let rriot2_rom = include_bytes!("/home/tmerritt/Projects/mos6502/resources/kim1/6530-003_fillerbyte00-0x1800.bin");
+        self.cpu = Default::default();
+        self.rriot1 = Mos6530::new(0x1700, 0x1780, 0x1800, rriot1_rom.as_array().unwrap());
+        self.rriot2 = Mos6530::new(0x1740, 0x17c0, 0x1c00, rriot2_rom.as_array().unwrap());
+        self.ram = Hm62256::new(0x0000);
+        self.address_bus = 0x0000;
+        self.data_bus = 0x0000;
+        self.cpu_read = true;
+        self.cpu.pc = 0x0000;
+    }
+}

core/src/computers/kim1/tick.rs

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+use crate::computers::kim1::Kim1;
+
+impl Kim1 {
+    pub fn tick(&mut self) {
+        println!("<- START KIM-1 Backplane Tick");
+        let (address_bus, data, rw) = self.cpu.tick2(self.address_bus, self.data_bus);
+        self.address_bus = address_bus;
+        self.data_bus = data;
+        self.cpu_read = rw;
+        // now tick the various items connected
+
+        self.rriot1.tick(self.address_bus, self.data_bus, false, self.cpu_read);
+        self.rriot2.tick(self.address_bus, self.data_bus, false, self.cpu_read);
+        self.ram.tick(self.address_bus, self.data_bus, self.cpu_read, true);
+
+
+        let (rr1_io, rr1_ram, rr1_rom) = self.rriot1.dump_data();
+        let (rr2_io, rr2_ram, rr2_rom) = self.rriot2.dump_data();
+
+        println!(" 0x0000 -> RAM / {}", self.ram.dump_data());
+        println!(" 0x1700 -> RRIOT 1 / 0x{rr1_io:04x}/0x{rr1_ram:04x}/0x{rr1_rom:04x}");
+        println!(" 0x1740 -> RRIOT 2 / 0x{rr2_io:04x}/0x{rr2_ram:04x}/0x{rr2_rom:04x}");
+        // display the memory map and device states
+        println!("-> FINISH KIM-1 Backplane Tick");
+    }
+}

core/src/computers/mod.rs

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+pub mod beneater;
+pub mod rom_only;
+pub mod kim1;
+pub mod ram_rom;

core/src/computers/ram_rom/backplane.rs

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+use crate::periph::at28c256::At28C256;
+use crate::periph::backplane::Backplane;
+use crate::periph::hm62256::Hm62256;
+
+pub struct RamRomComputer {
+    rom: At28C256,
+    ram: Hm62256,
+    data_bus: u8,
+    address_bus: u16,
+    read_mode: bool,
+}
+
+impl Backplane for RamRomComputer {
+    fn data_bus(&self) -> u8 {
+        self.data_bus
+    }
+
+    fn address_bus(&self) -> u16 {
+        self.address_bus
+    }
+
+    fn read_mode(&self) -> bool {
+        self.read_mode
+    }
+
+    fn tick(&mut self) {
+        todo!()
+    }
+    fn set_read_mode(&mut self, new_mode: bool) {
+        self.read_mode = new_mode;
+    }
+
+    fn set_address_bus(&mut self, new_value: u16) {
+        self.address_bus = new_value;
+    }
+
+    fn set_data_bus(&mut self, new_value: u8) {
+        self.data_bus = new_value;
+    }
+}
+
+impl RamRomComputer {
+    pub fn new() -> RamRomComputer {
+        RamRomComputer {
+            rom: At28C256::default(),
+            ram: Hm62256::default(),
+            data_bus: 0x00,
+            address_bus: 0x0000,
+            /// is the CPU reading from the 'other' device?
+            read_mode: true
+        }
+    }
+}

core/src/computers/ram_rom/mod.rs

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+pub mod backplane;

core/src/computers/rom_only/backplane.rs

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+use crate::constants::constants_system::{SIZE_32KB, SIZE_64KB};
+use crate::periph::at28c256::At28C256;
+use crate::periph::backplane::Backplane;
+use crate::periph::rom_chip::RomChip;
+pub struct RomOnlyComputer {
+    rom: At28C256,
+    data_bus: u8,
+    address_bus: u16,
+    read_mode: bool,
+}
+
+impl Backplane for RomOnlyComputer {
+    fn data_bus(&self) -> u8 { self.data_bus }
+    fn address_bus(&self) -> u16 { self.address_bus }
+    fn read_mode(&self) -> bool { self.read_mode }
+
+    fn set_read_mode(&mut self, new_mode: bool) {
+        self.read_mode = new_mode
+    }
+
+    fn set_data_bus(&mut self, new_value: u8) {
+        self.data_bus = new_value
+    }
+
+    fn set_address_bus(&mut self, new_value: u16) {
+        self.address_bus = new_value
+    }
+
+    fn tick(&mut self) {
+        println!("COMPUTER: Preparing to tick.");
+
+        // do are we being addressed?
+        println!("COMPUTER: BUSSES PRE: 0x{:04x} 0x{:02x} {}", self.address_bus, self.data_bus, self.read_mode);
+        let (new_addr, new_data) = self.rom.tick(self.address_bus, self.data_bus, self.read_mode);
+        self.set_address_bus(new_addr);
+        self.set_data_bus(new_data);
+        println!("COMPUTER: BUSSES POST: 0x{:04x} 0x{:02x} {}", self.address_bus, self.data_bus, self.read_mode);
+        println!("COMPUTER: Done ticking.");
+    }
+}
+
+impl RomOnlyComputer {
+    pub fn new() -> RomOnlyComputer {
+        let mut working = vec![0x00u8; SIZE_32KB];
+        for index in 0..SIZE_32KB {
+            working[index] = index as u8;
+        }
+        RomOnlyComputer::program(working)
+    }
+
+    pub fn program(rom: Vec<u8>) -> RomOnlyComputer {
+        RomOnlyComputer {
+            rom: At28C256::new(0x000, 0x3fff, rom),
+            address_bus: 0x0000,
+            data_bus: 0x00,
+            read_mode: true,
+        }
+    }
+}

core/src/computers/rom_only/mod.rs

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+pub mod backplane;