Lots of stuff.

core/src/periph/hm62256/mod.rs

@@ -0,0 +1,70 @@
+// HM62256 Static Ram
+
+pub mod ramchip;
+pub mod romchip;
+pub mod tick;
+pub mod default;
+pub mod new;
+pub mod dump;
+
+use crate::constants::constants_system::SIZE_32KB;
+use crate::periph::ram_chip::RamChip;
+use crate::periph::rom_chip::RomChip;
+use log::debug;
+
+/// Hitachi Semiconductor
+/// 8 Bit High Speed Static Ram
+/// 32KByte
+pub struct Hm62256 {
+    pub(crate) offset: u16,
+    pub(crate) data: Box<[u8]>,
+    pub(crate) address_bus: u16,
+    pub(crate) data_bus: u8
+}
+
+#[cfg(test)]
+mod test {
+    use super::*;
+    use rand::random;
+
+    #[test]
+    fn smoke() {
+        assert!(true)
+    }
+
+    #[test]
+    fn written_data_comes_back() {
+        let mut ram = Hm62256::default();
+
+        // 100,000 random read/writes to ram that all read back right
+        for _ in 0..100_000 {
+            let mut offset: u16 = random();
+            println!("Size = {SIZE_32KB}");
+            let value: u8 = random();
+            println!("Wrote [{value:02x}] to [{offset:04x}]");
+            ram.write(&offset, &value);
+
+            assert_eq!(ram.read(&offset), value)
+        }
+    }
+
+    #[test]
+    fn address_space_is_round() {
+        // addresses written past the last address 'loop' back to 0+(offset - MAX_SIZE)
+        let max_offset = SIZE_32KB;
+        let test_offset = max_offset;
+
+        // all zero
+        let mut ram = Hm62256::default();
+        // write FF to the addresss after the last
+        ram.write(&(test_offset as u16), &0xff);
+
+        // check all the ram for anything that isn't 0x00
+
+        assert_eq!(ram.read(&(0x0000)), 0xff);
+        for offset in 1..SIZE_32KB {
+            println!("Testing offset {offset:04x} for 0x00");
+            assert_eq!(ram.read(&(offset as u16)), 0x00);
+        }
+    }
+}