writes bins better now

core/src/periph/at28c256/mod.rs

@@ -1,6 +1,8 @@
 pub mod default;
 pub mod rom_chip;
 pub mod tick;
+mod new;
+mod program;
 
 use crate::constants::constants_system::SIZE_32KB;
 use crate::periph::rom_chip::RomChip;
@@ -16,14 +18,6 @@ pub struct At28C256 {
     data: Box<[u8; SIZE_32KB]>,
 }
 
-impl At28C256 {
-    pub fn program(&mut self, new_program: &[u8; SIZE_32KB]) {
-        // panic!("FAIL.  Cant program the chip.");
-        // println!("PROGRAMMING {:?}", new_program);
-        self.data = Box::new(*new_program);
-    }
-}
-
 #[cfg(test)]
 mod test {
     use super::*;

core/src/periph/at28c256/new.rs

@@ -0,0 +1,10 @@
+use crate::constants::constants_system::SIZE_32KB;
+use crate::periph::at28c256::At28C256;
+
+impl At28C256 {
+    pub fn new(data: &[u8; SIZE_32KB]) -> Self {
+        At28C256 {
+            data: (*data).into()
+        }
+    }
+}

core/src/periph/at28c256/program.rs

@@ -0,0 +1,10 @@
+use crate::constants::constants_system::SIZE_32KB;
+use crate::periph::at28c256::At28C256;
+
+impl At28C256 {
+    pub fn program(&mut self, new_program: &[u8; SIZE_32KB]) {
+        // panic!("FAIL.  Cant program the chip.");
+        // println!("PROGRAMMING {:?}", new_program);
+        self.data = Box::new(*new_program);
+    }
+}

core/src/periph/at28c256/tick.rs

@@ -3,8 +3,10 @@ use crate::periph::hm62256::Hm62256;
 
 impl At28C256 {
     fn tick(&mut self, address_bus: u16, data_bus: u8, read_mode: bool) -> (u16, u8) {
-        if !read_mode {
-            // has to be read mode.  its a rom.
+        if read_mode {
+            panic!("UNABLE TO WRITE TO ROM");
+        } else {
+        // has to be read mode.  its a rom.
             return (address_bus, data_bus)
         }
         (address_bus, self.data[address_bus as usize])

core/src/periph/hm62256/tick.rs

@@ -25,7 +25,9 @@ mod test {
     fn write_to_memory_read_back_works_at_0() {
         let mut ram = Hm62256::default();
 
+        // load the data to ram
         ram.tick(0x0000, 0xab, false);
+        // read the data back
         let (_, new_data) = ram.tick(0x0000, 0x00, true);
 
         assert_eq!(new_data, 0xab);

core/src/periph/mod.rs

@@ -3,3 +3,4 @@ pub mod rom_chip;
 pub mod at28c256;
 pub mod hm62256;
 pub mod ram_chip;
+pub mod mos6522;

core/src/periph/mos6522/mod.rs

@@ -0,0 +1,2 @@
+pub mod mos6522;
+mod registers;

core/src/periph/mos6522/mos6522.rs

@@ -0,0 +1,165 @@
+use std::time::Instant;
+use log::debug;
+use crate::constants::constants_via6522::*;
+
+#[derive(Default)]
+pub struct Mos6522 {
+    /// data direction
+    dda: u8,
+    ddb: u8,
+
+    /// bottom 4 address bits
+    rs0: u8,
+    rs1: u8,
+    rs2: u8,
+    rs3: u8,
+
+    /// external data bus
+    data_bus: u8,
+
+    cs1: bool,
+    cs2: bool,
+    rw: bool,
+
+    /// reset circuit - true when reset inited
+    reset: bool,
+
+    /// IRQ - true when interrupt waiting
+    irq: bool,
+
+    ira: u8,
+    ora: u8,
+    porta: u8,
+    irb: u8,
+    orb: u8,
+    portb: u8,
+
+    ca1: bool,
+    ca2: bool,
+    cb1: bool,
+    cb2: bool,
+}
+
+impl Mos6522 {
+    pub fn new() -> Self {
+        Mos6522::default()
+    }
+
+    /// tick
+    ///
+    /// data_bus -> 8 bits from the data bus
+    /// control  -> 4 bits to identify which register to control
+    pub fn tick(&mut self, data_bus: u8, control: u8, rw: bool) -> (u8) {
+        println!("Mos6522 Tick Start -> 0x{data_bus:02x} / 0x{control:02x} / {rw}");
+        if rw  {
+            // RW true = CPU is writing
+            self.data_bus = data_bus;
+            match control {
+                VIA6522_DDRA => {
+                    debug!("Setting DDA to 0x{data_bus:02x}");
+                    // setting the Data Direction for Port A
+                    self.dda = data_bus;
+                },
+                VIA6522_DDRB => {
+                    debug!("Setting DDB to 0x{data_bus:02x}");
+                    // setting the data direction for port b
+                    self.ddb = data_bus;
+                },
+                VIA6522_ORB => {
+                    // writing data to ORB
+                    let masked_data = data_bus & self.ddb;
+                    debug!("Setting ORB to 0x{data_bus:02x} / masked at 0x{masked_data:02x}");
+                    self.portb = masked_data;
+                },
+                VIA6522_ORA => {
+                    // writing data to ORA
+                    let masked_data = data_bus & self.dda;
+                    debug!("Setting ORA to 0x{data_bus:02x} / masked at 0x{masked_data:02x}");
+                    self.porta = masked_data;
+                },
+                _ => {}
+            }
+        } else {
+            // RW false = CPU is reading
+            self.data_bus = match control {
+                VIA6522_DDRA => {
+                    self.dda
+                }
+                VIA6522_DDRB => {
+                    self.ddb
+                }
+                VIA6522_ORA => {
+                    self.porta & self.dda
+                }
+                VIA6522_ORB => {
+                    self.portb & self.ddb
+                }
+                _ => {
+                    debug!("VIA got request for b{:08b} / 0x{:02x}", control, control);
+                    // do nothing.  bad address for VIA
+                    self.data_bus
+                }
+            }
+        }
+
+        (self.data_bus)
+    }
+
+    pub fn start_clocks(&mut self) {
+        loop {
+            let cycle_start = Instant::now();
+            // let duration = cycle_start.duration_since(self.clock);
+            // set the time to the new time.
+            // self.clock = cycle_start;
+        }
+    }
+}
+
+
+#[cfg(test)]
+mod test {
+    use super::*;
+
+    #[test]
+    fn smoke() { assert!(true); }
+
+    #[test]
+    fn registers() {
+        let mut x = Mos6522::new();
+        x.tick(0b0000_0000, VIA6522_DDRA, true);
+        assert_eq!(x.dda, 0b0000_0000);
+        x.tick(0b1111_1111, VIA6522_DDRA, true);
+        assert_eq!(x.dda, 0b1111_1111);
+
+        x.tick(0b0000_0000, VIA6522_DDRB, true);
+        assert_eq!(x.ddb, 0b0000_0000);
+        x.tick(0b1111_1111, VIA6522_DDRB, true);
+        assert_eq!(x.ddb, 0b1111_1111);
+
+        x.tick(0b0000_0000, VIA6522_ORA, true);
+        assert_eq!(x.porta, 0b0000_0000);
+        x.tick(0b1111_1111, VIA6522_ORA, true);
+        assert_eq!(x.porta, 0b1111_1111);
+
+        x.tick(0b0000_0000, VIA6522_ORB, true);
+        assert_eq!(x.portb, 0b0000_0000);
+        x.tick(0b1111_1111, VIA6522_ORB, true);
+        assert_eq!(x.portb, 0b1111_1111);
+    }
+
+    #[test]
+    fn partial_output_porta() {
+        let mut x = Mos6522::new();
+        x.tick(0b1010_1010, VIA6522_DDRA, true);
+        x.tick(0b1111_1111, VIA6522_ORA, true);
+        assert_eq!(x.porta, 0b1010_1010);
+    }
+
+    #[test]
+    fn partial_output_portb() {
+        let mut x = Mos6522::new();
+        x.tick(0b0101_0101, VIA6522_DDRB, true);
+        x.tick(0b1111_1111, VIA6522_ORB, true);
+        assert_eq!(x.portb, 0b0101_0101);
+    }
+}

core/src/periph/mos6522/registers.rs

@@ -0,0 +1,12 @@
+pub enum Via6522Registers {
+    ORA,
+    ORB,
+    DDRA,
+    DDRB,
+    T1WL,
+    T1CL,
+    T1CH,
+    T1LL,
+    T2LL,
+    T2CH,
+}