closer to being able to run a cycle?

core/src/periph/at28c256.rs

@@ -1,4 +1,4 @@
-use crate::mos6502cpu::{SIZE_32KB, SIZE_64KB};
+use crate::mos6502cpu::{SIZE_32KB};
 use crate::periph::rom_chip::RomChip;
 
 /// At28C256
@@ -48,20 +48,14 @@ mod test {
 
     #[test]
     fn programmed_data_reads_back_same() {
-        print!("Starting test...");
         let mut data = At28C256::default();
         for i in 0..SIZE_32KB {
             data.data[i] = 0xea;
         }
-        print!("allocated data for rom...");
-        println!("programmed chip...");
-        print!("testing");
         for offset in 0..SIZE_32KB {
             if offset.is_multiple_of(SIZE_1KB) {
-              print!(".");
             };
            assert_eq!(0xea, data.read(&(offset as u16)));
         }
-        println!("passed!");
     }
 }

core/src/periph/hm62256.rs

@@ -0,0 +1,88 @@
+// HM62256 Static Ram
+
+use log::debug;
+use crate::mos6502cpu::SIZE_32KB;
+use crate::periph::ram_chip::RamChip;
+use crate::periph::rom_chip::RomChip;
+
+struct Hm62256 {
+    base_offset: u16,
+    data: Box<[u8]>
+}
+
+impl Default for Hm62256 {
+    fn default() -> Self {
+        let vec = vec![0x00; SIZE_32KB];
+        let boxed_slice: Box<[u8]> = vec.into_boxed_slice();
+        let boxed_array: Box<[u8; SIZE_32KB]> = boxed_slice.try_into().expect("Unable to box the ram");
+        Hm62256 {
+            base_offset: 0x0000,
+            data: boxed_array
+        }
+    }
+}
+
+impl RomChip for Hm62256 {
+    fn read(&self, offset: &u16) -> u8 {
+        //println!("READING FROM RAM AT [{offset:04x}]");
+        self.data[*offset as usize]
+    }
+
+    fn program(_: Box<[u8; SIZE_32KB]>) -> Box<Self> {
+        debug!("Dont program ram.");
+        Hm62256::default().into()
+    }
+}
+
+impl RamChip for Hm62256 {
+    fn write(&mut self, offset: &u16, value: &u8) {
+        let effective = *offset as i32  % SIZE_32KB as i32;
+        println!("Writing at E[{effective:04x}] / O[{offset:04x}]");
+        self.data[effective as usize] = *value;
+    }
+}
+
+#[cfg(test)]
+mod test {
+    use rand::random;
+    use super::*;
+
+    #[test]
+    fn smoke() { assert!(true) }
+
+    #[test]
+    fn written_data_comes_back() {
+        let mut ram = Hm62256::default();
+
+        // 100,000 random read/writes to ram that all read back right
+        for _ in 0..100_000 {
+            let mut offset: u16 = random();
+            println!("SIze = {SIZE_32KB}");
+            let value: u8 =random();
+            println!("Wrote [{value:02x}] to [{offset:04x}]");
+            ram.write(&offset, &value);
+
+            assert_eq!(ram.read(&offset), value)
+        }
+    }
+
+    #[test]
+    fn address_space_is_round() {
+        // addresses written past the last address 'loop' back to 0+(offset - MAX_SIZE)
+        let max_offset = SIZE_32KB;
+        let test_offset = max_offset;
+
+        // all zero
+        let mut ram = Hm62256::default();
+        // write FF to the addresss after the last
+        ram.write(&(test_offset as u16), &0xff);
+
+        // check all the ram for anything that isn't 0x00
+
+        assert_eq!(ram.read(&(0x0000)), 0xff);
+        for offset in 1..SIZE_32KB {
+            println!("Testing offset {offset:04x} for 0x00");
+            assert_eq!(ram.read(&(offset as u16)), 0x00);
+        }
+    }
+}

core/src/periph/mod.rs

@@ -1,3 +1,6 @@
 pub mod rom_chip;
 
 pub mod at28c256;
+pub mod ram_chip;
+mod hm62256;
+

core/src/periph/ram_chip.rs

@@ -0,0 +1,5 @@
+use crate::periph::rom_chip::RomChip;
+
+pub trait RamChip: RomChip {
+    fn write(&mut self, offset: &u16, value: &u8);
+}

core/src/periph/rom_chip.rs

@@ -10,7 +10,3 @@ pub trait RomChip {
     /// Replaces all data in the ROM chip
     fn program(new_data: Box<[u8; SIZE_32KB]>) -> Box<Self>;
 }
-
-pub trait RamChip: RomChip {
-    fn write(&mut self, offset: &u16, value: &u8);
-}