adds docs

working on widetick

core/src/computers/rom_only/backplane.rs

@@ -1,5 +1,6 @@
+use log::debug;
 use crate::computers::rom_only::RomOnlyComputer;
-use crate::periph::backplane::Backplane;
+use crate::traits::backplane::Backplane;
 
 impl Backplane for RomOnlyComputer {
     fn data_bus(&self) -> u8 { self.data_bus }
@@ -17,7 +18,6 @@ impl Backplane for RomOnlyComputer {
 
     fn tick(&mut self) {
         println!("COMPUTER: Preparing to tick.");
-
         // do are we being addressed?
         println!("COMPUTER: BUSSES PRE: 0x{:04x} 0x{:02x} {}", self.address_bus, self.data_bus, self.read_mode);
         let (new_addr, new_data) = self.rom.tick(self.address_bus, self.data_bus, self.read_mode);
@@ -26,4 +26,18 @@ impl Backplane for RomOnlyComputer {
         println!("COMPUTER: BUSSES POST: 0x{:04x} 0x{:02x} {}", self.address_bus, self.data_bus, self.read_mode);
         println!("COMPUTER: Done ticking.");
     }
+
+    fn tick_ram(&mut self, address: u16, data: u8, cs: bool, oe: bool, we: bool) {
+        debug!("This system has no ram.  ROM only.");
+    }
+
+    fn tick_rom(&mut self, address: u16, data: u8, cs: bool, oe: bool, we: bool) -> (u8) {
+        let (_, data) = self.rom.tick(address, data, true);
+        data
+    }
+
+    fn tick_via(&mut self, address: u16, data: u8, cs: bool, rw: bool, ce: bool) -> (u8, u8, bool) {
+        debug!("This system has no VIA controllers.  ROM only");
+        (0,0,true)
+    }
 }

core/src/computers/rom_only/mod.rs

@@ -1,5 +1,5 @@
 use crate::periph::at28c256::At28C256;
-use crate::periph::backplane::Backplane;
+use crate::traits::backplane::Backplane;
 
 pub mod backplane;
 pub mod new;