start of rom_only PC

core/src/periph/at28c256/mod.rs

@@ -1,5 +1,6 @@
-mod default;
-mod rom_chip;
+pub mod default;
+pub mod rom_chip;
+pub mod tick;
 
 use crate::constants::constants_system::SIZE_32KB;
 use crate::periph::rom_chip::RomChip;

core/src/periph/at28c256/tick.rs

@@ -0,0 +1,31 @@
+use crate::periph::at28c256::At28C256;
+use crate::periph::hm62256::Hm62256;
+
+impl At28C256 {
+    fn tick(&mut self, address_bus: u16, data_bus: u8, read_mode: bool) -> (u16, u8) {
+        if !read_mode {
+            // has to be read mode.  its a rom.
+            return (address_bus, data_bus)
+        }
+        (address_bus, self.data[address_bus as usize])
+    }
+}
+
+
+#[cfg(test)]
+mod test {
+    use super::*;
+
+    #[test]
+    fn smoke() { assert!(true); }
+
+    #[test]
+    fn write_to_memory_read_back_works_at_0() {
+        let mut rom = At28C256::default();
+
+        rom.tick(0x0000, 0xab, false);
+        let (_, new_data) = rom.tick(0x0000, 0x00, true);
+
+        assert_eq!(new_data, 0xab);
+    }
+}

core/src/periph/hm62256/mod.rs

@@ -1,10 +1,13 @@
 // HM62256 Static Ram
 
+pub mod ramchip;
+pub mod romchip;
+pub mod tick;
+
 use crate::constants::constants_system::SIZE_32KB;
 use crate::periph::ram_chip::RamChip;
 use crate::periph::rom_chip::RomChip;
 use log::debug;
-
 pub struct Hm62256 {
     pub(crate) base_offset: u16,
     pub(crate) data: Box<[u8]>,
@@ -23,27 +26,6 @@ impl Default for Hm62256 {
     }
 }
 
-impl RomChip for Hm62256 {
-    fn read(&self, offset: &u16) -> u8 {
-        // loops memory around past 32k
-        let effective = *offset as i32 % SIZE_32KB as i32;
-        self.data[effective as usize]
-    }
-
-    fn program(_: &[u8; SIZE_32KB]) -> Box<Self> {
-        debug!("Dont program ram.");
-        Hm62256::default().into()
-    }
-}
-
-impl RamChip for Hm62256 {
-    fn write(&mut self, offset: &u16, value: &u8) {
-        let effective = *offset as i32 % SIZE_32KB as i32;
-        println!("Writing at E[{effective:04x}] / O[{offset:04x}]");
-        self.data[effective as usize] = *value;
-    }
-}
-
 #[cfg(test)]
 mod test {
     use super::*;
@@ -61,7 +43,7 @@ mod test {
         // 100,000 random read/writes to ram that all read back right
         for _ in 0..100_000 {
             let mut offset: u16 = random();
-            println!("SIze = {SIZE_32KB}");
+            println!("Size = {SIZE_32KB}");
             let value: u8 = random();
             println!("Wrote [{value:02x}] to [{offset:04x}]");
             ram.write(&offset, &value);

core/src/periph/hm62256/ramchip.rs

@@ -0,0 +1,12 @@
+use crate::constants::constants_system::SIZE_32KB;
+use crate::periph::hm62256::Hm62256;
+use crate::periph::ram_chip::RamChip;
+
+impl RamChip for Hm62256 {
+    fn write(&mut self, offset: &u16, value: &u8) {
+        let effective = *offset as i32 % SIZE_32KB as i32;
+        println!("Writing at E[{effective:04x}] / O[{offset:04x}]");
+        self.data[effective as usize] = *value;
+    }
+}
+

core/src/periph/hm62256/romchip.rs

@@ -0,0 +1,19 @@
+use log::debug;
+use crate::constants::constants_system::SIZE_32KB;
+use crate::periph::hm62256::Hm62256;
+use crate::periph::rom_chip::RomChip;
+
+impl RomChip for Hm62256 {
+
+
+    fn read(&self, offset: &u16) -> u8 {
+        // loops memory around past 32k
+        let effective = *offset as i32 % SIZE_32KB as i32;
+        self.data[effective as usize]
+    }
+
+    fn program(_: &[u8; SIZE_32KB]) -> Box<Self> {
+        debug!("Dont program ram.");
+        Hm62256::default().into()
+    }
+}

core/src/periph/hm62256/tick.rs

@@ -0,0 +1,33 @@
+use crate::periph::hm62256::Hm62256;
+
+impl Hm62256 {
+    fn tick(&mut self, address_bus: u16, data_bus: u8, read_mode: bool) -> (u16, u8) {
+        let new_data_bus = if read_mode {
+            // reading from ram
+            self.data[address_bus as usize]
+        } else {
+            // writing to ram
+            self.data[address_bus as usize] = data_bus.into();
+            data_bus
+        };
+        (address_bus, new_data_bus)
+    }
+}
+
+#[cfg(test)]
+mod test {
+    use super::*;
+
+    #[test]
+    fn smoke() { assert!(true); }
+
+    #[test]
+    fn write_to_memory_read_back_works_at_0() {
+        let mut ram = Hm62256::default();
+
+        ram.tick(0x0000, 0xab, false);
+        let (_, new_data) = ram.tick(0x0000, 0x00, true);
+
+        assert_eq!(new_data, 0xab);
+    }
+}