start of rom_only PC

core/src/periph/hm62256/mod.rs

@@ -0,0 +1,74 @@
+// HM62256 Static Ram
+
+pub mod ramchip;
+pub mod romchip;
+pub mod tick;
+
+use crate::constants::constants_system::SIZE_32KB;
+use crate::periph::ram_chip::RamChip;
+use crate::periph::rom_chip::RomChip;
+use log::debug;
+pub struct Hm62256 {
+    pub(crate) base_offset: u16,
+    pub(crate) data: Box<[u8]>,
+}
+
+impl Default for Hm62256 {
+    fn default() -> Self {
+        let vec = vec![0x00; SIZE_32KB];
+        let boxed_slice: Box<[u8]> = vec.into_boxed_slice();
+        let boxed_array: Box<[u8; SIZE_32KB]> =
+            boxed_slice.try_into().expect("Unable to box the ram");
+        Hm62256 {
+            base_offset: 0x0000,
+            data: boxed_array,
+        }
+    }
+}
+
+#[cfg(test)]
+mod test {
+    use super::*;
+    use rand::random;
+
+    #[test]
+    fn smoke() {
+        assert!(true)
+    }
+
+    #[test]
+    fn written_data_comes_back() {
+        let mut ram = Hm62256::default();
+
+        // 100,000 random read/writes to ram that all read back right
+        for _ in 0..100_000 {
+            let mut offset: u16 = random();
+            println!("Size = {SIZE_32KB}");
+            let value: u8 = random();
+            println!("Wrote [{value:02x}] to [{offset:04x}]");
+            ram.write(&offset, &value);
+
+            assert_eq!(ram.read(&offset), value)
+        }
+    }
+
+    #[test]
+    fn address_space_is_round() {
+        // addresses written past the last address 'loop' back to 0+(offset - MAX_SIZE)
+        let max_offset = SIZE_32KB;
+        let test_offset = max_offset;
+
+        // all zero
+        let mut ram = Hm62256::default();
+        // write FF to the addresss after the last
+        ram.write(&(test_offset as u16), &0xff);
+
+        // check all the ram for anything that isn't 0x00
+
+        assert_eq!(ram.read(&(0x0000)), 0xff);
+        for offset in 1..SIZE_32KB {
+            println!("Testing offset {offset:04x} for 0x00");
+            assert_eq!(ram.read(&(offset as u16)), 0x00);
+        }
+    }
+}

core/src/periph/hm62256/ramchip.rs

@@ -0,0 +1,12 @@
+use crate::constants::constants_system::SIZE_32KB;
+use crate::periph::hm62256::Hm62256;
+use crate::periph::ram_chip::RamChip;
+
+impl RamChip for Hm62256 {
+    fn write(&mut self, offset: &u16, value: &u8) {
+        let effective = *offset as i32 % SIZE_32KB as i32;
+        println!("Writing at E[{effective:04x}] / O[{offset:04x}]");
+        self.data[effective as usize] = *value;
+    }
+}
+

core/src/periph/hm62256/romchip.rs

@@ -0,0 +1,19 @@
+use log::debug;
+use crate::constants::constants_system::SIZE_32KB;
+use crate::periph::hm62256::Hm62256;
+use crate::periph::rom_chip::RomChip;
+
+impl RomChip for Hm62256 {
+
+
+    fn read(&self, offset: &u16) -> u8 {
+        // loops memory around past 32k
+        let effective = *offset as i32 % SIZE_32KB as i32;
+        self.data[effective as usize]
+    }
+
+    fn program(_: &[u8; SIZE_32KB]) -> Box<Self> {
+        debug!("Dont program ram.");
+        Hm62256::default().into()
+    }
+}

core/src/periph/hm62256/tick.rs

@@ -0,0 +1,33 @@
+use crate::periph::hm62256::Hm62256;
+
+impl Hm62256 {
+    fn tick(&mut self, address_bus: u16, data_bus: u8, read_mode: bool) -> (u16, u8) {
+        let new_data_bus = if read_mode {
+            // reading from ram
+            self.data[address_bus as usize]
+        } else {
+            // writing to ram
+            self.data[address_bus as usize] = data_bus.into();
+            data_bus
+        };
+        (address_bus, new_data_bus)
+    }
+}
+
+#[cfg(test)]
+mod test {
+    use super::*;
+
+    #[test]
+    fn smoke() { assert!(true); }
+
+    #[test]
+    fn write_to_memory_read_back_works_at_0() {
+        let mut ram = Hm62256::default();
+
+        ram.tick(0x0000, 0xab, false);
+        let (_, new_data) = ram.tick(0x0000, 0x00, true);
+
+        assert_eq!(new_data, 0xab);
+    }
+}