box swap

cli/src/bin/ram_rom_widetick.rs

@@ -0,0 +1,27 @@
+use std::fs;
+use core::computers::ram_rom::RamRomComputer;
+use core::periph::backplane::Backplane;
+fn main() {
+    println!("Taxation is theft");
+    let path = "/home/tmerritt/Projects/mos6502/resources/test/periph/at28c256/checksum.bin";
+    let bytes = match fs::read(path) {
+        Ok(bytes) => {
+            println!("Loaded {} bytes", bytes.len());
+            bytes
+        },
+        Err(e) => vec![]
+    };
+
+    let mut ramrom_computer = RamRomComputer::program_rom((&bytes[..]).to_vec());
+
+    ramrom_computer.tick2(0x05, 0b0000_0000, 0x05);
+    println!("COMPUTER: Read {:02x} from ROM / {:04x} from Address bus",
+             ramrom_computer.data_bus(),
+             ramrom_computer.address_bus()
+    );
+    ramrom_computer.tick2(0x4005, 0b0000_0001, ramrom_computer.data_bus());
+    println!("COMPUTER: Read {:02x} from ROM / {:04x} from Address bus",
+             ramrom_computer.data_bus(),
+             ramrom_computer.address_bus()
+    );
+}

cli/src/bin/rom_only_widetick.rs

@@ -1,5 +1,6 @@
 use std::fs;
 use core::computers::rom_only::RomOnlyComputer;
+use core::periph::backplane::Backplane;
 
 fn main() {
     println!("Taxation is theft");
@@ -15,6 +16,5 @@ fn main() {
     let mut rom_only = RomOnlyComputer::program((&bytes[..]).to_vec());
 
     rom_only.tick2(0x05, 0b0000_0001, 0x05);
-    println!("COMPUTER: Read {:02x} from ROM", rom_only.data_bus()) ;
-    println!("COMPUTER: Read {:04x} from Address Bus", rom_only.address_bus());
+    println!("COMPUTER: Read {:02x} from ROM / {:04x} from Address bus", rom_only.data_bus(), rom_only.address_bus()) ;
 }

core/src/computers/ram_rom/backplane.rs

@@ -1,14 +1,8 @@
+use crate::computers::ram_rom::RamRomComputer;
 use crate::periph::at28c256::At28C256;
 use crate::periph::backplane::Backplane;
 use crate::periph::hm62256::Hm62256;
 
-pub struct RamRomComputer {
-    rom: At28C256,
-    ram: Hm62256,
-    data_bus: u8,
-    address_bus: u16,
-    read_mode: bool,
-}
 
 impl Backplane for RamRomComputer {
     fn data_bus(&self) -> u8 {
@@ -23,6 +17,18 @@ impl Backplane for RamRomComputer {
         self.read_mode
     }
 
+    fn set_read_mode(&mut self, new_mode: bool) {
+        self.read_mode = new_mode;
+    }
+
+    fn set_data_bus(&mut self, new_value: u8) {
+        self.data_bus = new_value;
+    }
+
+    fn set_address_bus(&mut self, new_value: u16) {
+        self.address_bus = new_value;
+    }
+
     fn tick(&mut self) {
         println!("Preparing to tick the backplane. - ${:04x} ${:02x} {}", self.address_bus, self.data_bus, self.read_mode);
 
@@ -47,30 +53,5 @@ impl Backplane for RamRomComputer {
             }
         }
     }
-
-    fn set_read_mode(&mut self, new_mode: bool) {
-        self.read_mode = new_mode;
-    }
-
-    fn set_address_bus(&mut self, new_value: u16) {
-        self.address_bus = new_value;
-    }
-
-    fn set_data_bus(&mut self, new_value: u8) {
-        self.data_bus = new_value;
-    }
 }
 
-impl RamRomComputer {
-    pub fn new() -> RamRomComputer {
-        let rom = At28C256::new(0x4000, 0x7fff, (0..255).collect());
-        RamRomComputer {
-            rom,
-            ram: Hm62256::default(),
-            data_bus: 0x00,
-            address_bus: 0x0000,
-            /// is the CPU reading from the 'other' device?
-            read_mode: true
-        }
-    }
-}

core/src/computers/ram_rom/mod.rs

@@ -1 +1,15 @@
+use crate::periph::at28c256::At28C256;
+use crate::periph::hm62256::Hm62256;
+
 pub mod backplane;
+pub mod program_rom;
+pub mod new;
+mod tick2;
+
+pub struct RamRomComputer {
+    pub(crate) rom: At28C256,
+    pub(crate) ram: Hm62256,
+    pub(crate) data_bus: u8,
+    pub(crate) address_bus: u16,
+    pub(crate) read_mode: bool,
+}

core/src/computers/ram_rom/new.rs

@@ -0,0 +1,17 @@
+use crate::computers::ram_rom::RamRomComputer;
+use crate::periph::at28c256::At28C256;
+use crate::periph::hm62256::Hm62256;
+
+impl RamRomComputer {
+    pub fn new() -> RamRomComputer {
+        let rom = At28C256::new(0x4000, 0x7fff, (0..255).collect());
+        RamRomComputer {
+            rom,
+            ram: Hm62256::default(),
+            data_bus: 0x00,
+            address_bus: 0x0000,
+            /// is the CPU reading from the 'other' device?
+            read_mode: true
+        }
+    }
+}

core/src/computers/ram_rom/program_rom.rs

@@ -0,0 +1,16 @@
+use crate::computers::ram_rom::RamRomComputer;
+use crate::periph::at28c256::At28C256;
+use crate::periph::hm62256::Hm62256;
+
+impl RamRomComputer {
+    pub fn program_rom(rom: Vec<u8>) -> RamRomComputer {
+        let new_rom = At28C256::new(0x0000, 0x3fff, rom);
+        RamRomComputer {
+            rom: new_rom,
+            ram: Hm62256::new(0x3fff),
+            data_bus: 0x00,
+            address_bus: 0x00,
+            read_mode: false,
+        }
+    }
+}

core/src/computers/ram_rom/tick2.rs

@@ -0,0 +1,27 @@
+use std::collections::BTreeMap;
+use crate::computers::ram_rom::RamRomComputer;
+use crate::traits::bus_device::BusDevice;
+
+impl RamRomComputer {
+    pub fn tick2(&mut self, address: u16, control: u8, data: u8) -> (u8) {
+        println!("RAM ROM Computer tick starting");
+
+        // tick the parts
+        let (_, new_data) = self.rom.tick(address, data, control == 1);
+        let (_, new_data2) = self.ram.tick(address, data, control == 1, true);
+
+        // map of memory
+        // 0x0000 -> 0x3fff -> RAM (HM62256)
+        // 0x4000 -> 0x7fff -> ROM (At28C256)
+        match address {
+            0x0000..=0x3fff => {
+                self.data_bus = new_data
+            }
+            0x4000 ..=0x7fff => {
+                self.data_bus = new_data2
+            }
+            _ => {}
+        };
+        0
+    }
+}

core/src/computers/rom_only/mod.rs

@@ -1,4 +1,5 @@
 use crate::periph::at28c256::At28C256;
+use crate::periph::backplane::Backplane;
 
 pub mod backplane;
 pub mod new;
@@ -16,8 +17,11 @@ pub struct RomOnlyComputer {
 impl RomOnlyComputer {
     pub fn tick2(&mut self, address: u16, control: u8, data: u8) -> (u8) {
         // tick the parts...
+        println!("WIDETICK: A:${address:04x} D:${data:02x} C:b{control:08b}");
 
         let (_, new_data) = self.rom.tick(address, data, control == 0x01);
+        println!("\nNew Data : {new_data:02x}");
+        self.set_data_bus(new_data);
         new_data
     }
 }