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cli/tests/mod.rs

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+mod ram_rom_tests;
+mod rom_only_test;

cli/tests/ram_rom_tests.rs

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+use core::computers::ram_rom::RamRomComputer;
+use core::traits::backplane::Backplane;
+const RAM_START: u16 = 0x4000;
+const ROM_START: u16 = 0x0000;
+
+#[test]
+fn ram_rom_thintick() {
+    let mut ramrom = RamRomComputer::new();
+
+    ramrom.tick2(0x0001, 1, 0x00);
+    println!("DataBus: {}", ramrom.data_bus());
+    ramrom.tick2(0x4001, 1,0xab);
+    println!("DataBus: {}", ramrom.data_bus());
+    ramrom.tick2(0x4001, 1,0x00);
+    println!("DataBus: {}", ramrom.data_bus());
+}

cli/tests/rom_only_test.rs

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+use core::computers::rom_only::RomOnlyComputer;
+use core::traits::backplane::Backplane;
+
+#[test]
+fn rom_only_widetick_test() {
+    let bytes = include_bytes!("/home/tmerritt/Projects/mos6502/resources/test/periph/at28c256/checksum.bin");
+
+    let mut rom_only = RomOnlyComputer::program((&bytes[..]).to_vec());
+
+    rom_only.tick2(0x05, 0x00, 0x00);
+    assert_eq!(rom_only.data_bus(), 0x05);
+    assert_eq!(rom_only.address_bus(), 0x05);
+
+    rom_only.tick2(0x07, 0x00, 0x00);
+    assert_eq!(rom_only.data_bus(), 0x07);
+    assert_eq!(rom_only.address_bus(), 0x07);
+
+    rom_only.tick2(0x09, 0x00, 0x00);
+    assert_eq!(rom_only.data_bus(), 0x09);
+    assert_eq!(rom_only.address_bus(), 0x09);
+}
+
+#[test]
+fn rom_only_thintick_test() {
+    let bytes = include_bytes!("/home/tmerritt/Projects/mos6502/resources/test/periph/at28c256/checksum.bin");
+
+    let mut rom_only = RomOnlyComputer::program((&bytes[..]).to_vec());
+
+    rom_only.set_read_mode(true);
+    rom_only.set_address_bus(0x05);
+    rom_only.tick();
+
+    assert_eq!(rom_only.data_bus(), 0x05);
+    assert_eq!(rom_only.address_bus(), 0x05);
+
+    rom_only.set_read_mode(true);
+    rom_only.set_address_bus(0x07);
+    rom_only.tick();
+
+    assert_eq!(rom_only.data_bus(), 0x07);
+    assert_eq!(rom_only.address_bus(), 0x07);
+}