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This commit is contained in:
Trevor Merritt
2025-08-02 11:17:23 -04:00
parent 7ac8bd86ba
commit c4e1f233ae
98 changed files with 2908 additions and 2270 deletions
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core/src/computers/beneater/mod.rs
+11 -1
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@@ -1,7 +1,17 @@
mod backplane;
use crate::mos6502cpu::Mos6502Cpu;
use crate::periph::mos6522::mos6522::Mos6522;
use crate::periph::mos6522::Mos6522;
/*
SBC Designed by Ben Eater
0x0000 -> 0x3fff -> RAM (16KB)
0x4000 -> 0x5fff -> UNUSED
0x6000 -> 0x600f -> VIA
0x6010 -> 0x7fff -> UNUSED
0x8000 -> 0xffff -> ROM (32KB)
*/
pub struct BenEater {
cpu: Mos6502Cpu,
core/src/computers/kim1/mod.rs
+1 -1
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@@ -5,7 +5,7 @@ pub mod reset;
use crate::mos6502cpu::Mos6502Cpu;
use crate::periph::hm62256::Hm62256;
use crate::periph::kim1_keypad::Kim1Keypad;
use crate::periph::mos6530::mos6530::Mos6530;
use crate::periph::mos6530::Mos6530;
/// Represents a KIM-1
///
core/src/computers/kim1/new.rs
+3 -3
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@@ -1,7 +1,7 @@
use crate::computers::kim1::Kim1;
use crate::periph::hm62256::Hm62256;
use crate::periph::kim1_keypad::Kim1Keypad;
use crate::periph::mos6530::mos6530::Mos6530;
use crate::periph::mos6530::Mos6530;
impl Kim1 {
pub fn dump(&self) {
@@ -13,8 +13,8 @@ impl Kim1 {
}
pub fn new() -> Self {
let rriot1_rom = include_bytes!("/home/tmerritt/Projects/mos6502/resources/kim1/6530-002_fillerbyte00-0x1c00.bin");
let rriot2_rom = include_bytes!("/home/tmerritt/Projects/mos6502/resources/kim1/6530-003_fillerbyte00-0x1800.bin");
let rriot1_rom = include_bytes!("/home/tmerritt/Projects/mos6502/resources/pia/6530-002_fillerbyte00-0x1c00.bin");
let rriot2_rom = include_bytes!("/home/tmerritt/Projects/mos6502/resources/pia/6530-003_fillerbyte00-0x1800.bin");
Self {
cpu: Default::default(),
core/src/computers/kim1/reset.rs
+3 -3
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@@ -1,11 +1,11 @@
use crate::computers::kim1::Kim1;
use crate::periph::hm62256::Hm62256;
use crate::periph::mos6530::mos6530::Mos6530;
use crate::periph::mos6530::Mos6530;
impl Kim1 {
pub fn reset(&mut self) {
let rriot1_rom = include_bytes!("/home/tmerritt/Projects/mos6502/resources/kim1/6530-002_fillerbyte00-0x1c00.bin");
let rriot2_rom = include_bytes!("/home/tmerritt/Projects/mos6502/resources/kim1/6530-003_fillerbyte00-0x1800.bin");
let rriot1_rom = include_bytes!("/home/tmerritt/Projects/mos6502/resources/pia/6530-002_fillerbyte00-0x1c00.bin");
let rriot2_rom = include_bytes!("/home/tmerritt/Projects/mos6502/resources/pia/6530-003_fillerbyte00-0x1800.bin");
self.cpu = Default::default();
self.rriot1 = Mos6530::new(0x1700, 0x1780, 0x1800, rriot1_rom.as_array().unwrap());
self.rriot2 = Mos6530::new(0x1740, 0x17c0, 0x1c00, rriot2_rom.as_array().unwrap());
core/src/computers/mod.rs
+1
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@@ -3,3 +3,4 @@ pub mod rom_only;
pub mod kim1;
pub mod ram_rom;
pub mod tim1;
pub mod single_breadboard;
core/src/computers/ram_rom/backplane.rs
-1
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@@ -69,4 +69,3 @@ impl Backplane for RamRomComputer {
(0, false, false)
}
}
core/src/computers/ram_rom/mod.rs
+1 -1
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@@ -4,7 +4,7 @@ use crate::periph::hm62256::Hm62256;
pub mod backplane;
pub mod program_rom;
pub mod new;
mod tick2;
pub mod tick2;
pub struct RamRomComputer {
pub(crate) rom: At28C256,
core/src/computers/ram_rom/tick2.rs
+11 -19
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@@ -1,6 +1,5 @@
use std::collections::BTreeMap;
use crate::computers::ram_rom::RamRomComputer;
use crate::traits::bus_device::BusDevice;
use crate::traits::backplane::Backplane;
struct ChipSignals {
cs: bool,
@@ -14,21 +13,8 @@ enum RomRamChips {
}
impl RamRomComputer {
pub fn signal_tick(&mut self, address: u16, data: u8) {
println!("⏲️RAM ROM COMPUTER SIGNAL TICK");
// no CPU to tick.
let mut ram_state = ChipSignals { oe: false, we: false, cs: false};
let mut rom_state = ChipSignals { oe: false, we: false, cs: false};
// Tick the RAM
// Tick the ROM
}
pub fn tick2(&mut self, address: u16, control: u8, data: u8) -> (u8) {
println!("RAM ROM Computer tick starting / {address:04x} {control:08b} {data:02x}");
println!("⏲RAM ROM Computer tick starting / {address:04x} {control:08b} {data:02x}");
// tick the parts
@@ -37,10 +23,16 @@ impl RamRomComputer {
// 0x4000 -> 0x7fff -> ROM (At28C256)
match address {
0x0000..=0x3fff => {
println!("__DATA TARGETTING ROM BEING STORED ON DATA BUS");
if self.read_mode {
println!("⏲__ROM BEING READ FROM");
let new_data = self.rom.signal_tick(address, data, true, true, true);
self.set_data_bus(new_data);
} else {
panic!("UNABLE TO WRITE TO ROM");
}
}
0x4000 ..=0x7fff => {
println!("__DATA TARGETTING RRAAMM GETTING STORED ON DATA BUS");
println!("⏲__DATA TARGETTING RRAAMM GETTING STORED ON DATA BUS");
}
_ => {}
};
@@ -48,4 +40,4 @@ impl RamRomComputer {
let (_, ram_data_bus) = self.ram.tick(address, data, control == 1, true);
0
}
}
}
core/src/computers/rom_only/debug_memory.rs
+1 -2
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@@ -7,7 +7,6 @@ impl RomOnlyComputer {
for index in 0..size {
println!("Index {index} for {}", index + start_offset);
}
data
}
}
}
core/src/computers/rom_only/mod.rs
+6 -4
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@@ -8,16 +8,18 @@ pub mod debug_memory;
mod rom_chunks;
pub struct RomOnlyComputer {
pub(crate) rom: At28C256,
pub(crate) data_bus: u8,
pub(crate) address_bus: u16,
pub(crate) read_mode: bool,
pub rom: At28C256,
pub data_bus: u8,
pub address_bus: u16,
pub read_mode: bool,
}
impl RomOnlyComputer {
pub fn tick2(&mut self, address: u16, control: u8, data: u8) -> (u8) {
// tick the parts...
println!("WIDETICK: A:${address:04x} D:${data:02x} C:b{control:08b}");
self.address_bus = address;
self.data_bus = data;
let new_data = self.rom.signal_tick(self.address_bus, self.data_bus, true, true, true);
println!("\nNew Data : {new_data:02x}");
core/src/computers/rom_only/new.rs
-1
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@@ -9,5 +9,4 @@ impl RomOnlyComputer {
}
RomOnlyComputer::program(working)
}
}
core/src/computers/single_breadboard/README
+3
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@@ -0,0 +1,3 @@
Computer at
https://www.youtube.com/watch?v=s3t2QMukBRs
https://github.com/AndersBNielsen/6507SBC
core/src/computers/single_breadboard/mod.rs
+20
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@@ -0,0 +1,20 @@
use crate::constants::constants_system::SIZE_32KB;
use crate::mos6502cpu::Mos6502Cpu;
use crate::periph::at28c256::At28C256;
use crate::periph::mos6532::Mos6532;
pub struct SingleBreadboard {
pub cpu: Mos6502Cpu,
pub ram: At28C256,
pub via: Mos6532
}
impl SingleBreadboard {
pub fn new() -> Self {
SingleBreadboard {
cpu: Mos6502Cpu::default(),
ram: At28C256::new(0xf000, 0xffff, vec![0x00; SIZE_32KB]),
via: Mos6532::new(0x0000, 0x0080)
}
}
}
core/src/computers/tim1/backplane.rs
+46
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@@ -0,0 +1,46 @@
use std::net::IpAddr::V4;
use log::debug;
use crate::computers::tim1::Tim1;
use crate::traits::backplane::Backplane;
impl Backplane for Tim1 {
fn data_bus(&self) -> u8 { self.data_bus }
fn address_bus(&self) -> u16 { self.address_bus }
fn read_mode(&self) -> bool { self.read_mode }
fn set_read_mode(&mut self, new_mode: bool) {
self.read_mode = new_mode
}
fn set_data_bus(&mut self, new_value: u8) {
self.data_bus = new_value
}
fn set_address_bus(&mut self, new_value: u16) {
self.address_bus = new_value
}
fn tick(&mut self) {
println!("Starting tick for TIM-1");
}
fn tick_ram(&mut self, address: u16, data: u8, cs: bool, oe: bool, we: bool) -> u8 {
debug!("No dedicated RAM. Its in the VIA");
0x00
}
fn tick_rom(&mut self, address: u16, cs: bool, oe: bool) -> u8 {
debug!("No dedicated ROM. Its in the VIA");
0x00
}
fn tick_via(&mut self, address: u16, data: u8, cs0: bool, cs1: bool, rw: bool, rs0: bool, rs1: bool) -> (u8, bool, bool) {
debug!("Starting VIA Tick");
self.pia.tick(address, data, false, self.read_mode);
// is this for the ROM?
// is this for the RAM?
// is this for the Interrupts?
// is this for the Timers?
(0x00, false, false)
}
}
core/src/computers/tim1/mod.rs
+7 -2
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@@ -1,8 +1,13 @@
mod backplane;
use crate::mos6502cpu::Mos6502Cpu;
use crate::periph::mos6530::mos6530::Mos6530;
use crate::periph::mos6530::Mos6530;
pub struct Tim1 {
cpu: Mos6502Cpu,
pia: Mos6530
pia: Mos6530,
read_mode: bool,
data_bus: u8,
address_bus: u16
}