From cad8d5eaa383114d396938600baff657c9ecc148 Mon Sep 17 00:00:00 2001
From: Trevor Merritt <trevor.merritt@gmail.com>
Date: Thu, 17 Jul 2025 08:56:01 -0400
Subject: [PATCH] fixes address mode of instructions for BCC, BCS, TYA

---
 core/src/instruction.rs       | 16 ++++++++--------
 core/src/instruction_table.rs |  2 +-
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/core/src/instruction.rs b/core/src/instruction.rs
index 7813a67..54e2f24 100644
--- a/core/src/instruction.rs
+++ b/core/src/instruction.rs
@@ -245,7 +245,7 @@ mod test {
                 vec![0x10, 0xab],
                 Instruction {
                     op: BPL,
-                    mode: Implied,
+                    mode: Immediate,
                     operand: Operand::Byte(0xab),
                 },
             ),
@@ -253,7 +253,7 @@ mod test {
                 vec![0x30, 0xab],
                 Instruction {
                     op: BMI,
-                    mode: Implied,
+                    mode: Immediate,
                     operand: Operand::Byte(0xab),
                 },
             ),
@@ -261,7 +261,7 @@ mod test {
                 vec![0x50, 0xab],
                 Instruction {
                     op: BVC,
-                    mode: Implied,
+                    mode: Immediate,
                     operand: Operand::Byte(0xab),
                 },
             ),
@@ -269,7 +269,7 @@ mod test {
                 vec![0x70, 0xab],
                 Instruction {
                     op: BVS,
-                    mode: Implied,
+                    mode: Immediate,
                     operand: Operand::Byte(0xab),
                 },
             ),
@@ -277,7 +277,7 @@ mod test {
                 vec![0x90, 0xab],
                 Instruction {
                     op: BCC,
-                    mode: Implied,
+                    mode: Immediate,
                     operand: Operand::Byte(0xab),
                 },
             ),
@@ -285,7 +285,7 @@ mod test {
                 vec![0xb0, 0xab],
                 Instruction {
                     op: BCS,
-                    mode: Implied,
+                    mode: Immediate,
                     operand: Operand::Byte(0xab),
                 },
             ),
@@ -293,7 +293,7 @@ mod test {
                 vec![0xd0, 0xab],
                 Instruction {
                     op: BNE,
-                    mode: Implied,
+                    mode: Immediate,
                     operand: Operand::Byte(0xab),
                 },
             ),
@@ -301,7 +301,7 @@ mod test {
                 vec![0xf0, 0xab],
                 Instruction {
                     op: BEQ,
-                    mode: Implied,
+                    mode: Immediate,
                     operand: Operand::Byte(0xab),
                 },
             ),
diff --git a/core/src/instruction_table.rs b/core/src/instruction_table.rs
index 9f46684..f1dff83 100644
--- a/core/src/instruction_table.rs
+++ b/core/src/instruction_table.rs
@@ -215,7 +215,7 @@ pub const INSTRUCTION_TABLE: [Option<OpInfo>; 256] = {
 
     table[ISA_OP_BCC as usize] = Some(OpInfo {
         operation: BCC,
-        mode: AddressMode::Implied,
+        mode: AddressMode::Immediate,
         length: 2,
         cycles: 2,
         format_prefix: "BCC $",