From f9c938757f80771a51b4a9fd54b8a700f49a6957 Mon Sep 17 00:00:00 2001 From: Trevor Merritt Date: Tue, 1 Jul 2025 13:08:23 -0400 Subject: [PATCH] box swap --- core/src/address_mode.rs | 61 +++ core/src/instruction.rs | 39 +- core/src/mos6502flags.rs | 35 +- core/src/op_info.rs | 4 + core/src/operation.rs | 1072 ++++++++------------------------------ 5 files changed, 325 insertions(+), 886 deletions(-) diff --git a/core/src/address_mode.rs b/core/src/address_mode.rs index 9062aa1..f2d8c55 100644 --- a/core/src/address_mode.rs +++ b/core/src/address_mode.rs @@ -1,16 +1,77 @@ +/// Represents the various addressing modes of the 6502 CPU. #[derive(PartialEq, Debug, Copy, Clone)] pub enum AddressMode { + /// Implied + /// + /// No operand is needed; the instruction implicitly operates on a register or flag. + /// Example: `CLC` (Clear Carry Flag) Implied, + + /// Accumulator + /// + /// Operates directly on the accumulator register. + /// Example: `ASL A` (Arithmetic Shift Left on Accumulator) Accumulator, + + /// Immediate + /// + /// Operand is a constant 8-bit value. + /// Example: `LDA #$01` loads the value 0x01 into the accumulator. Immediate, + + /// Zero Page + /// + /// Operand is an address in the first 256 bytes of memory (0x0000–0x00FF). + /// Example: `LDA $10` reads from address 0x0010. ZeroPage, + + /// Zero Page X + /// + /// Zero page address offset by the X register. + /// Example: If X = 0x10, `LDA $23,X` reads from 0x33. ZeroPageX, + + /// Zero Page Y + /// + /// Zero page address offset by the Y register. + /// Used only by a few instructions like `LDX` and `STX`. + /// Example: If Y = 0x10, `LDX $23,Y` reads from 0x33. ZeroPageY, + + /// Absolute + /// + /// Full 16-bit address is provided as the operand. + /// Example: `LDA $1234` reads from address 0x1234. Absolute, + + /// Absolute X + /// + /// Absolute address offset by the X register. + /// Example: If X = 0x10, `LDA $1234,X` reads from 0x1244. AbsoluteX, + + /// Absolute Y + /// + /// Absolute address offset by the Y register. + /// Example: If Y = 0x10, `LDA $1234,Y` reads from 0x1244. AbsoluteY, + + /// Indirect + /// + /// Only used by `JMP`. Operand is a 16-bit address pointing to another 16-bit address. + /// Example: `JMP ($1234)` jumps to the address stored at 0x1234/0x1235. Indirect, + + /// Indirect X (Indexed Indirect) + /// + /// Operand is a zero-page address. Add X to it, then fetch the 16-bit address from that location. + /// Example: If X = 0x04 and operand = $20, `LDA ($20,X)` reads from the address at $24/$25. IndirectX, + + /// Indirect Y (Indirect Indexed) + /// + /// Operand is a zero-page address. Fetch the 16-bit address from that location, then add Y. + /// Example: If Y = 0x10 and ($20) = $3000, `LDA ($20),Y` reads from $3010. IndirectY, } diff --git a/core/src/instruction.rs b/core/src/instruction.rs index 7b87356..38b8a9d 100644 --- a/core/src/instruction.rs +++ b/core/src/instruction.rs @@ -1,11 +1,12 @@ +use log::trace; use crate::address_mode::AddressMode; use crate::address_mode::AddressMode::*; -use crate::address_mode::AddressMode::{Absolute, AbsoluteX, AbsoluteY, Accumulator, Immediate, Implied, Indirect, IndirectX, IndirectY, ZeroPage, ZeroPageX}; +use crate::address_mode::AddressMode::*; use crate::instruction_table::INSTRUCTION_TABLE; use crate::op_info::OpInfo; use crate::operand::Operand; use crate::operation::Operation; -use crate::operation::Operation::{ADC, AND, ASL, BCC, BCS, BEQ, BIT, BMI, BNE, BPL, BRK, BVC, BVS, CLC, CLD, CLI, CLV, CMP, CPX, CPY, DEC, DEX, DEY, EOR, INC, INX, JMP, JSR, LDA, LDX, LDY, NOP, ORA, PHA, PHP, PLA, PLP, ROL, ROR, RTI, RTS, SBC, SEC, SED, SEI, STA, STX, STY, TAX, TAY, TSX, TXA, TXS, TYA}; +use crate::operation::Operation::*; #[derive(Debug, PartialEq)] pub struct Instruction { @@ -16,32 +17,28 @@ pub struct Instruction { impl Instruction { pub fn opinfo(bytes: &[u8]) -> Option { - println!("DECODING : {bytes:?}"); + trace!("DECODING : {bytes:?}"); let opcode = bytes.get(0).copied()?; Some(INSTRUCTION_TABLE[opcode as usize])? } pub fn decode(bytes: &[u8]) -> Option { - let info = Instruction::opinfo(bytes).unwrap(); + let info = Instruction::opinfo(bytes)?; + let operand = match info.length { - 2 => Operand::Byte(bytes.get(1).copied()?), - 3 => { - let lo = *bytes.get(1)?; - let hi = *bytes.get(2)?; - Operand::Word(u16::from_le_bytes([lo, hi])) - } - _ => Operand::None, - }; + 2 => Operand::Byte(*bytes.get(1)?), + 3 => Operand::Word(u16::from_le_bytes([*bytes.get(1)?, *bytes.get(2)?])), + _ => Operand::None, + }; - let return_value = Some(Instruction { - op: info.operation, - mode: info.mode, - operand, - }); + let instruction = Instruction { + op: info.operation, + mode: info.mode, + operand, + }; - println!("RETURNING: {:?}", return_value); - - return_value + trace!("RETURNING: {:?}", instruction); + Some(instruction) } } @@ -50,7 +47,7 @@ impl Instruction { mod test { use crate::address_mode::AddressMode::*; use crate::instruction::Instruction; - use crate::operation::Operation::{ADC, INY, LSR}; + use crate::operation::Operation::*; use super::*; #[test] diff --git a/core/src/mos6502flags.rs b/core/src/mos6502flags.rs index 815944b..24d9a6b 100644 --- a/core/src/mos6502flags.rs +++ b/core/src/mos6502flags.rs @@ -1,12 +1,45 @@ +/// Represents the status flags in the 6502 processor's status register (P). +#[derive(Debug, Copy, Clone, PartialEq)] pub enum Mos6502Flag { + /// Carry Flag (C) + /// + /// Set if an arithmetic operation results in a carry out of the most significant bit (for addition), + /// or a borrow (for subtraction). Also used for bit shifts and rotates. Carry, + + /// Zero Flag (Z) + /// + /// Set if the result of an operation is zero. Zero, + + /// Interrupt Disable Flag (I) + /// + /// When set, disables maskable interrupts (IRQ). Interrupt, + + /// Decimal Mode Flag (D) + /// + /// When set, arithmetic operations use Binary-Coded Decimal (BCD) mode. + /// Note: Not supported on all 6502 variants (e.g., not on the NES CPU). Decimal, + + /// Break Command Flag (B) + /// + /// Set when a BRK (break) instruction is executed. + /// Used to distinguish software interrupts from hardware ones. Break, + + /// Overflow Flag (V) + /// + /// Set when an arithmetic operation results in a signed overflow. + /// For example, adding two positive numbers results in a negative. Overflow, - Negative + + /// Negative Flag (N) + /// + /// Set if the result of an operation has bit 7 set (i.e., the result is negative in two's complement). + Negative, } #[derive(Default)] diff --git a/core/src/op_info.rs b/core/src/op_info.rs index 10f80f8..0626d04 100644 --- a/core/src/op_info.rs +++ b/core/src/op_info.rs @@ -3,8 +3,12 @@ use crate::operation::Operation; #[derive(Debug, Copy, Clone)] pub struct OpInfo { + /// What is the operation pub operation: Operation, + /// How does this operation access memory pub mode: AddressMode, + /// Bytes to represent the instruction and parameters pub length: u8, + /// CPU Cycles to complete the instruction pub cycles: u8, } diff --git a/core/src/operation.rs b/core/src/operation.rs index 49d43ed..1d420ad 100644 --- a/core/src/operation.rs +++ b/core/src/operation.rs @@ -1,1012 +1,356 @@ - +/// Represents all official 6502 CPU instructions. #[derive(Clone, Copy, Debug, PartialEq)] pub enum Operation { - /// ADC – Add with Carry - /// A,Z,C,N = A+M+C + /// Add with Carry /// - /// This instruction adds the contents of a memory location to the accumulator together with the carry bit. If overflow occurs the carry bit is set, this enables multiple byte addition to be performed. + /// Affects flags: N, V, Z, C /// - /// Processor Status after use: - /// - /// C Carry Flag Set if overflow in bit 7 - /// Z Zero Flag Set if A = 0 - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Set if sign bit is incorrect - /// N Negative Flag Set if bit 7 set - /// - /// Addressing Mode Opcode Bytes Cycles - /// Immediate $69 2 2 - /// Zero Page $65 2 3 - /// Zero Page,X $75 2 4 - /// Absolute $6D 3 4 - /// Absolute,X $7D 3 4 (+1 if page crossed) - /// Absolute,Y $79 3 4 (+1 if page crossed) - /// (Indirect,X) $61 2 6 - /// (Indirect),Y $71 2 5 (+1 if page crossed) + /// Addressing Modes: Immediate, ZeroPage, ZeroPageX, Absolute, AbsoluteX, AbsoluteY, IndirectX, IndirectY ADC, - /// AND - /// A,Z,N = A&M + + /// Logical AND with Accumulator /// - /// A logical AND is performed, bit by bit, on the accumulator contents using the contents of a byte of memory. - /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Set if A = 0 - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 set - /// - /// Addressing Mode Opcode Bytes Cycles - /// Immediate $29 2 2 - /// ZeroPage $25 2 3 - /// ZeroPage,X $35 2 4 - /// Absolute $2D 3 4 - /// Absolute,X $3D 3 4 (+1 if page crossed) - /// Absolute,Y $39 3 4 (+1 if page crossed) - /// (Indirect,X) $21 2 6 - /// (Indirect),Y $31 2 5 (+1 if page crossed) + /// Affects flags: N, Z /// + /// Addressing Modes: Immediate, ZeroPage, ZeroPageX, Absolute, AbsoluteX, AbsoluteY, IndirectX, IndirectY AND, - /// ASL - /// A,Z,C,N = M*2 or M,Z,C,N = M*2 + + /// Arithmetic Shift Left /// - /// This operation shifts all the bits of the accumulator or memory contents one bit left. Bit 0 is set to 0 and bit 7 is placed in the carry flag. The effect of this operation is to multiply the memory contents by 2 (ignoring 2’s complement considerations), setting the carry if the result will not fit in 8 bits. + /// Affects flags: N, Z, C /// - /// Processor Status after use: - /// - /// C Carry Flag Set to contents of old bit 7 - /// Z Zero Flag Set if A = 0 - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of the result is set - /// - /// Addressing Mode Opcode Bytes Cycles - /// Accumulator $0A 1 2 - /// ZeroPage $06 2 5 - /// ZeroPage,X $16 2 6 - /// Absolute $0E 3 6 - /// Absolute,X $1E 3 7 + /// Addressing Modes: Accumulator, ZeroPage, ZeroPageX, Absolute, AbsoluteX ASL, - /// BCC – Branch if Carry Clear - /// If the carry flag is clear then add the relative displacement to the program counter to cause a branch to a new location. - /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Relative $90 2 2 (+1 if branch succeeds - /// - /// +2 if to a new page) + /// Branch if Carry Clear + /// + /// Addressing Modes: Relative BCC, - /// BCS – Branch if Carry Set - /// If the carry flag is set then add the relative displacement to the program counter to cause a branch to a new location. - /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// - /// Addressing Mode Opcode Bytes Cycles - /// Relative $B0 2 2 (+1 if branch succeeds - /// - /// +2 if to a new page) + /// Branch if Carry Set + /// + /// Addressing Modes: Relative BCS, - /// BEQ – Branch if Equal - /// If the zero flag is set then add the relative displacement to the program counter to cause a branch to a new location. + + /// Branch if Equal (Zero Set) /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Relative $F0 2 2 (+1 if branch succeeds - /// - /// +2 if to a new page) + /// Addressing Modes: Relative BEQ, - /// BIT – Bit Test - /// A & M, N = M7, V = M6 + + /// Bit Test /// - /// This instructions is used to test if one or more bits are set in a target memory location. The mask pattern in A is ANDed with the value in memory to set or clear the zero flag, but the result is not kept. Bits 7 and 6 of the value from memory are copied into the N and V flags. + /// Affects flags: N, V, Z /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Set if the result if the AND is zero - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Set to bit 6 of the memory value - /// N Negative Flag Set to bit 7 of the memory value - /// Addressing Mode Opcode Bytes Cycles - /// ZeroPage $24 2 3 - /// Absolute $2C 3 4 + /// Addressing Modes: ZeroPage, Absolute BIT, - /// BMI – Branch if Minus - /// If the negative flag is set then add the relative displacement to the program counter to cause a branch to a new location. + + /// Branch if Minus (Negative Set) /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Relative $30 2 2 (+1 if branch succeeds - /// - /// +2 if to a new page) + /// Addressing Modes: Relative BMI, - /// BNE – Branch if Not Equal - /// If the zero flag is clear then add the relative displacement to the program counter to cause a branch to a new location. + + /// Branch if Not Equal (Zero Clear) /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Relative $D0 2 2 (+1 if branch succeeds - /// - /// +2 if to a new page) + /// Addressing Modes: Relative BNE, - /// BPL – Branch if Positive - /// If the negative flag is clear then add the relative displacement to the program counter to cause a branch to a new location. + + /// Branch if Positive (Negative Clear) /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Relative $10 2 2 (+1 if branch succeeds - /// - /// +2 if to a new page) + /// Addressing Modes: Relative BPL, - /// BRK – Force Interrupt - /// The BRK instruction forces the generation of an interrupt request. The program counter and processor status are pushed on the stack then the IRQ interrupt vector at $FFFE/F is loaded into the PC and the break flag in the status set to one. + + /// Force Interrupt /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Set to 1 - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Implied $00 1 7 + /// Affects flags: B + /// + /// Addressing Modes: Implied BRK, - /// BVC – Branch if Overflow Clear - /// If the overflow flag is clear then add the relative displacement - /// to the program counter to cause a branch to a new location. + + /// Branch if Overflow Clear /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Relative $50 2 2 (+1 if branch succeeds - /// - /// +2 if to a new page) + /// Addressing Modes: Relative BVC, - /// BVS – Branch if Overflow Set - /// If the overflow flag is set then add the relative displacement to the program counter to cause a branch to a new location. + + /// Branch if Overflow Set /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Relative $70 2 2 (+1 if branch succeeds - /// - /// +2 if to a new page) + /// Addressing Modes: Relative BVS, - /// CLC – Clear Carry Flag - /// C = 0 + + /// Clear Carry Flag /// - /// Set the carry flag to zero. + /// Affects flags: C /// - /// C Carry Flag Set to 0 - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Implied $18 1 2 + /// Addressing Modes: Implied CLC, - /// CLD – Clear Decimal Mode - /// D = 0 + + /// Clear Decimal Mode /// - /// Sets the decimal mode flag to zero. + /// Affects flags: D /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Set to 0 - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Implied $D8 1 2 + /// Addressing Modes: Implied CLD, - /// CLI – Clear Interrupt Disable - /// I = 0 + + /// Clear Interrupt Disable /// - /// Clears the interrupt disable flag allowing normal interrupt - /// requests to be serviced. + /// Affects flags: I /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Set to 0 - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Implied $58 1 2 + /// Addressing Modes: Implied CLI, - /// CLV – Clear Overflow Flag - /// V = 0 + + /// Clear Overflow Flag /// - /// Clears the overflow flag. + /// Affects flags: V /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Set to 0 - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Implied $B8 1 2 + /// Addressing Modes: Implied CLV, - /// CMP – Compare - /// Z,C,N = A-M + + /// Compare Accumulator /// - /// This instruction compares the contents of the accumulator with another memory held value and sets the zero and carry flags as appropriate. + /// Affects flags: N, Z, C /// - /// Processor Status after use: - /// - /// C Carry Flag Set if A >= M - /// Z Zero Flag Set if A = M - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of the result is set - /// Addressing Mode Opcode Bytes Cycles - /// Immediate $C9 2 2 - /// Zero Page $C5 2 3 - /// Zero Page,X $D5 2 4 - /// Absolute $CD 3 4 - /// Absolute,X $DD 3 4 (+1 if page crossed) - /// Absolute,Y $D9 3 4 (+1 if page crossed) - /// (Indirect,X) $C1 2 6 - /// (Indirect),Y $D1 2 5 (+1 if page crossed) + /// Addressing Modes: Immediate, ZeroPage, ZeroPageX, Absolute, AbsoluteX, AbsoluteY, IndirectX, IndirectY CMP, - /// CPX – Compare X Register - /// Z,C,N = X-M + + /// Compare X Register /// - /// This instruction compares the contents of the X register with another memory held value and sets the zero and carry flags as appropriate. + /// Affects flags: N, Z, C /// - /// Processor Status after use: - /// - /// C Carry Flag Set if X >= M - /// Z Zero Flag Set if X = M - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of the result is set - /// Addressing Mode Opcode Bytes Cycles - /// Immediate $E0 2 2 - /// Zero Page $E4 2 3 - /// Absolute $EC 3 4 + /// Addressing Modes: Immediate, ZeroPage, Absolute CPX, - /// CPY – Compare Y Register - /// Z,C,N = Y-M + + /// Compare Y Register /// - /// This instruction compares the contents of the Y register with another memory held value and sets the zero and carry flags as appropriate. + /// Affects flags: N, Z, C /// - /// Processor Status after use: - /// - /// C Carry Flag Set if Y >= M - /// Z Zero Flag Set if Y = M - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of the result is set - /// Addressing Mode Opcode Bytes Cycles - /// Immediate $C0 2 2 - /// Zero Page $C4 2 3 - /// Absolute $CC 3 4 + /// Addressing Modes: Immediate, ZeroPage, Absolute CPY, - /// DEC – Decrement Memory - /// M,Z,N = M-1 + + /// Decrement Memory /// - /// Subtracts one from the value held at a specified memory location setting the zero and negative flags as appropriate. + /// Affects flags: N, Z /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Set if result is zero - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of the result is set - /// Addressing Mode Opcode Bytes Cycles - /// Zero Page $C6 2 5 - /// Zero Page,X $D6 2 6 - /// Absolute $CE 3 6 - /// Absolute,X $DE 3 7 + /// Addressing Modes: ZeroPage, ZeroPageX, Absolute, AbsoluteX DEC, - /// DEX – Decrement X Register - /// X,Z,N = X-1 + + /// Decrement X Register /// - /// Subtracts one from the X register setting the zero and negative flags as appropriate. + /// Affects flags: N, Z /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Set if X is zero - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of X is set - /// Addressing Mode Opcode Bytes Cycles - /// Implied $CA 1 2 + /// Addressing Modes: Implied DEX, - /// DEY – Decrement Y Register - /// Y,Z,N = Y-1 + + /// Decrement Y Register /// - /// Subtracts one from the Y register setting the zero and negative flags as appropriate. + /// Affects flags: N, Z /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Set if Y is zero - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of Y is set - /// Addressing Mode Opcode Bytes Cycles - /// Implied $88 1 2 + /// Addressing Modes: Implied DEY, - /// EOR – Exclusive OR - /// A,Z,N = A^M + + /// Exclusive OR with Accumulator /// - /// An exclusive OR is performed, bit by bit, on the accumulator contents using the contents of a byte of memory. + /// Affects flags: N, Z /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Set if A = 0 - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 set - /// Addressing Mode Opcode Bytes Cycles - /// Immediate $49 2 2 - /// ZeroPage $45 2 3 - /// ZeroPage,X $55 2 4 - /// Absolute $4D 3 4 - /// Absolute,X $5D 3 4 (+1 if page crossed) - /// Absolute,Y $59 3 4 (+1 if page crossed) - /// (Indirect,X) $41 2 6 - /// (Indirect),Y $51 2 5 (+1 if page crossed) + /// Addressing Modes: Immediate, ZeroPage, ZeroPageX, Absolute, AbsoluteX, AbsoluteY, IndirectX, IndirectY EOR, - /// INC – Increment Memory - /// M,Z,N = M+1 + + /// Increment Memory /// - /// Adds one to the value held at a specified memory location setting the zero and negative flags as appropriate. + /// Affects flags: N, Z /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Set if result is zero - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of the result is set - /// Addressing Mode Opcode Bytes Cycles - /// Zero Page $E6 2 5 - /// Zero Page,X $F6 2 6 - /// Absolute $EE 3 6 - /// Absolute,X $FE 3 7 + /// Addressing Modes: ZeroPage, ZeroPageX, Absolute, AbsoluteX INC, - /// INX – Increment X Register - /// X,Z,N = X+1 + + /// Increment X Register /// - /// Adds one to the X register setting the zero and negative flags as appropriate. + /// Affects flags: N, Z /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Set if X is zero - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of X is set - /// Addressing Mode Opcode Bytes Cycles - /// Implied $E8 1 2 + /// Addressing Modes: Implied INX, - /// INY – Increment Y Register - /// Y,Z,N = Y+1 + + /// Increment Y Register /// - /// Adds one to the Y register setting the zero and negative flags as appropriate. + /// Affects flags: N, Z /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Set if Y is zero - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of Y is set - /// Addressing Mode Opcode Bytes Cycles - /// Implied $C8 1 2 + /// Addressing Modes: Implied INY, - /// JMP – Jump - /// Sets the program counter to the address specified by the operand. + + /// Jump to Address /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Absolute $4C 3 3 - /// Indirect $6C 3 5 + /// Addressing Modes: Absolute, Indirect JMP, - /// JSR – Jump to Subroutine - /// The JSR instruction pushes the address (minus one) of the return point on to the stack and then sets the program counter to the target memory address. + + /// Jump to Subroutine /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Absolute $20 3 6 + /// Addressing Modes: Absolute JSR, - /// LDA – Load Accumulator - /// A,Z,N = M + + /// Load Accumulator /// - /// Loads a byte of memory into the accumulator setting the zero and negative flags as appropriate. + /// Affects flags: N, Z /// - /// C Carry Flag Not affected - /// Z Zero Flag Set if A = 0 - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of A is set - /// Addressing Mode Opcode Bytes Cycles - /// Immediate $A9 2 2 - /// Zero Page $A5 2 3 - /// Zero Page,X $B5 2 4 - /// Absolute $AD 3 4 - /// Absolute,X $BD 3 4 (+1 if page crossed) - /// Absolute,Y $B9 3 4 (+1 if page crossed) - /// (Indirect,X) $A1 2 6 - /// (Indirect),Y $B1 2 5 (+1 if page crossed) + /// Addressing Modes: Immediate, ZeroPage, ZeroPageX, Absolute, AbsoluteX, AbsoluteY, IndirectX, IndirectY LDA, - /// LDX – Load X Register - /// X,Z,N = M + + /// Load X Register /// - /// Loads a byte of memory into the X register setting the zero and negative flags as appropriate. + /// Affects flags: N, Z /// - /// C Carry Flag Not affected - /// Z Zero Flag Set if X = 0 - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of X is set - /// Addressing Mode Opcode Bytes Cycles - /// Immediate $A2 2 2 - /// Zero Page $A6 2 3 - /// Zero Page,Y $B6 2 4 - /// Absolute $AE 3 4 - /// Absolute,Y $BE 3 4 (+1 if page crossed) + /// Addressing Modes: Immediate, ZeroPage, ZeroPageY, Absolute, AbsoluteY LDX, - /// LDY – Load Y Register - /// Y,Z,N = M + + /// Load Y Register /// - /// Loads a byte of memory into the Y register setting the zero and negative flags as appropriate. + /// Affects flags: N, Z /// - /// C Carry Flag Not affected - /// Z Zero Flag Set if Y = 0 - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of Y is set - /// Addressing Mode Opcode Bytes Cycles - /// Immediate $A0 2 2 - /// Zero Page $A4 2 3 - /// Zero Page,X $B4 2 4 - /// Absolute $AC 3 4 - /// Absolute,X $BC 3 4 (+1 if page crossed) + /// Addressing Modes: Immediate, ZeroPage, ZeroPageX, Absolute, AbsoluteX LDY, - /// LSR – Logical Shift Right - /// A,C,Z,N = A/2 or M,C,Z,N = M/2 + + /// Logical Shift Right /// - /// Each of the bits in A or M is shift one place to the right. The bit that was in bit 0 is shifted into the carry flag. Bit 7 is set to zero. + /// Affects flags: N, Z, C /// - /// Processor Status after use: - /// - /// C Carry Flag Set to contents of old bit 0 - /// Z Zero Flag Set if result = 0 - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of the result is set - /// Addressing Mode Opcode Bytes Cycles - /// Accumulator $4A 1 2 - /// ZeroPage $46 2 5 - /// ZeroPage,X $56 2 6 - /// Absolute $4E 3 6 - /// Absolute,X $5E 3 7 + /// Addressing Modes: Accumulator, ZeroPage, ZeroPageX, Absolute, AbsoluteX LSR, - /// NOP – No Operation - /// The NOP instruction causes no changes to the processor other than the normal incrementing of the program counter to the next instruction. + + /// No Operation /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Implied $EA 1 2 + /// Addressing Modes: Implied NOP, - /// ORA – Logical Inclusive OR - /// A,Z,N = A|M + + /// Logical Inclusive OR with Accumulator /// - /// An inclusive OR is performed, bit by bit, on the accumulator contents using the contents of a byte of memory. + /// Affects flags: N, Z /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Set if A = 0 - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 set - /// Addressing Mode Opcode Bytes Cycles - /// Immediate $09 2 2 - /// Zero Page $05 2 3 - /// Zero Page,X $15 2 4 - /// Absolute $0D 3 4 - /// Absolute,X $1D 3 4 (+1 if page crossed) - /// Absolute,Y $19 3 4 (+1 if page crossed) - /// (Indirect,X) $01 2 6 - /// (Indirect),Y $11 2 5 (+1 if page crossed) + /// Addressing Modes: Immediate, ZeroPage, ZeroPageX, Absolute, AbsoluteX, AbsoluteY, IndirectX, IndirectY ORA, - /// PHA – Push Accumulator - /// Pushes a copy of the accumulator on to the stack. + + /// Push Accumulator on Stack /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Implied $48 1 3 + /// Addressing Modes: Implied PHA, - /// PHP – Push Processor Status - /// Pushes a copy of the status flags on to the stack. + + /// Push Processor Status on Stack /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Implied $08 1 3 + /// Addressing Modes: Implied PHP, - /// PLA – Pull Accumulator - /// Pulls an 8 bit value from the stack and into the accumulator. The zero and negative flags are set as appropriate. + + /// Pull Accumulator from Stack /// - /// C Carry Flag Not affected - /// Z Zero Flag Set if A = 0 - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of A is set - /// Addressing Mode Opcode Bytes Cycles - /// Implied $68 1 4 + /// Affects flags: N, Z + /// + /// Addressing Modes: Implied PLA, - /// PLP – Pull Processor Status - /// Pulls an 8 bit value from the stack and into the processor flags. The flags will take on new states as determined by the value pulled. + + /// Pull Processor Status from Stack /// - /// Processor Status after use: - /// - /// C Carry Flag Set from stack - /// Z Zero Flag Set from stack - /// I Interrupt Disable Set from stack - /// D Decimal Mode Flag Set from stack - /// B Break Command Set from stack - /// V Overflow Flag Set from stack - /// N Negative Flag Set from stack - /// Addressing Mode Opcode Bytes Cycles - /// Implied $28 1 4 + /// Addressing Modes: Implied PLP, - /// ROL – Rotate Left - /// Move each of the bits in either A or M one place to the left. Bit 0 is filled with the current value of the carry flag while the old bit 7 becomes the new carry flag value. + + /// Rotate Left /// - /// Processor Status after use: + /// Affects flags: N, Z, C /// - /// C Carry Flag Set to contents of old bit 7 - /// Z Zero Flag Set if A = 0 - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of the result is set - /// Addressing Mode Opcode Bytes Cycles - /// Accumulator $2A 1 2 - /// ZeroPage $26 2 5 - /// ZeroPage,X $36 2 6 - /// Absolute $2E 3 6 - /// Absolute,X $3E 3 7 + /// Addressing Modes: Accumulator, ZeroPage, ZeroPageX, Absolute, AbsoluteX ROL, - /// ROR – Rotate Right - /// Move each of the bits in either A or M one place to the right. Bit 7 is filled with the current value of the carry flag while the old bit 0 becomes the new carry flag value. + + /// Rotate Right /// - /// Processor Status after use: + /// Affects flags: N, Z, C /// - /// C Carry Flag Set to contents of old bit 0 - /// Z Zero Flag Set if A = 0 - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of the result is set - /// Addressing Mode Opcode Bytes Cycles - /// Accumulator $6A 1 2 - /// ZeroPage $66 2 5 - /// ZeroPage,X $76 2 6 - /// Absolute $6E 3 6 - /// Absolute,X $7E 3 7 + /// Addressing Modes: Accumulator, ZeroPage, ZeroPageX, Absolute, AbsoluteX ROR, - /// RTI – Return from Interrupt - /// The RTI instruction is used at the end of an interrupt processing routine. It pulls the processor flags from the stack followed by the program counter. + + /// Return from Interrupt /// - /// Processor Status after use: - /// - /// C Carry Flag Set from stack - /// Z Zero Flag Set from stack - /// I Interrupt Disable Set from stack - /// D Decimal Mode Flag Set from stack - /// B Break Command Set from stack - /// V Overflow Flag Set from stack - /// N Negative Flag Set from stack - /// Addressing Mode Opcode Bytes Cycles - /// Implied $40 1 6 + /// Addressing Modes: Implied RTI, - /// RTS – Return from Subroutine - /// The RTS instruction is used at the end of a subroutine to return to the calling routine. It pulls the program counter (minus one) from the stack. + + /// Return from Subroutine /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Implied $60 1 6 + /// Addressing Modes: Implied RTS, - /// SBC – Subtract with Carry - /// A,Z,C,N = A-M-(1-C) + + /// Subtract with Carry /// - /// This instruction subtracts the contents of a memory location to the accumulator together with the not of the carry bit. If overflow occurs the carry bit is clear, this enables multiple byte subtraction to be performed. + /// Affects flags: N, V, Z, C /// - /// Processor Status after use: - /// - /// C Carry Flag Clear if overflow in bit 7 - /// Z Zero Flag Set if A = 0 - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Set if sign bit is incorrect - /// N Negative Flag Set if bit 7 set - /// Addressing Mode Opcode Bytes Cycles - /// Immediate $E9 2 2 - /// Zero Page $E5 2 3 - /// Zero Page,X $F5 2 4 - /// Absolute $ED 3 4 - /// Absolute,X $FD 3 4 (+1 if page crossed) - /// Absolute,Y $F9 3 4 (+1 if page crossed) - /// (Indirect,X) $E1 2 6 - /// (Indirect),Y $F1 2 5 (+1 if page crossed) + /// Addressing Modes: Immediate, ZeroPage, ZeroPageX, Absolute, AbsoluteX, AbsoluteY, IndirectX, IndirectY SBC, - /// SEC – Set Carry Flag - /// C = 1 + + /// Set Carry Flag /// - /// Set the carry flag to one. + /// Affects flags: C /// - /// C Carry Flag Set to 1 - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Implied $38 1 2 + /// Addressing Modes: Implied SEC, - /// SED – Set Decimal Flag - /// D = 1 + + /// Set Decimal Flag /// - /// Set the decimal mode flag to one. + /// Affects flags: D /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Set to 1 - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Implied $F8 1 2 + /// Addressing Modes: Implied SED, - /// SEI – Set Interrupt Disable - /// I = 1 + + /// Set Interrupt Disable /// - /// Set the interrupt disable flag to one. + /// Affects flags: I /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Set to 1 - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Implied $78 1 2 + /// Addressing Modes: Implied SEI, - /// STA – Store Accumulator - /// M = A + + /// Store Accumulator /// - /// Stores the contents of the accumulator into memory. - /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Zero Page $85 2 3 - /// Zero Page,X $95 2 4 - /// Absolute $8D 3 4 - /// Absolute,X $9D 3 5 - /// Absolute,Y $99 3 5 - /// (Indirect,X) $81 2 6 - /// (Indirect),Y $91 2 6 + /// Addressing Modes: ZeroPage, ZeroPageX, Absolute, AbsoluteX, AbsoluteY, IndirectX, IndirectY STA, - /// STX – Store X Register - /// M = X + + /// Store X Register /// - /// Stores the contents of the X register into memory. - /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Zero Page $86 2 3 - /// Zero Page,Y $96 2 4 - /// Absolute $8E 3 4 + /// Addressing Modes: ZeroPage, ZeroPageY, Absolute STX, - /// STY – Store Y Register - /// M = Y + + /// Store Y Register /// - /// Stores the contents of the Y register into memory. - /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Zero Page $84 2 3 - /// Zero Page,X $94 2 4 - /// Absolute $8C 3 4 + /// Addressing Modes: ZeroPage, ZeroPageX, Absolute STY, - /// TAX – Transfer Accumulator to X - /// X = A + + /// Transfer Accumulator to X /// - /// Copies the current contents of the accumulator into the X register and sets the zero and negative flags as appropriate. + /// Affects flags: N, Z /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Set if X = 0 - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of X is set - /// Addressing Mode Opcode Bytes Cycles - /// Implied $AA 1 2 + /// Addressing Modes: Implied TAX, - /// TAY – Transfer Accumulator to Y - /// Y = A + + /// Transfer Accumulator to Y /// - /// Copies the current contents of the accumulator into the Y register and sets the zero and negative flags as appropriate. + /// Affects flags: N, Z /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Set if Y = 0 - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of Y is set - /// Addressing Mode Opcode Bytes Cycles - /// Implied $A8 1 2 + /// Addressing Modes: Implied TAY, - /// TSX – Transfer Stack Pointer to X - /// X = S + + /// Transfer Stack Pointer to X /// - /// Copies the current contents of the stack register into the X register and sets the zero and negative flags as appropriate. + /// Affects flags: N, Z /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Set if X = 0 - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of X is set - /// Addressing Mode Opcode Bytes Cycles - /// Implied $BA 1 2 + /// Addressing Modes: Implied TSX, - /// TXA – Transfer X to Accumulator - /// A = X + + /// Transfer X to Accumulator /// - /// Copies the current contents of the X register into the accumulator and sets the zero and negative flags as appropriate. + /// Affects flags: N, Z /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Set if A = 0 - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of A is set - /// Addressing Mode Opcode Bytes Cycles - /// Implied $8A 1 + /// Addressing Modes: Implied TXA, - /// TXS – Transfer X to Stack Pointer - /// S = X + + /// Transfer X to Stack Pointer /// - /// Copies the current contents of the X register into the stack register. - /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Not affected - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Not affected - /// Addressing Mode Opcode Bytes Cycles - /// Implied $9A 1 2 + /// Addressing Modes: Implied TXS, - /// TYA – Transfer Y to Accumulator - /// A = Y + + /// Transfer Y to Accumulator /// - /// Copies the current contents of the Y register into the accumulator and sets the zero and negative flags as appropriate. + /// Affects flags: N, Z /// - /// Processor Status after use: - /// - /// C Carry Flag Not affected - /// Z Zero Flag Set if A = 0 - /// I Interrupt Disable Not affected - /// D Decimal Mode Flag Not affected - /// B Break Command Not affected - /// V Overflow Flag Not affected - /// N Negative Flag Set if bit 7 of A is set - /// Addressing Mode Opcode Bytes Cycles - /// Implied $98 1 2 + /// Addressing Modes: Implied TYA, -} + +} \ No newline at end of file