boxswap

core/src/periph/at28c256/default.rs

@@ -9,7 +9,11 @@ impl Default for At28C256 {
         let boxed_array: Box<[u8; SIZE_32KB]> = boxed_slice
             .try_into()
             .expect("Failed to convert Vec to boxed array");
-        At28C256 { data: boxed_array }
+        At28C256 { data: boxed_array,
+        address_bus: 0x0000,
+        data_bus: 0x00,
+        offset: 0x0000
+        }
     }
 }
 

core/src/periph/at28c256/dump.rs

@@ -0,0 +1,13 @@
+use crate::periph::at28c256::At28C256;
+
+pub struct At28C256State {
+    offset: u16
+}
+
+impl At28C256 {
+    pub fn dump(&self) -> At28C256State {
+        At28C256State {
+            offset: self.offset
+        }
+    }
+}

core/src/periph/at28c256/mod.rs

@@ -3,6 +3,7 @@ pub mod rom_chip;
 pub mod tick;
 mod new;
 mod program;
+mod dump;
 
 use crate::constants::constants_system::SIZE_32KB;
 use crate::periph::rom_chip::RomChip;
@@ -15,7 +16,11 @@ use std::io::Read;
 /// 256kbit storage
 /// 32kbyte storage
 pub struct At28C256 {
+    data_bus: u8,
+    address_bus: u16,
     data: Box<[u8; SIZE_32KB]>,
+    // where in the computer memory map do we live?
+    offset: u16
 }
 
 #[cfg(test)]

core/src/periph/at28c256/new.rs

@@ -2,9 +2,12 @@ use crate::constants::constants_system::SIZE_32KB;
 use crate::periph::at28c256::At28C256;
 
 impl At28C256 {
-    pub fn new(data: &[u8; SIZE_32KB]) -> Self {
+    pub fn new(offset: u16, data: &[u8; SIZE_32KB]) -> Self {
         At28C256 {
-            data: (*data).into()
+            data: (*data).into(),
+            address_bus: 0x0000,
+            data_bus: 0x00,
+            offset
         }
     }
 }

core/src/periph/at28c256/tick.rs

@@ -1,14 +1,23 @@
+use crate::constants::constants_system::SIZE_32KB;
 use crate::periph::at28c256::At28C256;
 use crate::periph::hm62256::Hm62256;
 
 impl At28C256 {
-    fn tick(&mut self, address_bus: u16, data_bus: u8, read_mode: bool) -> (u16, u8) {
-        if read_mode {
-            panic!("UNABLE TO WRITE TO ROM");
-        } else {
-        // has to be read mode.  its a rom.
-            return (address_bus, data_bus)
+    fn max_address(&self) -> u16 {
+        self.offset + SIZE_32KB as u16
+    }
+
+
+    pub fn tick(&mut self, address_bus: u16, data_bus: u8, read_mode: bool) -> (u16, u8) {
+        if address_bus.gt(&self.offset) & address_bus.lt(&self.max_address()) {
+            if read_mode {
+                panic!("UNABLE TO WRITE TO ROM");
+            } else {
+                // has to be read mode.  its a rom.
+                return (address_bus, data_bus)
+            }
         }
+        // not for us.
         (address_bus, self.data[address_bus as usize])
     }
 }

core/src/periph/bus_device.rs

@@ -0,0 +1,3 @@
+pub trait BusDevice {
+    fn talking_to_me(&self, address: u16) -> bool;
+}

core/src/periph/hm62256/default.rs

@@ -0,0 +1,17 @@
+use crate::constants::constants_system::SIZE_32KB;
+use crate::periph::hm62256::Hm62256;
+
+impl Default for Hm62256 {
+    fn default() -> Self {
+        let vec = vec![0x00; SIZE_32KB];
+        let boxed_slice: Box<[u8]> = vec.into_boxed_slice();
+        let boxed_array: Box<[u8; SIZE_32KB]> =
+            boxed_slice.try_into().expect("Unable to box the ram");
+        Hm62256 {
+            offset: 0x0000,
+            data: boxed_array,
+            address_bus: 0x0000,
+            data_bus: 0x00
+        }
+    }
+}

core/src/periph/hm62256/dump.rs

@@ -0,0 +1,17 @@
+use crate::periph::hm62256::Hm62256;
+
+pub struct Hm62256State {
+    pub offset: u16
+}
+
+impl Hm62256 {
+    pub fn dump(&self) -> Hm62256State {
+        Hm62256State {
+            offset: self.offset
+        }
+    }
+
+    pub fn dump_data(&self) -> (u16) {
+        self.offset
+    }
+}

core/src/periph/hm62256/mod.rs

@@ -3,27 +3,23 @@
 pub mod ramchip;
 pub mod romchip;
 pub mod tick;
+pub mod default;
+pub mod new;
+pub mod dump;
 
 use crate::constants::constants_system::SIZE_32KB;
 use crate::periph::ram_chip::RamChip;
 use crate::periph::rom_chip::RomChip;
 use log::debug;
-pub struct Hm62256 {
-    pub(crate) base_offset: u16,
-    pub(crate) data: Box<[u8]>,
-}
 
-impl Default for Hm62256 {
-    fn default() -> Self {
-        let vec = vec![0x00; SIZE_32KB];
-        let boxed_slice: Box<[u8]> = vec.into_boxed_slice();
-        let boxed_array: Box<[u8; SIZE_32KB]> =
-            boxed_slice.try_into().expect("Unable to box the ram");
-        Hm62256 {
-            base_offset: 0x0000,
-            data: boxed_array,
-        }
-    }
+/// Hitachi Semiconductor
+/// 8 Bit High Speed Static Ram
+/// 32KByte
+pub struct Hm62256 {
+    pub(crate) offset: u16,
+    pub(crate) data: Box<[u8]>,
+    pub(crate) address_bus: u16,
+    pub(crate) data_bus: u8
 }
 
 #[cfg(test)]

core/src/periph/hm62256/new.rs

@@ -0,0 +1,13 @@
+use crate::constants::constants_system::SIZE_32KB;
+use crate::periph::hm62256::Hm62256;
+
+impl Hm62256 {
+    pub fn new(base_offset: u16) -> Self {
+        Self {
+            offset: base_offset,
+            data: vec![0; SIZE_32KB].into_boxed_slice(),
+            address_bus: 0x0000,
+            data_bus: 0x00
+        }
+    }
+}

core/src/periph/hm62256/tick.rs

@@ -1,16 +1,41 @@
+use crate::constants::constants_system::SIZE_32KB;
 use crate::periph::hm62256::Hm62256;
 
 impl Hm62256 {
-    fn tick(&mut self, address_bus: u16, data_bus: u8, read_mode: bool) -> (u16, u8) {
-        let new_data_bus = if read_mode {
-            // reading from ram
-            self.data[address_bus as usize]
+    fn max_address(&self) -> u16 {
+        self.offset + SIZE_32KB as u16
+    }
+
+    pub fn tick(&mut self, address_bus: u16, data_bus: u8, read_mode: bool, cs: bool) -> (u16, u8) {
+        if !(address_bus.gt( &self.offset) && address_bus.le(&self.max_address())) {
+            return (address_bus, data_bus);
+        }
+
+        println!("HM62256RAM TICK START -> 0x{address_bus:04x} 0x{data_bus:02x} {read_mode} {cs}");
+
+        self.address_bus = address_bus;
+        self.data_bus = data_bus;
+        let addr = address_bus.wrapping_sub(self.offset) + self.offset;
+
+        // did we want to talk to the chip...
+        if !cs {
+            return (address_bus, data_bus);
+        }
+
+        // ...or are we outside the range?
+        if (addr - self.offset) > SIZE_32KB as u16 {
+            return (address_bus, data_bus);
+        }
+
+        // ok.  lets see what we are dealing with
+        self.data_bus = if read_mode {
+            self.data[addr as usize]
         } else {
             // writing to ram
-            self.data[address_bus as usize] = data_bus.into();
+            self.data[addr as usize] = data_bus.into();
             data_bus
         };
-        (address_bus, new_data_bus)
+        (self.address_bus, self.data_bus)
     }
 }
 
@@ -26,9 +51,9 @@ mod test {
         let mut ram = Hm62256::default();
 
         // load the data to ram
-        ram.tick(0x0000, 0xab, false);
+        ram.tick(0x0000, 0xab, false, true);
         // read the data back
-        let (_, new_data) = ram.tick(0x0000, 0x00, true);
+        let (_, new_data) = ram.tick(0x0000, 0x00, true, true);
 
         assert_eq!(new_data, 0xab);
     }

core/src/periph/kim1_keypad/mod.rs

@@ -0,0 +1,105 @@
+/*
+  +---+---+---+---+---+---+
+  | 0 | 1 | 2 | 3 | 4 | 5 |
+  +---+---+---+---+---+---+
+  | 6 | 7 | 8 | 9 | A | B |
+  +---+---+---+---+---+---+
+  | C | D | E | F | AD| DA|
+  +---+---+---+---+---+---+
+  | + | PC| ST| RS|   |   |
+  +---+---+---+---+---+---+
+ */
+
+pub struct Kim1Keypad {
+    keys: [bool; 23],
+    stepping: bool
+}
+
+impl Kim1Keypad {
+    pub fn dump(&self) {
+        println!("Dumping state of keypad");
+    }
+}
+
+impl Kim1Keypad {
+    fn keyid(from: u8) -> usize{
+        (from % 23) as usize
+    }
+    pub fn new() -> Self {
+        Kim1Keypad {
+            keys: [false; 23],
+            stepping: false
+        }
+    }
+
+    pub fn toggle_stepping(&mut self) {
+        self.stepping = !self.stepping;;
+    }
+
+    pub fn set_stepping(&mut self, new_state: bool) {
+        self.stepping = new_state
+    }
+
+    pub fn press_key(&mut self, key_to_press: u8) {
+        self.keys[Self::keyid(key_to_press)] = true;
+    }
+
+    pub fn release_key(&mut self, key_to_release: u8) {
+        self.keys[Self::keyid(key_to_release)] = false;
+    }
+
+    pub fn is_pressed(&self, key: u8) -> bool {
+        self.keys[Self::keyid(key)]
+    }
+}
+
+#[cfg(test)]
+mod test {
+    use super::*;
+
+    #[test]
+    fn smoke() { assert!(true); }
+
+    #[test]
+    fn keys_are_pressed() {
+        let mut kb = Kim1Keypad::new();
+
+        for index in 0..23 {
+            assert!(!kb.is_pressed(index));
+            kb.press_key(index);
+            assert!(kb.is_pressed(index));
+
+            kb.release_key(index);
+            assert!(!kb.is_pressed(index));
+        }
+    }
+
+    #[test]
+    fn stepping_changes() {
+        let mut kb = Kim1Keypad::new();
+
+        kb.set_stepping(false);
+
+        assert!(!kb.stepping);
+
+        kb.toggle_stepping();
+
+        assert!(kb.stepping);
+
+        kb.toggle_stepping();
+        kb.toggle_stepping();
+        kb.toggle_stepping();
+        kb.toggle_stepping();
+        kb.toggle_stepping();
+
+        assert!(!kb.stepping);
+    }
+
+    #[test]
+    fn out_of_range() {
+        let mut kb = Kim1Keypad::new();
+
+        kb.press_key(24);
+        assert!(kb.is_pressed(1));
+    }
+}

core/src/periph/mod.rs

@@ -1,6 +1,8 @@
 pub mod rom_chip;
-
 pub mod at28c256;
 pub mod hm62256;
 pub mod ram_chip;
 pub mod mos6522;
+pub mod mos6530;
+pub mod kim1_keypad;
+mod bus_device;

core/src/periph/mos6522/mod.rs

@@ -1,2 +1,4 @@
 pub mod mos6522;
-mod registers;
+mod registers;
+mod new;
+mod tick;

core/src/periph/mos6522/mos6522.rs

@@ -5,106 +5,47 @@ use crate::constants::constants_via6522::*;
 #[derive(Default)]
 pub struct Mos6522 {
     /// data direction
-    dda: u8,
-    ddb: u8,
+    pub(crate) dda: u8,
+    pub(crate) ddb: u8,
 
     /// bottom 4 address bits
-    rs0: u8,
-    rs1: u8,
-    rs2: u8,
-    rs3: u8,
+    pub(crate) rs0: u8,
+    pub(crate) rs1: u8,
+    pub(crate) rs2: u8,
+    pub(crate) rs3: u8,
 
     /// external data bus
-    data_bus: u8,
+    pub(crate) data_bus: u8,
 
-    cs1: bool,
-    cs2: bool,
-    rw: bool,
+    pub(crate) cs1: bool,
+    pub(crate) cs2: bool,
+    // when true CPU is reading
+    pub(crate) rw: bool,
 
     /// reset circuit - true when reset inited
-    reset: bool,
+    pub(crate) reset: bool,
 
     /// IRQ - true when interrupt waiting
-    irq: bool,
+    pub(crate) irq: bool,
 
-    ira: u8,
-    ora: u8,
-    porta: u8,
-    irb: u8,
-    orb: u8,
-    portb: u8,
+    pub(crate) ira: u8,
+    pub(crate) ora: u8,
+    pub(crate) porta: u8,
+    pub(crate) irb: u8,
+    pub(crate) orb: u8,
+    pub(crate) portb: u8,
 
-    ca1: bool,
-    ca2: bool,
-    cb1: bool,
-    cb2: bool,
+    pub(crate) ca1: bool,
+    pub(crate) ca2: bool,
+    pub(crate) cb1: bool,
+    pub(crate) cb2: bool,
+
+    // memory offset for where in the computers memory map this fits
+    pub(crate) offset: u16,
+    pub(crate) address_bus: u16,
 }
 
 impl Mos6522 {
-    pub fn new() -> Self {
-        Mos6522::default()
-    }
-
-    /// tick
-    ///
-    /// data_bus -> 8 bits from the data bus
-    /// control  -> 4 bits to identify which register to control
-    pub fn tick(&mut self, data_bus: u8, control: u8, rw: bool) -> (u8) {
-        println!("Mos6522 Tick Start -> 0x{data_bus:02x} / 0x{control:02x} / {rw}");
-        if rw  {
-            // RW true = CPU is writing
-            self.data_bus = data_bus;
-            match control {
-                VIA6522_DDRA => {
-                    debug!("Setting DDA to 0x{data_bus:02x}");
-                    // setting the Data Direction for Port A
-                    self.dda = data_bus;
-                },
-                VIA6522_DDRB => {
-                    debug!("Setting DDB to 0x{data_bus:02x}");
-                    // setting the data direction for port b
-                    self.ddb = data_bus;
-                },
-                VIA6522_ORB => {
-                    // writing data to ORB
-                    let masked_data = data_bus & self.ddb;
-                    debug!("Setting ORB to 0x{data_bus:02x} / masked at 0x{masked_data:02x}");
-                    self.portb = masked_data;
-                },
-                VIA6522_ORA => {
-                    // writing data to ORA
-                    let masked_data = data_bus & self.dda;
-                    debug!("Setting ORA to 0x{data_bus:02x} / masked at 0x{masked_data:02x}");
-                    self.porta = masked_data;
-                },
-                _ => {}
-            }
-        } else {
-            // RW false = CPU is reading
-            self.data_bus = match control {
-                VIA6522_DDRA => {
-                    self.dda
-                }
-                VIA6522_DDRB => {
-                    self.ddb
-                }
-                VIA6522_ORA => {
-                    self.porta & self.dda
-                }
-                VIA6522_ORB => {
-                    self.portb & self.ddb
-                }
-                _ => {
-                    debug!("VIA got request for b{:08b} / 0x{:02x}", control, control);
-                    // do nothing.  bad address for VIA
-                    self.data_bus
-                }
-            }
-        }
-
-        (self.data_bus)
-    }
-
     pub fn start_clocks(&mut self) {
         loop {
             let cycle_start = Instant::now();
@@ -115,7 +56,6 @@ impl Mos6522 {
     }
 }
 
-
 #[cfg(test)]
 mod test {
     use super::*;
@@ -126,40 +66,40 @@ mod test {
     #[test]
     fn registers() {
         let mut x = Mos6522::new();
-        x.tick(0b0000_0000, VIA6522_DDRA, true);
+        x.tick(0b0000_0000, VIA6522_DDRA, false, true);
         assert_eq!(x.dda, 0b0000_0000);
-        x.tick(0b1111_1111, VIA6522_DDRA, true);
+        x.tick(0b1111_1111, VIA6522_DDRA, false, true);
         assert_eq!(x.dda, 0b1111_1111);
 
-        x.tick(0b0000_0000, VIA6522_DDRB, true);
+        x.tick(0b0000_0000, VIA6522_DDRB, false, true);
         assert_eq!(x.ddb, 0b0000_0000);
-        x.tick(0b1111_1111, VIA6522_DDRB, true);
+        x.tick(0b1111_1111, VIA6522_DDRB, false, true);
         assert_eq!(x.ddb, 0b1111_1111);
 
-        x.tick(0b0000_0000, VIA6522_ORA, true);
+        x.tick(0b0000_0000, VIA6522_ORA, false, true);
         assert_eq!(x.porta, 0b0000_0000);
-        x.tick(0b1111_1111, VIA6522_ORA, true);
+        x.tick(0b1111_1111, VIA6522_ORA, false, true);
         assert_eq!(x.porta, 0b1111_1111);
 
-        x.tick(0b0000_0000, VIA6522_ORB, true);
+        x.tick(0b0000_0000, VIA6522_ORB, false, true);
         assert_eq!(x.portb, 0b0000_0000);
-        x.tick(0b1111_1111, VIA6522_ORB, true);
+        x.tick(0b1111_1111, VIA6522_ORB, false, true);
         assert_eq!(x.portb, 0b1111_1111);
     }
 
     #[test]
     fn partial_output_porta() {
         let mut x = Mos6522::new();
-        x.tick(0b1010_1010, VIA6522_DDRA, true);
-        x.tick(0b1111_1111, VIA6522_ORA, true);
+        x.tick(0b1010_1010, VIA6522_DDRA, false, true);
+        x.tick(0b1111_1111, VIA6522_ORA, false, true);
         assert_eq!(x.porta, 0b1010_1010);
     }
 
     #[test]
     fn partial_output_portb() {
         let mut x = Mos6522::new();
-        x.tick(0b0101_0101, VIA6522_DDRB, true);
-        x.tick(0b1111_1111, VIA6522_ORB, true);
+        x.tick(0b0101_0101, VIA6522_DDRB, false, true);
+        x.tick(0b1111_1111, VIA6522_ORB, false, true);
         assert_eq!(x.portb, 0b0101_0101);
     }
 }

core/src/periph/mos6522/new.rs

@@ -0,0 +1,7 @@
+use crate::periph::mos6522::mos6522::Mos6522;
+
+impl Mos6522 {
+    pub fn new() -> Self {
+        Mos6522::default()
+    }
+}

core/src/periph/mos6522/tick.rs

@@ -0,0 +1,86 @@
+use log::debug;
+use crate::constants::constants_system::SIZE_32KB;
+use crate::constants::constants_via6522::{VIA6522_DDRA, VIA6522_DDRB, VIA6522_ORA, VIA6522_ORB};
+use crate::periph::mos6522::mos6522::Mos6522;
+
+impl Mos6522 {
+    fn max_address(&self) -> u16 {
+        self.offset + SIZE_32KB as u16
+    }
+    /// tick
+    ///
+    /// data_bus -> 8 bits from the data bus
+    /// control  -> 4 bits to identify which register to control
+    pub fn tick(&mut self,  address_bus: u16, data_bus: u8,reset: bool, rw: bool) -> (u16, u8) {
+        if !(address_bus.gt( &self.offset) && address_bus.le(&self.max_address())) {
+            return (address_bus, data_bus);
+        }
+
+        let local_address = address_bus - self.offset;
+
+        println!("Mos6522 Tick Start -> D:0x{data_bus:02x} / A:0x{address_bus:02x} / {rw} (Actual 0x{local_address:02x}");
+        if reset {
+            // reset process
+            println!("Resetting Mos6522");
+            self.data_bus = data_bus;
+            self.dda = 0x00;
+            self.ddb = 0x00;
+            self.porta = 0x00;
+            self.portb = 0x00;
+            return (self.address_bus, self.data_bus)
+        }
+
+        if rw {
+            // RW true = CPU is writing
+            self.data_bus = data_bus;
+            match local_address as u8 {
+                VIA6522_DDRA => {
+                    debug!("Setting DDA to 0x{data_bus:02x}");
+                    // setting the Data Direction for Port A
+                    self.dda = data_bus;
+                },
+                VIA6522_DDRB => {
+                    debug!("Setting DDB to 0x{data_bus:02x}");
+                    // setting the data direction for port b
+                    self.ddb = data_bus;
+                },
+                VIA6522_ORB => {
+                    // writing data to ORB
+                    let masked_data = data_bus & self.ddb;
+                    debug!("Setting ORB to 0x{data_bus:02x} / masked at 0x{masked_data:02x}");
+                    self.portb = masked_data;
+                },
+                VIA6522_ORA => {
+                    // writing data to ORA
+                    let masked_data = data_bus & self.dda;
+                    debug!("Setting ORA to 0x{data_bus:02x} / masked at 0x{masked_data:02x}");
+                    self.porta = masked_data;
+                },
+                _ => {}
+            }
+        } else {
+            // RW false = CPU is reading
+            self.data_bus = match local_address as u8 {
+                VIA6522_DDRA => {
+                    self.dda
+                }
+                VIA6522_DDRB => {
+                    self.ddb
+                }
+                VIA6522_ORA => {
+                    self.porta & self.dda
+                }
+                VIA6522_ORB => {
+                    self.portb & self.ddb
+                }
+                _ => {
+                    debug!("VIA got request for b{:08b} / 0x{:02x}", address_bus, address_bus);
+                    // do nothing.  bad address for VIA
+                    self.data_bus
+                }
+            }
+        }
+
+        (self.address_bus, self.data_bus)
+    }
+}

core/src/periph/mos6530/dump.rs

@@ -0,0 +1,11 @@
+use crate::periph::mos6530::mos6530::Mos6530;
+
+impl Mos6530 {
+    pub fn dump(&self) {
+        println!("Dumping state of Mos6530 RRIOT");
+    }
+
+    pub fn dump_data(&self) -> (u16, u16, u16) {
+        (self.io_offset, self.ram_offset, self.rom_offset)
+    }
+}

core/src/periph/mos6530/mod.rs

@@ -0,0 +1,4 @@
+pub mod mos6530;
+pub mod tick;
+mod new;
+mod dump;

core/src/periph/mos6530/mos6530.rs

@@ -0,0 +1,32 @@
+use crate::constants::constants_system::*;
+use crate::periph::mos6522::mos6522::Mos6522;
+
+/// Mos6530 RRIOT
+/// Ram/Rom/IO/Timer
+///
+/// Represents a single Mos6530 RRIOT Chip
+///
+/// Used in the TIM-1, KIM-1
+///
+/// 1kb Rom
+/// 64 bytes RAM
+/// IO Ports (A, B)
+/// Timer
+///
+/// SEE ALSO Mos6532
+pub struct Mos6530 {
+    pub(crate) data: [u8; SIZE_1KB],
+    pub(crate) ram: [u8; 64],
+    pub(crate) porta: u8,
+    pub(crate) portb: u8,
+    pub(crate) data_bus: u8,
+    pub(crate) address_bus: u16,
+    pub(crate) cs1: bool,
+    pub(crate) cs2: bool,
+    // when true, CPU is reading
+    pub(crate) rw: bool,
+    pub(crate) reset: bool,
+    pub(crate) io_offset: u16,
+    pub(crate) ram_offset: u16,
+    pub(crate) rom_offset: u16
+}

core/src/periph/mos6530/new.rs

@@ -0,0 +1,25 @@
+use crate::constants::constants_system::SIZE_1KB;
+use crate::periph::mos6530::mos6530::Mos6530;
+
+impl Mos6530 {
+    pub fn new(io_offset: u16,
+               ram_offset: u16,
+               rom_offset: u16,
+               data: &[u8; SIZE_1KB]) -> Self {
+        Mos6530 {
+            data: *data,
+            ram: [0x00; 64],
+            porta: 0,
+            portb: 0,
+            data_bus: 0,
+            address_bus: 0,
+            cs1: false,
+            cs2: false,
+            rw: false,
+            reset: false,
+            io_offset,
+            ram_offset,
+            rom_offset
+        }
+    }
+}

core/src/periph/mos6530/tick.rs

@@ -0,0 +1,26 @@
+use log::debug;
+use crate::periph::mos6530::mos6530::Mos6530;
+
+impl Mos6530 {
+    pub fn tick(&mut self, address_bus: u16, data_bus: u8, reset: bool, rw: bool) {
+        debug!("Starting tick of MOS6530 RRIOT with 0x{address_bus:04x} / 0b{data_bus:08b} / R:{reset} / RW:{rw} (OFFSETS: I{:04x}, RA{:04x}, RO{:04x})", self.io_offset, self.ram_offset, self.rom_offset);
+        let io_max = self.io_offset + 0x3f;
+        let ram_max = self.ram_offset + 0x3f;
+        let rom_max = self.rom_offset + 0x400;
+
+        if address_bus.ge(&self.io_offset) && address_bus.le(&io_max) {
+            let effective = address_bus - self.io_offset;
+            println!("IO Activity at effective 0x{effective:02x}");
+        }
+
+        if address_bus.ge(&self.ram_offset) && address_bus.le(&ram_max) {
+            let effective = address_bus - self.ram_offset;
+            println!("RAM Activity at effective 0x{effective:02x}");
+        }
+
+        if address_bus.ge(&self.rom_offset) && address_bus.le(&rom_max) {
+            let effective = address_bus - self.rom_offset;
+            println!("Rom Activity at effective 0x{effective:02x}");
+        }
+    }
+}