80 lines
1.9 KiB
Rust
80 lines
1.9 KiB
Rust
// HM62256 Static Ram
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pub mod ramchip;
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pub mod romchip;
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pub mod tick;
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pub mod default;
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pub mod new;
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pub mod dump;
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mod control;
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use crate::constants::constants_system::SIZE_32KB;
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use crate::traits::ram_chip::RamChip;
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use crate::traits::rom_chip::RomChip;
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use log::debug;
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/// Hitachi Semiconductor
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/// 8 Bit High Speed Static Ram
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/// 32KByte
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pub struct Hm62256 {
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pub(crate) offset: u16,
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pub(crate) max_offset: u16,
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pub(crate) data: Box<[u8]>,
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pub(crate) address_bus: u16,
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pub(crate) data_bus: u8,
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// Chip Select
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pub(crate) cs: bool,
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// Write Enable
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pub(crate) we: bool,
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// Output Enable
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pub(crate) oe: bool
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}
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#[cfg(test)]
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mod test {
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use super::*;
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use rand::random;
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use crate::traits::memory_chip::MemoryChip;
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#[test]
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fn smoke() {
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assert!(true)
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}
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#[test]
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fn written_data_comes_back() {
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let mut ram = Hm62256::default();
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// 100,000 random read/writes to ram that all read back right
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for _ in 0..100_000 {
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let mut offset: u16 = random();
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println!("Size = {SIZE_32KB}");
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let value: u8 = random();
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println!("Wrote [{value:02x}] to [{offset:04x}]");
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ram.write(&offset, &value);
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assert_eq!(ram.read(&offset), value)
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}
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}
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#[test]
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fn address_space_is_round() {
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// addresses written past the last address 'loop' back to 0+(offset - MAX_SIZE)
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let max_offset = SIZE_32KB;
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let test_offset = max_offset;
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// all zero
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let mut ram = Hm62256::default();
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// write FF to the addresss after the last
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ram.write(&(test_offset as u16), &0xff);
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// check all the ram for anything that isn't 0x00
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assert_eq!(ram.read(&(0x0000)), 0xff);
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for offset in 1..SIZE_32KB {
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println!("Testing offset {offset:04x} for 0x00");
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assert_eq!(ram.read(&(offset as u16)), 0x00);
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}
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}
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}
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