80 lines
1.9 KiB
Rust
80 lines
1.9 KiB
Rust
use log::debug;
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use crate::constants::constants_system::{SIZE_1KB, SIZE_32KB};
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use crate::periph::mos6530::mos6530::Mos6530;
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use crate::traits::bus_device::BusDevice;
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use crate::traits::memory_chip::MemoryChip;
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use crate::traits::ram_chip::RamChip;
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use crate::traits::rom_chip::RomChip;
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use crate::traits::via_chip::ViaChip;
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impl BusDevice for Mos6530 {
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fn min_offset(&self) -> u16 {
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self.ram_offset
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}
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fn max_offset(&self) -> u16 {
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self.min_offset() + SIZE_1KB as u16
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}
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fn address_bus(&self) -> u16 {
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self.address_bus
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}
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fn data_bus(&self) -> u8 {
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self.data_bus
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}
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fn set_address_bus(&mut self, new_value: u16) {
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self.address_bus = new_value
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}
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fn set_data_bus(&mut self, new_value: u8) {
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self.data_bus = new_value
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}
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}
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impl RamChip for Mos6530 {
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fn write(&mut self, offset: &u16, value: &u8) {
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debug!("🐙 Writing ${value:02x} to ${offset:04x}");
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}
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}
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impl MemoryChip for Mos6530 {
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fn read(&self, offset: &u16) -> u8 {
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debug!("🐙 Reading from ${offset:04x}");
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0
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}
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}
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impl RomChip for Mos6530 {
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fn program(new_data: &[u8]) -> Box<Self> {
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debug!("🐙 programming {}b to ROM", new_data.len());
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Box::new(Mos6530 {
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data: new_data.to_vec().try_into().unwrap(),
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ram: [0x00; 64],
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porta: 0,
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portb: 0,
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data_bus: 0,
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address_bus: 0,
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cs1: false,
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cs2: false,
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rw: false,
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reset: false,
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io_offset: 0,
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ram_offset: 0,
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rom_offset: 0,
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})
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}
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}
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impl ViaChip for Mos6530 {
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fn set_port_ddr(&mut self, port_index: u8, value: u8) {
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debug!("🐙Setting DDR{port_index} to {value:02x}");
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}
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fn set_port_data(&mut self, port_index: u8, value: u8) {
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debug!("🐙Setting PORT{port_index} to {value:02x}");
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}
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}
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