681 lines
24 KiB
Rust
681 lines
24 KiB
Rust
use log::trace;
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use crate::address_mode::AddressMode;
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use crate::constants::constants_isa_op::ISA_OP_NOP;
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use crate::instruction::Instruction;
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use crate::mos6502flags::{Mos6502Flag, Mos6502Flags};
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use crate::mos6502flags::Mos6502Flag::*;
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use crate::op_info::OpInfo;
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use crate::operand::Operand;
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use crate::operation::Operation;
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use crate::constants::constants_system::*;
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use crate::instruction_table::INSTRUCTION_TABLE;
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pub struct Mos6502Cpu {
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// this is public for rendering quickly.
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pub memory: Box<[u8]>,
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a: u8,
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x: u8,
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y: u8,
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flags: Mos6502Flags,
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pc: u16,
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s: u8,
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pub microcode_step: u8,
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pub address_bus: u16,
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pub data_bus: u8,
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ir: Instruction, // Instruction Register
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oi: OpInfo,
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has_reset: bool,
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iv: u16, // Interrupt Vector
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cycle_carry: u16, // Value to hold between microsteps
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ir_bytes: Box<[u8]>
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}
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impl Default for Mos6502Cpu {
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fn default() -> Self {
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let vec = vec![0x00; SIZE_64KB];
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let boxed_slize: Box<[u8]> = vec.into_boxed_slice();
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let boxed_array: Box<[u8; SIZE_64KB]> = boxed_slize.try_into().expect("Failed to allocate system memory");
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let mut working = Mos6502Cpu {
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memory: boxed_array,
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a: 0x00,
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x: 0x00,
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y: 0x00,
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flags: Default::default(),
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pc: 0xfffd,
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s: 0x00,
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microcode_step: 0x00,
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address_bus: 0x00,
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data_bus: 0x00,
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ir: Instruction {
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op: Operation::NOP,
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mode: AddressMode::Implied,
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operand: Operand::None,
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},
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oi: INSTRUCTION_TABLE[ISA_OP_NOP as usize].unwrap(),
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has_reset: false,
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iv: 0xfffe,
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cycle_carry: 0x0000,
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ir_bytes: [].into()
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};
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working.reset_cpu();
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working
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}
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}
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impl Mos6502Cpu {
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pub fn new() -> Mos6502Cpu {
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let vec = vec![0x00; SIZE_64KB];
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let boxed_slize: Box<[u8]> = vec.into_boxed_slice();
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let boxed_array: Box<[u8; SIZE_64KB]> = boxed_slize.try_into().expect("Failed to allocate system memory");
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let mut working = Mos6502Cpu {
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memory: boxed_array,
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ir_bytes: [].into(),
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..Default::default()
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};
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working.reset_cpu();
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working
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}
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fn reset_cpu(&mut self) {
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// self = &mut Mos6502Cpu::default();
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println!("Should tick 7 times.");
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// read the value at 0xfffc 0xfffd for our reset vector.
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// read the value at 0xfffe 0xffff for our int vector
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self.pc = self.read_word(&OFFSET_RESET_VECTOR);
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self.iv = self.read_word(&OFFSET_INT_VECTOR);
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println!("PC and IV are now set from ROM addresses");
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}
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fn read_word(&self, offset: &u16) -> u16 {
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let low = self.memory[*offset as usize];
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let high = self.memory[*offset as usize + 1];
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(high as u16) << 8 | low as u16
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}
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pub fn peek_flag(&self, flag_to_read: Mos6502Flag) -> bool {
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self.flags.flag(flag_to_read)
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}
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pub fn poke_flag(&mut self, flag_to_set: Mos6502Flag, new_value: bool) {
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if new_value { self.flags.set_flag(flag_to_set) } else { self.flags.clear_flag(flag_to_set) }
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}
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pub fn peek(&self, offset: u16) -> u8 {
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self.memory[offset as usize]
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}
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pub fn poke(&mut self, offset: u16, value: u8) {
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self.memory[offset as usize] = value
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}
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pub fn peek_a(&self) -> u8 {
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self.a
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}
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pub fn poke_a(&mut self, new_a: u8) {
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self.a = new_a;
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}
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pub fn peek_x(&self) -> u8 {
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self.x
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}
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pub fn poke_x(&mut self, new_x: u8) {
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println!("Updating register X from [{}] to [{}]", self.x, new_x);
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self.x = new_x
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}
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pub fn peek_y(&self) -> u8 {
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self.y
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}
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pub fn poke_y(&mut self, new_y: u8) {
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self.y = new_y
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}
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fn advance_pc(&mut self, how_far: u16) {
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self.pc += how_far;
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}
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fn set_pc_to(&mut self, new_pc: u16) {
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self.pc = new_pc;
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}
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/// Ticks the CPU
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pub fn tick(&mut self) {
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println!("PREPARiNG TO TICK CPU AT PC 0x{:04x}", self.pc);
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if self.microcode_step == 0 {
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println!("OUT OF MICROSTEPS. Decoding the next instruction");
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let offset = self.pc as usize;
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// TODO: this calls opinfo 2x
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self.oi = Instruction::opinfo(&self.memory[offset..offset + 4]).unwrap();
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self.ir = Instruction::decode(&self.memory[offset..offset + 4]).unwrap();
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self.microcode_step = self.oi.cycles;
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println!("Decoded [[{:?}]]", self.ir);
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self.advance_pc(self.oi.length as u16);
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// load the microstep buffer with what steps to run
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// set the counter to the number of steps left
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} else {
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// run 1 microcode step
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println!("Microstep {}/{} for {:?}", self.microcode_step, self.oi.cycles, self.ir.op);
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match self.ir.op {
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Operation::ADC => {
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match self.microcode_step {
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1 => {
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match self.ir.mode {
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AddressMode::Immediate => {}
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AddressMode::ZeroPage => {}
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AddressMode::ZeroPageX => {}
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AddressMode::Absolute => {}
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AddressMode::AbsoluteX => {}
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AddressMode::AbsoluteY => {}
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AddressMode::Indirect => {}
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AddressMode::IndirectX => {}
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AddressMode::IndirectY => {}
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_ => {}
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}
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},
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2 => {},
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_ => {}
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}
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}
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Operation::AND => {}
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Operation::ASL => {}
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Operation::BCC => {}
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Operation::BCS => {}
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Operation::BEQ => {}
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Operation::BIT => {}
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Operation::BMI => {}
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Operation::BNE => {}
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Operation::BPL => {}
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Operation::BRK => {}
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Operation::BVC => {}
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Operation::BVS => {}
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Operation::CLC => {
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self.flags.clear_flag(Carry);
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}
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Operation::CLD => {
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self.flags.clear_flag(Decimal);
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}
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Operation::CLI => {
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self.flags.clear_flag(Interrupt);
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}
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Operation::CLV => {
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self.flags.clear_flag(Overflow);
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}
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Operation::CMP => {}
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Operation::CPX => {}
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Operation::CPY => {}
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Operation::DEC => {
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match self.microcode_step {
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// DEC Step 1
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1 => {
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let working_value = match self.oi.mode {
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AddressMode::ZeroPage => {
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// read from
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let offset = match self.ir.operand {
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Operand::Byte(z) => {
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z
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}
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_ => { 0x00 }
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};
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trace!("READING FROM MEMORY AT 0x{offset:04x}");
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self.memory[offset as usize]
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// self.peek(offset);
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}
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AddressMode::ZeroPageX => {
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let offset = match self.ir.operand {
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Operand::Byte(z) => {
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z
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}
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_ => { 0x00 }
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};
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// self.memory.peek(offset + self.x);
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self.memory[offset as usize]
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}
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AddressMode::Absolute => {
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let offset = match self.ir.operand {
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Operand::Word(offset) => {
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offset
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}
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_ => { 0x00 }
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};
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// self.memory.peek(offset)
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self.memory[offset as usize]
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}
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AddressMode::AbsoluteX => {
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let offset = match self.ir.operand {
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Operand::Word(offset) => {
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offset
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}
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_ => { 0x00 }
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};
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// self.memory.peek(offset + self.x);
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self.memory[offset as usize]
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}
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_ => {
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0x00
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}
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};
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}
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// DEC write memory
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2 => {
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self.a = self.cycle_carry as u8;
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}
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_ => {}
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}
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}
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Operation::DEX => {
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if self.microcode_step == 1 {
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let (new_x, new_carry) = self.x.overflowing_sub(1);
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self.poke_x(new_x);
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self.poke_flag(Carry, new_carry);
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}
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}
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Operation::DEY => {
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if self.microcode_step == 1 {
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(self.y, _) = self.y.overflowing_sub(1);
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}
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}
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Operation::EOR => { }
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Operation::INC => { }
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Operation::INX => {
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if self.microcode_step == 1 {
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let (new_x, new_carry) = self.x.overflowing_add(1);
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self.poke_x(new_x);
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self.poke_flag(Carry, new_carry);
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}
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}
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Operation::INY => {
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if self.microcode_step == 1 {
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let (new_y, new_carry) = self.y.overflowing_add(1);
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self.poke_y(new_y);
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self.poke_flag(Carry, new_carry);
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} }
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Operation::JMP => {
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match self.ir.operand {
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Operand::Word(offset) => {
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self.pc = offset;
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}
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_ => {}
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}
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}
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Operation::JSR => {
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// push pc to stack.
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// jump to the subroutine.
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}
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Operation::LDA => {
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match self.oi.mode {
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AddressMode::Immediate => {
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match self.ir.operand {
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Operand::Byte(value) => {
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println!("Loading 0x{value:02x} ({value}) into A");
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self.a = value;
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}
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_ => {}
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}
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}
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AddressMode::ZeroPage => {
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match self.ir.operand {
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Operand::Byte(value) => {
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println!("Loading from zero page at 0x{value:02x} ({value})");
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self.a = self.memory[value as usize];
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}
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_ => {}
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}
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}
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AddressMode::ZeroPageX => {
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match self.ir.operand {
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Operand::Byte(value) => {
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let x_offset = self.x;
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self.a = self.memory[(value + x_offset) as usize];
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}
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_ => {}
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}
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}
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AddressMode::Absolute => {
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if let Operand::Word(offset) = self.ir.operand {
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println!("Loading from absolute address 0x{offset:04x}");
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self.a = self.memory[offset as usize];
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}
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}
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AddressMode::AbsoluteX => {
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if let Operand::Word(offset) = self.ir.operand {
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self.a = self.memory[(offset + self.x as u16) as usize];
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}
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}
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AddressMode::AbsoluteY => {
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if let Operand::Word(offset) = self.ir.operand {
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self.a = self.memory[(offset + self.y as u16) as usize];
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}
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}
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AddressMode::Indirect => {}
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AddressMode::IndirectX => {}
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AddressMode::IndirectY => {}
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_ => {
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println!("INVALID ADDRESS MODE FOR LDA");
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}
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}
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}
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Operation::LDX => {}
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Operation::LDY => {}
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Operation::LSR => {}
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Operation::NOP => {
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// do nothing.
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}
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Operation::ORA => {}
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Operation::PHA => {}
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Operation::PHP => {}
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Operation::PLA => {}
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Operation::PLP => {}
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Operation::ROL => {
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if self.microcode_step == 1 {
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self.a = self.a.rotate_left(1);
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}
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}
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Operation::ROR => {
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// rotate A
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if self.microcode_step == 1 {
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self.a = self.a.rotate_right(1);
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}
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}
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Operation::RTI => {}
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Operation::RTS => {}
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Operation::SBC => {}
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Operation::SEC => {
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self.flags.set_flag(Carry);
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}
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Operation::SED => {
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self.flags.set_flag(Decimal);
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}
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Operation::SEI => {
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self.flags.set_flag(Interrupt);
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}
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Operation::STA => {
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match self.oi.mode {
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AddressMode::ZeroPage => {
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// write to the zero page.
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match self.ir.operand {
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Operand::Byte(target) => {
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self.memory[target as usize] = self.a;
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}
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_ => {
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// Invalid parameter
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}
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}
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}
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AddressMode::ZeroPageX => {
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match self.ir.operand {
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Operand::Byte(target) => {
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let x = self.x;
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self.memory[(x + target) as usize] = self.a;
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}
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_ => {
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// Invalid Parameter
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}
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}
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}
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AddressMode::Absolute => {
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// write from A to the specified memory location
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match self.ir.operand {
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Operand::Word(offset) => {
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self.memory[offset as usize] = self.a;
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}
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_ => {
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// Invalid Parameter
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}
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}
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}
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AddressMode::AbsoluteX => {
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match self.ir.operand {
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Operand::Word(offset) => {
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self.memory[(offset + self.x as u16) as usize] = self.a;
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}
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_ => {
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// Invalid Parameter
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}
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}
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}
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AddressMode::AbsoluteY => {
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match self.ir.operand {
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Operand::Word(offset) => {
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self.memory[(offset + self.y as u16) as usize] = self.a;
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}
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_ => {
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// Invalid Parameter
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}
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}
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}
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AddressMode::IndirectX => {}
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AddressMode::IndirectY => {}
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_ => {
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// invalid memory mode
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}
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}
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}
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Operation::STX => {}
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Operation::STY => {}
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Operation::TAX => {
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self.x = self.a;
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}
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Operation::TAY => {
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self.y = self.a;
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}
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Operation::TSX => {
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}
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Operation::TXA => {
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self.a = self.x;
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}
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Operation::TXS => {
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}
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Operation::TYA => {
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self.y = self.a;
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}
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}
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self.microcode_step -= 1;
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}
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}
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pub fn dump(&self) {
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println!("CPU State: PC: {:04x} / A: {:02x} / X: {:02x} / Y: {:02x} / ADDRESS: {:04x} / DATA: {:02x} / MICROSTEPS: {:02x} / S: {}",
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self.pc, self.a, self.x, self.y, self.address_bus, self.data_bus, self.microcode_step, self.flags.dump());
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}
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pub fn dump_data(&self) -> ( u16, u8, u8, u8, u16, u8, u8) {
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(self.pc, self.a, self.x, self.y, self.address_bus, self.data_bus, self.microcode_step)
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}
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}
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#[cfg(test)]
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mod test {
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use crate::constants::constants_isa_op::*;
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use crate::instruction_table::{INSTRUCTION_CYCLES, INSTRUCTION_TABLE};
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use super::*;
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#[test]
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fn clc() {
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// setup the CPU for our test
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let mut cpu = Mos6502Cpu::default();
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cpu.flags.set_flag(Carry);
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// Load our 'test program'
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cpu.memory[0x6000] = ISA_OP_CLC;
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// Start the PC at our program
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cpu.pc = 0x6000;
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// Tick the CPU through the instruction
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for _ in 0..INSTRUCTION_TABLE[ISA_OP_CLC as usize].unwrap().cycles { cpu.tick(); }
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assert!(!cpu.peek_flag(Carry));
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}
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#[test]
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fn cld() {
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let mut cpu = Mos6502Cpu::default();
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cpu.flags.set_flag(Decimal);
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cpu.memory[0x6000] = ISA_OP_CLD;
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cpu.pc = 0x6000;
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for _ in 0..INSTRUCTION_TABLE[ISA_OP_CLD as usize].unwrap().cycles { cpu.tick(); }
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assert!(!cpu.peek_flag(Decimal));
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}
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#[test]
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fn cli() {
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let mut cpu = Mos6502Cpu::default();
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cpu.flags.set_flag(Interrupt);
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cpu.memory[0x6000] = ISA_OP_CLI;
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cpu.pc = 0x6000;
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for _ in 0..=INSTRUCTION_CYCLES(ISA_OP_CLI) { cpu.tick(); }
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assert!(!cpu.peek_flag(Interrupt));
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}
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#[test]
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fn clv() {
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let mut cpu = Mos6502Cpu::default();
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cpu.flags.set_flag(Overflow);
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cpu.memory[0x6000] = ISA_OP_CLV;
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cpu.pc = 0x6000;
|
|
|
|
for _ in 0..=INSTRUCTION_CYCLES(ISA_OP_CLV) { cpu.tick(); }
|
|
|
|
assert!(!cpu.peek_flag(Overflow));
|
|
}
|
|
|
|
#[test]
|
|
fn lda_immediate() {
|
|
let mut cpu = Mos6502Cpu::default();
|
|
cpu.memory[0x6000] = ISA_OP_LDA_I;
|
|
cpu.memory[0x6001] = 0xab;
|
|
cpu.pc = 0x6000;
|
|
|
|
for _ in 0..=INSTRUCTION_CYCLES(ISA_OP_LDA_I) { cpu.tick(); }
|
|
|
|
assert_eq!(cpu.a, 0xab);
|
|
}
|
|
|
|
#[test]
|
|
fn lda_zx() {
|
|
let mut cpu = Mos6502Cpu::default();
|
|
cpu.poke_x(1);
|
|
cpu.memory[0x6000] = ISA_OP_LDA_ZX;
|
|
cpu.memory[0x6001] = 0xab;
|
|
cpu.memory[0x00ac] = 0xbe;
|
|
cpu.pc = 0x6000;
|
|
|
|
for _ in 0..=INSTRUCTION_CYCLES(ISA_OP_LDA_ZX) { cpu.tick(); };
|
|
|
|
// println!("MEMORY AT 0x00aa, ab, ac, ad, ae -> {:02x} {:02x} {:02x} {:02x} {:02x}", cpu.memory[0x00aa], cpu.memory[0x00ab], cpu.memory[0x00ac], cpu.memory[0x00ad], cpu.memory[0x00ae]);
|
|
// cpu.dump();
|
|
assert_eq!(cpu.peek_a(), 0xbe);
|
|
assert!(!cpu.peek_flag(Zero));
|
|
assert!(!cpu.peek_flag(Carry));
|
|
assert!(!cpu.peek_flag(Negative));
|
|
}
|
|
|
|
#[test]
|
|
fn lda_zeropage() {
|
|
let mut cpu = Mos6502Cpu::default();
|
|
cpu.memory[0x6000] = ISA_OP_LDA_Z;
|
|
cpu.memory[0x6001] = 0xab;
|
|
// Load ZeroPage
|
|
cpu.memory[0x00ab] = 0xbe;
|
|
cpu.pc = 0x6000;
|
|
|
|
for _ in 0..INSTRUCTION_CYCLES(ISA_OP_LDA_Z) { cpu.tick(); }
|
|
|
|
assert_eq!(cpu.a, 0xbe);
|
|
}
|
|
|
|
#[test]
|
|
fn lda_absolute() {
|
|
let mut cpu = Mos6502Cpu::default();
|
|
cpu.memory[0x6000] = ISA_OP_LDA_ABS;
|
|
cpu.memory[0x6001] = 0xef;
|
|
cpu.memory[0x6002] = 0xbe;
|
|
cpu.memory[0xbeef] = 0xab;
|
|
cpu.pc = 0x6000;
|
|
|
|
for _ in 0..=INSTRUCTION_CYCLES(ISA_OP_LDA_ABS) { cpu.tick(); }
|
|
|
|
assert_eq!(cpu.a, 0xab);
|
|
}
|
|
|
|
#[test]
|
|
fn lda_absolutex() {
|
|
let mut cpu = Mos6502Cpu::default();
|
|
cpu.memory[0x6000] = ISA_OP_LDA_ABSX;
|
|
cpu.memory[0x6001] = 0xef;
|
|
cpu.memory[0x6002] = 0xbe;
|
|
cpu.poke_x(0x01);
|
|
cpu.memory[0xbef0] = 0xab;
|
|
cpu.pc = 0x6000;
|
|
|
|
for _ in 0..=INSTRUCTION_CYCLES(ISA_OP_LDA_ABSX) { cpu.tick(); }
|
|
|
|
assert_eq!(cpu.a, 0xab);
|
|
}
|
|
|
|
#[test]
|
|
fn lda_absolutey() {
|
|
let mut cpu = Mos6502Cpu::default();
|
|
cpu.memory[0x6000] = ISA_OP_LDA_ABSY;
|
|
cpu.memory[0x6001] = 0xef;
|
|
cpu.memory[0x6002] = 0xbe;
|
|
cpu.poke_y(0x01);
|
|
cpu.memory[0xbef0] = 0xab;
|
|
cpu.pc = 0x6000;
|
|
|
|
for _ in 0..=INSTRUCTION_CYCLES(ISA_OP_LDA_ABSY) { cpu.tick(); }
|
|
|
|
assert_eq!(cpu.a, 0xab);
|
|
}
|
|
|
|
#[test]
|
|
fn dex_inx() {
|
|
let mut cpu = Mos6502Cpu::default();
|
|
cpu.x = 0xab;
|
|
cpu.memory[0x6000] = ISA_OP_DEX;
|
|
cpu.memory[0x6001] = ISA_OP_INX;
|
|
cpu.pc = 0x6000;
|
|
|
|
for _ in 0..=INSTRUCTION_CYCLES(ISA_OP_DEX) { cpu.tick(); }
|
|
assert_eq!(0xaa, cpu.x);
|
|
for _ in 0..=INSTRUCTION_CYCLES(ISA_OP_INX) { cpu.tick(); }
|
|
assert_eq!(0xab, cpu.x);
|
|
}
|
|
|
|
#[test]
|
|
fn dey_iny() {
|
|
let mut cpu = Mos6502Cpu::default();
|
|
cpu.poke_y(0xab);
|
|
cpu.memory[0x6000] = ISA_OP_DEY;
|
|
cpu.memory[0x6001] = ISA_OP_INY;
|
|
cpu.pc = 0x6000;
|
|
|
|
for _ in 0..=INSTRUCTION_CYCLES(ISA_OP_DEY) { cpu.tick(); }
|
|
assert_eq!(0xaa, cpu.peek_y());
|
|
for _ in 0..=INSTRUCTION_CYCLES(ISA_OP_INY) { cpu.tick(); }
|
|
assert_eq!(0xab, cpu.peek_y());
|
|
}
|
|
|
|
#[test]
|
|
fn rol_a_ror_a() {
|
|
let mut cpu = Mos6502Cpu::default();
|
|
cpu.poke_a(0b1010_1010); // 0xaa
|
|
cpu.memory[0x6000] = ISA_OP_ROL_A;
|
|
cpu.memory[0x6001] = ISA_OP_ROR_A;
|
|
cpu.pc = 0x6000;
|
|
|
|
for _ in 0..=INSTRUCTION_CYCLES(ISA_OP_ROL_A) { cpu.tick(); }
|
|
assert_eq!(cpu.peek_a(), 0b0101_0101);
|
|
for _ in 0..=INSTRUCTION_CYCLES(ISA_OP_ROR_A) { cpu.tick(); }
|
|
assert_eq!(cpu.peek_a(), 0b1010_1010);
|
|
}
|
|
}
|