lets try clippy
This commit is contained in:
parent
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commit
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29
.idea/workspace.xml
generated
29
.idea/workspace.xml
generated
@ -7,9 +7,13 @@
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<cargoProject FILE="$PROJECT_DIR$/Cargo.toml" />
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</component>
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<component name="ChangeListManager">
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<<<<<<< Updated upstream
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<list default="true" id="9bcba7c5-ac1d-4216-959a-63faee7047bc" name="Changes" comment="">
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<change beforePath="$PROJECT_DIR$/.idea/workspace.xml" beforeDir="false" afterPath="$PROJECT_DIR$/.idea/workspace.xml" afterDir="false" />
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</list>
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=======
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<list default="true" id="9bcba7c5-ac1d-4216-959a-63faee7047bc" name="Changes" comment="" />
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>>>>>>> Stashed changes
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<option name="SHOW_DIALOG" value="false" />
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<option name="HIGHLIGHT_CONFLICTS" value="true" />
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<option name="HIGHLIGHT_NON_ACTIVE_CHANGELIST" value="false" />
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@ -54,17 +58,29 @@
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"Cargo.Build `Test chip8::video::test::poke_byte`.executor": "Run",
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"Cargo.Build `Test chip8::video::test::scroll_down_1_row_test`.executor": "Run",
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"Cargo.Build `Test computer::test`.executor": "Run",
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<<<<<<< Updated upstream
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"Cargo.Build `Test instructions::test (1)`.executor": "Run",
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"Cargo.Build `Test instructions::test`.executor": "Run",
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"Cargo.Build `Test video::test`.executor": "Run",
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"Cargo.Build gemma.executor": "Run",
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"Cargo.Run ch8asm.executor": "Run",
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=======
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"Cargo.Build `Test computer_dump_registers_to_string`.executor": "Run",
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"Cargo.Build `Test instructions::test (1)`.executor": "Run",
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"Cargo.Build `Test instructions::test`.executor": "Run",
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"Cargo.Build `Test instructions_name_tests`.executor": "Run",
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"Cargo.Build `Test video::test`.executor": "Run",
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"Cargo.Build gemma.executor": "Run",
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>>>>>>> Stashed changes
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"Cargo.Run emmagui.executor": "Run",
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"Cargo.Run gemmaegui.executor": "Debug",
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"Cargo.Run gemmaegui_viewer.executor": "Debug",
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"Cargo.Run gemmaimgui.executor": "Debug",
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"Cargo.Run trevors_chip8_toy.executor": "Debug",
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<<<<<<< Updated upstream
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"Cargo.Test ch8asm::test.executor": "Debug",
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=======
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>>>>>>> Stashed changes
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"Cargo.Test chip8::computer::test::cls_test.executor": "Run",
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"Cargo.Test chip8::computer::test::decoder_test_valid_instructions.executor": "Run",
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"Cargo.Test chip8::instructions::test::LdStVx_test.executor": "Run",
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@ -93,9 +109,17 @@
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"Cargo.Test chip8::video::test::scroll_down_1_row_test.executor": "Run",
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"Cargo.Test chip8::video::test::write_checkboard.executor": "Run",
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"Cargo.Test computer::test.executor": "Debug",
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<<<<<<< Updated upstream
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"Cargo.Test instruction_tests.executor": "Run",
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"Cargo.Test instructions::test (1).executor": "Debug",
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"Cargo.Test instructions::test.executor": "Debug",
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=======
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"Cargo.Test computer_dump_registers_to_string.executor": "Run",
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"Cargo.Test encode_decode_name_test.executor": "Debug",
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"Cargo.Test instructions::test (1).executor": "Debug",
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"Cargo.Test instructions::test.executor": "Debug",
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"Cargo.Test instructions_name_tests.executor": "Run",
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>>>>>>> Stashed changes
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"Cargo.Test sound_timer::test.executor": "Run",
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"Cargo.Test util::test.executor": "Run",
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"Cargo.Test video::test.executor": "Debug",
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@ -258,9 +282,14 @@
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<workItem from="1729353568282" duration="4624000" />
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<workItem from="1729375372050" duration="3579000" />
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<workItem from="1729797802231" duration="9220000" />
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<<<<<<< Updated upstream
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<workItem from="1729992186995" duration="4475000" />
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<workItem from="1730040713781" duration="2808000" />
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<workItem from="1730065968935" duration="6000" />
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=======
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<workItem from="1729992186995" duration="4226000" />
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<workItem from="1730115460078" duration="31140000" />
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>>>>>>> Stashed changes
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</task>
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<servers />
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</component>
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3
TODO
Normal file
3
TODO
Normal file
@ -0,0 +1,3 @@
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XOChip
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- 00DN
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- scroll screen content up N hires pixel, in XO-CHIP only selected planes are scrolled
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File diff suppressed because one or more lines are too long
@ -2,6 +2,7 @@ use log::{debug};
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use crate::chip8::delay_timer::DelayTimer;
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use crate::chip8::keypad::Keypad;
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use crate::chip8::quirk_modes::QuirkMode;
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use crate::chip8::quirk_modes::QuirkMode::Chip8;
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use crate::chip8::registers::Chip8Registers;
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use crate::chip8::sound_timer::SoundTimer;
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use crate::chip8::stack::Chip8Stack;
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@ -101,7 +102,7 @@ impl Chip8Computer {
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let low_byte = local_memory.peek(start_pc + 1) as u16;
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let result = high_byte | low_byte;
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let decoded_instruction =
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Chip8CpuInstructions::decode(result);
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Chip8CpuInstructions::decode(result, &self.quirk_mode);
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// todo: THIS IS BAD AND IS A SIDE EFFECT
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decoded_instruction.execute(self);
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@ -8,6 +8,7 @@ use rand::{random, Rng};
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use crate::chip8::computer::{Chip8Computer};
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use crate::chip8::cpu_states::Chip8CpuStates::WaitingForKey;
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use crate::chip8::instructions::Chip8CpuInstructions::*;
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use crate::chip8::quirk_modes::QuirkMode;
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use crate::chip8::util::InstructionUtil;
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use crate::constants::{*};
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@ -259,6 +260,10 @@ pub enum Chip8CpuInstructions {
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///
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/// Load V0..VX from RPL user flags (X <= 7)
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LIDR(u8),
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/// 0xBxNN
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///
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/// Jump to Address XNN+Vx
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JPX(u8, u16)
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}
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impl Chip8CpuInstructions {
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@ -308,12 +313,16 @@ impl Chip8CpuInstructions {
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Chip8CpuInstructions::DIS => INST_DIS,
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Chip8CpuInstructions::ENA => INST_ENA,
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Chip8CpuInstructions::ORY(_, _) => INST_ORY,
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JPX(_, _) => INST_JPX,
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XXXXERRORINSTRUCTION => "XX ERROR XX",
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}
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}
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pub fn operands(&self) -> String {
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match self {
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JPX(x, addr) => {
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format!("0x{x:02x}, 0x{addr:04x}")
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}
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Chip8CpuInstructions::SYS(addr) |
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Chip8CpuInstructions::JPI(addr) |
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Chip8CpuInstructions::JPA(addr) |
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@ -528,6 +537,9 @@ impl Chip8CpuInstructions {
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INST_LDD => {
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LDD(param1 as u8)
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}
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INST_JPX => {
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JPX(param1 as u8, param2)
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}
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_ => {
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XXXXERRORINSTRUCTION
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}
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@ -558,6 +570,7 @@ impl Chip8CpuInstructions {
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Chip8CpuInstructions::SNEY(x_register, y_register) => 0x9000 | ((*x_register as u16) << 8) | ((*y_register as u16) << 4),
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Chip8CpuInstructions::LDIA(addr) => 0xA000 | addr,
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Chip8CpuInstructions::JPI(addr) => 0xB000 | addr,
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JPX(x_register, addr)=> 0xB000u16 | ((*x_register as u16) << 12) | *addr ,
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Chip8CpuInstructions::RND(x_register, byte) => 0xC000 | ((*x_register as u16) << 8) | (*byte as u16),
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Chip8CpuInstructions::DRW(x_register, y_register, height) => {
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0xD000 | ((*x_register as u16) << 8) | ((*y_register as u16) << 4) | (*height as u16)
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@ -585,7 +598,7 @@ impl Chip8CpuInstructions {
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XXXXERRORINSTRUCTION => 0xFFFF
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}
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}
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pub fn decode(input: u16) -> Chip8CpuInstructions {
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pub fn decode(input: u16, quirk_mode: &QuirkMode) -> Chip8CpuInstructions {
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let x_param = InstructionUtil::read_x_from_instruction(input);
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let y_param = InstructionUtil::read_y_from_instruction(input);
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let addr_param = InstructionUtil::read_addr_from_instruction(input);
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@ -596,10 +609,35 @@ impl Chip8CpuInstructions {
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let last_nibble = (input & 0xF) as u8;
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match input {
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0x00C0..=0x00CF => Chip8CpuInstructions::SDN(last_nibble),
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0x00C0..=0x00CF => {
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match quirk_mode {
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QuirkMode::Chip8 => {
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XXXXERRORINSTRUCTION
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}
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QuirkMode::XOChip => {
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SDN(last_nibble)
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}
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QuirkMode::SChipModern => {
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SDN(last_nibble)
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}
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}
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},
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0x00E0 => Chip8CpuInstructions::CLS,
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0x00EE => Chip8CpuInstructions::RET,
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0x00FB => Chip8CpuInstructions::SRT,
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0x00FB => {
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match quirk_mode {
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QuirkMode::Chip8 => {
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// does not exist on Chip8
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XXXXERRORINSTRUCTION
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}
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QuirkMode::XOChip => {
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Chip8CpuInstructions::SRT
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}
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QuirkMode::SChipModern => {
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Chip8CpuInstructions::SRT
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}
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}
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},
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0x00FC => Chip8CpuInstructions::SLF,
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0x00FD => Chip8CpuInstructions::EXIT,
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0x00FE => Chip8CpuInstructions::DIS,
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@ -856,6 +894,12 @@ impl Chip8CpuInstructions {
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// The program counter is set to nnn plus the value of V0.
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input.registers.poke_pc(input.registers.peek(0) as u16 + addr);
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}
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// 0xBxnn Jump to Xnn+Vx
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JPX(vx_register, addr) => {
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let x_reg_value: u16 = input.registers.peek(*vx_register) as u16;
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let new_addr = *addr + x_reg_value;
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input.registers.poke_i(new_addr);
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}
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Chip8CpuInstructions::RND(x, byte) => {
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// Cxkk - RND Vx, byte
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// Set Vx = random byte AND kk.
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@ -2,7 +2,6 @@
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pub enum QuirkMode {
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#[default]
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Chip8,
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SChipLegacy,
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XOChip,
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SChipModern
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}
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@ -29,6 +29,7 @@ pub const INST_DRW: &str = "DRW";
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pub const INST_EXIT: &str = "EXIT";
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pub const INST_JPA: &str = "JPA";
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pub const INST_JPI: &str = "JPI";
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pub const INST_JPX: &str = "JPX";
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pub const INST_BCD: &str = "BCD";
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pub const INST_LDD: &str = "LDD";
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pub const INST_LDF: &str = "LDF";
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@ -6,6 +6,7 @@ use gemma::chip8::delay_timer::DelayTimer;
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use gemma::chip8::instructions::Chip8CpuInstructions;
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use gemma::chip8::instructions::Chip8CpuInstructions::JPA;
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use gemma::chip8::keypad::Keypad;
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use gemma::chip8::quirk_modes::QuirkMode::{Chip8, SChipModern, XOChip};
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use gemma::chip8::registers::Chip8Registers;
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use gemma::chip8::sound_timer::SoundTimer;
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use gemma::chip8::stack::Chip8Stack;
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@ -72,6 +73,8 @@ fn encode_decode_test() {
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assert_eq!(Chip8CpuInstructions::STR(1).encode(), 0xF175);
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assert_eq!(Chip8CpuInstructions::LIDR(1).encode(), 0xF185);
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/*
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assert!(matches!(Chip8CpuInstructions::decode(0xF175), Chip8CpuInstructions::STR(1)));
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assert!(matches!(Chip8CpuInstructions::decode(0xF185), Chip8CpuInstructions::LIDR(1)));
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assert!(matches!(Chip8CpuInstructions::decode(0x00C1u16), Chip8CpuInstructions::SDN(0x01)));
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@ -118,6 +121,7 @@ fn encode_decode_test() {
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assert!(matches!(Chip8CpuInstructions::decode(0xfd33), Chip8CpuInstructions::BCD(0xd)));
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assert!(matches!(Chip8CpuInstructions::decode(0xfe55), Chip8CpuInstructions::LDIX(0xe)));
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assert!(matches!(Chip8CpuInstructions::decode(0xf365), Chip8CpuInstructions::LDRI(0x3)));
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*/
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}
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#[test]
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@ -129,8 +133,8 @@ fn decoder_test_invalid_instructions() {
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];
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for i in invalid_to_encode {
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assert_eq!(Chip8CpuInstructions::decode(i).encode(), 0xffff);
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assert!(matches!(Chip8CpuInstructions::decode(i), Chip8CpuInstructions::XXXXERRORINSTRUCTION));
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assert_eq!(Chip8CpuInstructions::decode(i, &Chip8).encode(), 0xffff);
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assert!(matches!(Chip8CpuInstructions::decode(i, &Chip8), Chip8CpuInstructions::XXXXERRORINSTRUCTION));
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}
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}
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@ -1327,350 +1331,6 @@ fn video_scroll_right_4_row_test_high_def() {
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assert_eq!(read_test_result("test_scroll_right_4_hd.asc"), x.format_as_string());
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}
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struct InstructionTest {
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name: String,
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instruction: Chip8CpuInstructions,
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operands: String,
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asm: String,
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encoded: u16,
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}
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#[test]
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fn instructions_name_tests() {
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assert_eq!(Chip8CpuInstructions::SYS(0x0000).name(), INST_SYS);
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assert_eq!(Chip8CpuInstructions::ADD(0x0, 0x1).name(), INST_ADD);
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assert_eq!(Chip8CpuInstructions::ADDI(0x0).name(), INST_ADDI);
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assert_eq!(Chip8CpuInstructions::ADDR(0x01, 0x02).name(), INST_ADDR);
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assert_eq!(Chip8CpuInstructions::AND(0x01, 0x02).name(), INST_AND);
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let it = vec![
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InstructionTest {
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name: INST_SYS.to_string(),
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instruction: Chip8CpuInstructions::SYS(0x123),
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operands: "0x0123".to_string(),
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asm: "SYS 0x0123".to_string(),
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encoded: 0x0123
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},
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InstructionTest {
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name: INST_CLS.to_string(),
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instruction: Chip8CpuInstructions::CLS,
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asm: "CLS".to_string(),
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operands: "".to_string(),
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encoded: 0x00E0
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},
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InstructionTest {
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name: INST_RET.to_string(),
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instruction: Chip8CpuInstructions::RET,
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asm: "RET".to_string(),
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operands: "".to_string(),
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encoded: 0x00ee
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},
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InstructionTest {
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name: INST_JPA.to_string(),
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instruction: JPA(0x234),
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asm: "JPA 0x0234".to_string(),
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encoded: 0xb234,
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operands: "0x0234".to_string(),
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},
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InstructionTest {
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name: INST_CALL.to_string(),
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instruction: Chip8CpuInstructions::CALL(0x123),
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asm: "CALL 0x0123".to_string(),
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encoded: 0x2123,
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operands: "0x0123".to_string()
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},
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InstructionTest {
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name: INST_DRW.to_string(),
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instruction: Chip8CpuInstructions::DRW(0x01, 0x02, 0x03),
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operands: "0x01, 0x02, 0x03".to_string(),
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asm: "DRW 0x01, 0x02, 0x03".to_string(),
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encoded: 0xd123
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},
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InstructionTest {
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name: INST_JPI.to_string(),
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instruction: Chip8CpuInstructions::JPI(0x321),
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operands: "0x0321".to_string(),
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asm: "JPI 0x0321".to_string(),
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encoded: 0xb321
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},
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InstructionTest {
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name: INST_SDN.to_string(),
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instruction: Chip8CpuInstructions::SDN(0x01),
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operands: "0x01".to_string(),
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asm: "SDN 0x01".to_string(),
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encoded: 0x00c1
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},
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InstructionTest {
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name: INST_SRT.to_string(),
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instruction: Chip8CpuInstructions::SRT,
|
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operands: "".to_string(),
|
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asm: "SRT".to_string(),
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encoded: 0x00FB
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},
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InstructionTest {
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name: INST_SLF.to_string(),
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instruction: Chip8CpuInstructions::SLF,
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operands: "".to_string(),
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asm: "SLF".to_string(),
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encoded: 0x00FC,
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},
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InstructionTest {
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name: INST_EXIT.to_string(),
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instruction: Chip8CpuInstructions::EXIT,
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operands: "".to_string(),
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asm: "EXIT".to_string(),
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encoded: 0x00FD,
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},
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InstructionTest {
|
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name: INST_DIS.to_string(),
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instruction: Chip8CpuInstructions::DIS,
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operands: "".to_string(),
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asm: "DIS".to_string(),
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encoded: 0x00FE,
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},
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InstructionTest {
|
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name: INST_ENA.to_string(),
|
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instruction: Chip8CpuInstructions::ENA,
|
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operands: "".to_string(),
|
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asm: "ENA".to_string(),
|
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encoded: 0x00FF,
|
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},
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InstructionTest {
|
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name: INST_SEX.to_string(),
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instruction: Chip8CpuInstructions::SEX(0x01, 0xfa),
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operands: "0x01, 0xfa".to_string(),
|
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asm: "SEX 0x01, 0xfa".to_string(),
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encoded: 0x32fa,
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},
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InstructionTest {
|
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name: INST_SNEB.to_string(),
|
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instruction: Chip8CpuInstructions::SNEB(0x01, 0xab),
|
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operands: "0x01, 0xab".to_string(),
|
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asm: "SNEB 0x01, 0xab".to_string(),
|
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encoded: 0x41ab,
|
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},
|
||||
InstructionTest {
|
||||
name: INST_SEY.to_string(),
|
||||
instruction: Chip8CpuInstructions::SEY(0x1, 0x2),
|
||||
operands: "0x1, 0x2".to_string(),
|
||||
asm: "SEY 0x1, 0x2".to_string(),
|
||||
encoded: 0x5120
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDR.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDR(0xa, 0xbe),
|
||||
operands: "0x0a, 0xbe".to_string(),
|
||||
asm: "LDR 0x0a, 0xbe".to_string(),
|
||||
encoded: 0x6abe,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_ADD.to_string(),
|
||||
instruction: Chip8CpuInstructions::ADD(0x01, 0xab),
|
||||
operands: "0x01, 0xab".to_string(),
|
||||
asm: "ADD 0x01, 0xab".to_string(),
|
||||
encoded: 0x71ab
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDRY.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDR_Y(0x1, 0x2),
|
||||
operands: "0x1, 0x2".to_string(),
|
||||
asm: "LDRY 0x1, 0x2".to_string(),
|
||||
encoded: 0x8120,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_OR.to_string(),
|
||||
instruction: Chip8CpuInstructions::OR(0x1, 0x2),
|
||||
operands: "0x1, 0x2".to_string(),
|
||||
asm: "OR 0x1, 0x2".to_string(),
|
||||
encoded: 0x8121
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_AND.to_string(),
|
||||
instruction: Chip8CpuInstructions::AND(0xb, 0xc),
|
||||
operands: "0xb, 0xc".to_string(),
|
||||
asm: "AND 0xb, 0xc".to_string(),
|
||||
encoded: 0x8bc2,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_ORY.to_string(),
|
||||
instruction: Chip8CpuInstructions::ORY(0xa, 0x3),
|
||||
operands: "0xa, 0x3".to_string(),
|
||||
asm: "ORY 0xa, 0x3".to_string(),
|
||||
encoded: 0x8a33
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_ADDR.to_string(),
|
||||
instruction: Chip8CpuInstructions::ADDR(0x1, 0x2),
|
||||
operands: "0x1, 0x2".to_string(),
|
||||
asm: "ADDR 0x1, 0x2".to_string(),
|
||||
encoded: 0x8124
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_SUB.to_string(),
|
||||
instruction: Chip8CpuInstructions::SUB(0x4, 0x5),
|
||||
operands: "0x4, 0x5".to_string(),
|
||||
asm: "SUB 0x4, 0x5".to_string(),
|
||||
encoded: 0x8455
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_SHR.to_string(),
|
||||
instruction: Chip8CpuInstructions::SHR(0x01, 0x1),
|
||||
operands: "0x1, 0x1".to_string(),
|
||||
asm: "SHR 0x1, 0x1".to_string(),
|
||||
encoded: 0x8116,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_SUBC.to_string(),
|
||||
instruction: Chip8CpuInstructions::SUBC(0xf, 0xa),
|
||||
operands: "0xf, 0xa".to_string(),
|
||||
asm: "SUBC 0xf, 0xa".to_string(),
|
||||
encoded: 0x8fa7,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_SHL.to_string(),
|
||||
instruction: Chip8CpuInstructions::SHL(0x1, 0x4),
|
||||
operands: "0x1, 0x4".to_string(),
|
||||
asm: "SHL 0x1, 0x4".to_string(),
|
||||
encoded: 0x814e,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_SNEY.to_string(),
|
||||
instruction: Chip8CpuInstructions::SNEY(0x4, 0x5),
|
||||
operands: "0x4, 0x5".to_string(),
|
||||
asm: "SNEY 0x4, 0x5".to_string(),
|
||||
encoded: 0x9450,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDIA.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDIA(0xbee),
|
||||
operands: "0x0bee".to_string(),
|
||||
asm: "LDIA 0x0bee".to_string(),
|
||||
encoded: 0x9bee
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_JPI.to_string(),
|
||||
instruction: Chip8CpuInstructions::JPI(0xfee),
|
||||
operands: "0x0fee".to_string(),
|
||||
asm: "JPI 0x0fee".to_string(),
|
||||
encoded: 0xbfee
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_RND.to_string(),
|
||||
instruction: Chip8CpuInstructions::RND(0x1, 0xae),
|
||||
operands: "0x01, 0xae".to_string(),
|
||||
asm: "RND 0x01, 0xae".to_string(),
|
||||
encoded: 0xc1ae,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_DRW.to_string(),
|
||||
instruction: Chip8CpuInstructions::DRW(0x1, 0x2, 0xf),
|
||||
operands: "0x01, 0x02, 0x0f".to_string(),
|
||||
asm: "DRW 0x01, 0x02, 0x0f".to_string(),
|
||||
encoded: 0xd12f
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_SKP.to_string(),
|
||||
instruction: Chip8CpuInstructions::SKP(0x4),
|
||||
operands: "0x04".to_string(),
|
||||
asm: "SKP 0x04".to_string(),
|
||||
encoded: 0xe49e,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_SKNP.to_string(),
|
||||
instruction: Chip8CpuInstructions::SKNP(0x3),
|
||||
operands: "0x03".to_string(),
|
||||
asm: "SKNP 0x03".to_string(),
|
||||
encoded: 0x83a1
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDRD.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDRD(0x4),
|
||||
operands: "0x04".to_string(),
|
||||
asm: "LDRD 0x04".to_string(),
|
||||
encoded: 0xF407
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDRK.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDRK(0x6),
|
||||
operands: "0x06".to_string(),
|
||||
asm: "LDRK 0x06".to_string(),
|
||||
encoded: 0xF60A
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDD.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDD(0x02),
|
||||
operands: "0x02".to_string(),
|
||||
asm: "LDD 0x02".to_string(),
|
||||
encoded: 0xF215,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDRI.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDRI(0x01),
|
||||
operands: "0x01".to_string(),
|
||||
asm: "LDRI 0x01".to_string(),
|
||||
encoded: 0xF118,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_BCD.to_string(),
|
||||
instruction: Chip8CpuInstructions::BCD(0x4),
|
||||
operands: "0x04".to_string(),
|
||||
asm: "BCD 0x04".to_string(),
|
||||
encoded: 0xF433,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDF.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDFX(0x5),
|
||||
operands: "0x05".to_string(),
|
||||
asm: "LDF 0x05".to_string(),
|
||||
encoded: 0xF529
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDF2.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDF2(0x6),
|
||||
operands: "0x06".to_string(),
|
||||
asm: "LDF2 0x06".to_string(),
|
||||
encoded: 0xF630
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDIX.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDIX(0x5),
|
||||
operands: "0x05".to_string(),
|
||||
asm: "LDIX 0x05".to_string(),
|
||||
encoded: 0xF555
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDIS.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDIS(0xf),
|
||||
operands: "0x0f".to_string(),
|
||||
asm: "LDIS 0x0f".to_string(),
|
||||
encoded: 0xFF18
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LIDR.to_string(),
|
||||
instruction: Chip8CpuInstructions::LIDR(0x4),
|
||||
operands: "0x04".to_string(),
|
||||
asm: "LIDR 0x04".to_string(),
|
||||
encoded: 0xF485,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_STR.to_string(),
|
||||
instruction: Chip8CpuInstructions::STR(0xa),
|
||||
operands: "0x0a".to_string(),
|
||||
asm: "STR 0x0a".to_string(),
|
||||
encoded: 0xF000
|
||||
}
|
||||
];
|
||||
|
||||
for current in it {
|
||||
assert_eq!(current.instruction.name(), current.name);
|
||||
let i = current.instruction;
|
||||
assert!(matches!(Chip8CpuInstructions::decode(current.encoded), i));
|
||||
assert_eq!(i.to_string(), current.asm);
|
||||
let asm = Chip8CpuInstructions::from_str(¤t.asm);
|
||||
assert_eq!(i.to_string(), asm.to_string());
|
||||
assert_eq!(i.operands(), current.operands);
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn instructions_operands_tests() {
|
||||
@ -1744,11 +1404,3 @@ fn computer_dump_registers_to_string() {
|
||||
// now verify.
|
||||
assert_eq!(expected_value, x.dump_registers_to_string());
|
||||
}
|
||||
|
||||
//#[test]
|
||||
fn quirks_chip8_vf_reset_tests() {
|
||||
// vF reset - The AND, OR and XOR opcodes (8xy1, 8xy2 and 8xy3) reset the flags
|
||||
// register to zero. Test will show ERR1 if the AND and OR tests don't behave
|
||||
// the same and ERR2 if the AND and XOR tests don't behave the same.
|
||||
let mut x = Chip8Computer::new();
|
||||
}
|
||||
399
gemma/tests/unit_tests_instructions.rs
Normal file
399
gemma/tests/unit_tests_instructions.rs
Normal file
@ -0,0 +1,399 @@
|
||||
use gemma::chip8::instructions::Chip8CpuInstructions;
|
||||
use gemma::chip8::instructions::Chip8CpuInstructions::*;
|
||||
use gemma::chip8::quirk_modes::QuirkMode::{Chip8, SChipModern, XOChip};
|
||||
use gemma::constants::*;
|
||||
|
||||
struct InstructionTestQuirks {
|
||||
chip8: Chip8CpuInstructions,
|
||||
schip: Chip8CpuInstructions,
|
||||
xochip: Chip8CpuInstructions
|
||||
}
|
||||
|
||||
struct InstructionTest {
|
||||
name: String,
|
||||
instruction: Chip8CpuInstructions,
|
||||
operands: String,
|
||||
asm: String,
|
||||
encoded: u16,
|
||||
quirks: InstructionTestQuirks
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn instructions_encode_decode_tests_with_quirks() {
|
||||
let it = vec![
|
||||
InstructionTest {
|
||||
name: INST_SYS.to_string(),
|
||||
instruction: Chip8CpuInstructions::SYS(0x123),
|
||||
operands: "0x0123".to_string(),
|
||||
asm: "SYS 0x0123".to_string(),
|
||||
encoded: 0x0123,
|
||||
quirks: InstructionTestQuirks {
|
||||
chip8: SYS(0x123),
|
||||
schip: XXXXERRORINSTRUCTION,
|
||||
xochip: XXXXERRORINSTRUCTION,
|
||||
}
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_CLS.to_string(),
|
||||
instruction: Chip8CpuInstructions::CLS,
|
||||
asm: "CLS".to_string(),
|
||||
operands: "".to_string(),
|
||||
encoded: 0x00E0,
|
||||
quirks: InstructionTestQuirks {
|
||||
chip8: CLS,
|
||||
schip: CLS,
|
||||
xochip: CLS
|
||||
}
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_RET.to_string(),
|
||||
instruction: Chip8CpuInstructions::RET,
|
||||
asm: "RET".to_string(),
|
||||
operands: "".to_string(),
|
||||
encoded: 0x00ee,
|
||||
quirks: InstructionTestQuirks {
|
||||
chip8: RET,
|
||||
schip: RET,
|
||||
xochip: RET
|
||||
}
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_JPA.to_string(),
|
||||
instruction: JPA(0x234),
|
||||
asm: "JPA 0x0234".to_string(),
|
||||
encoded: 0xb234,
|
||||
operands: "0x0234".to_string(),
|
||||
quirks: InstructionTestQuirks {
|
||||
chip8: JPA(0x0234),
|
||||
schip: JPA(0x0234),
|
||||
xochip: JPA(0x0234)
|
||||
}
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_JPX.to_string(),
|
||||
instruction: Chip8CpuInstructions::JPX(0x1, 0xab),
|
||||
operands: "0x01, 0x01ab".to_string(),
|
||||
asm: "JPX 0x01, 0x01ab".to_string(),
|
||||
encoded: 0,
|
||||
quirks: InstructionTestQuirks {
|
||||
chip8: XXXXERRORINSTRUCTION,
|
||||
schip: JPX(0x1, 0xab),
|
||||
xochip: XXXXERRORINSTRUCTION,
|
||||
},
|
||||
}
|
||||
/*
|
||||
|
||||
|
||||
,
|
||||
InstructionTest {
|
||||
name: INST_CALL.to_string(),
|
||||
instruction: Chip8CpuInstructions::CALL(0x123),
|
||||
asm: "CALL 0x0123".to_string(),
|
||||
encoded: 0x2123,
|
||||
operands: "0x0123".to_string()
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_DRW.to_string(),
|
||||
instruction: Chip8CpuInstructions::DRW(0x01, 0x02, 0x03),
|
||||
operands: "0x01, 0x02, 0x03".to_string(),
|
||||
asm: "DRW 0x01, 0x02, 0x03".to_string(),
|
||||
encoded: 0xd123
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_JPI.to_string(),
|
||||
instruction: Chip8CpuInstructions::JPI(0x321),
|
||||
operands: "0x0321".to_string(),
|
||||
asm: "JPI 0x0321".to_string(),
|
||||
encoded: 0xb321
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_SDN.to_string(),
|
||||
instruction: Chip8CpuInstructions::SDN(0x01),
|
||||
operands: "0x01".to_string(),
|
||||
asm: "SDN 0x01".to_string(),
|
||||
encoded: 0x00c1
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_SRT.to_string(),
|
||||
instruction: Chip8CpuInstructions::SRT,
|
||||
operands: "".to_string(),
|
||||
asm: "SRT".to_string(),
|
||||
encoded: 0x00FB
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_SLF.to_string(),
|
||||
instruction: Chip8CpuInstructions::SLF,
|
||||
operands: "".to_string(),
|
||||
asm: "SLF".to_string(),
|
||||
encoded: 0x00FC,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_EXIT.to_string(),
|
||||
instruction: Chip8CpuInstructions::EXIT,
|
||||
operands: "".to_string(),
|
||||
asm: "EXIT".to_string(),
|
||||
encoded: 0x00FD,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_DIS.to_string(),
|
||||
instruction: Chip8CpuInstructions::DIS,
|
||||
operands: "".to_string(),
|
||||
asm: "DIS".to_string(),
|
||||
encoded: 0x00FE,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_ENA.to_string(),
|
||||
instruction: Chip8CpuInstructions::ENA,
|
||||
operands: "".to_string(),
|
||||
asm: "ENA".to_string(),
|
||||
encoded: 0x00FF,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_SEX.to_string(),
|
||||
instruction: Chip8CpuInstructions::SEX(0x01, 0xfa),
|
||||
operands: "0x01, 0xfa".to_string(),
|
||||
asm: "SEX 0x01, 0xfa".to_string(),
|
||||
encoded: 0x32fa,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_SNEB.to_string(),
|
||||
instruction: Chip8CpuInstructions::SNEB(0x01, 0xab),
|
||||
operands: "0x01, 0xab".to_string(),
|
||||
asm: "SNEB 0x01, 0xab".to_string(),
|
||||
encoded: 0x41ab,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_SEY.to_string(),
|
||||
instruction: Chip8CpuInstructions::SEY(0x1, 0x2),
|
||||
operands: "0x1, 0x2".to_string(),
|
||||
asm: "SEY 0x1, 0x2".to_string(),
|
||||
encoded: 0x5120
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDR.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDR(0xa, 0xbe),
|
||||
operands: "0x0a, 0xbe".to_string(),
|
||||
asm: "LDR 0x0a, 0xbe".to_string(),
|
||||
encoded: 0x6abe,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_ADD.to_string(),
|
||||
instruction: Chip8CpuInstructions::ADD(0x01, 0xab),
|
||||
operands: "0x01, 0xab".to_string(),
|
||||
asm: "ADD 0x01, 0xab".to_string(),
|
||||
encoded: 0x71ab
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDRY.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDR_Y(0x1, 0x2),
|
||||
operands: "0x1, 0x2".to_string(),
|
||||
asm: "LDRY 0x1, 0x2".to_string(),
|
||||
encoded: 0x8120,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_OR.to_string(),
|
||||
instruction: Chip8CpuInstructions::OR(0x1, 0x2),
|
||||
operands: "0x1, 0x2".to_string(),
|
||||
asm: "OR 0x1, 0x2".to_string(),
|
||||
encoded: 0x8121
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_AND.to_string(),
|
||||
instruction: Chip8CpuInstructions::AND(0xb, 0xc),
|
||||
operands: "0xb, 0xc".to_string(),
|
||||
asm: "AND 0xb, 0xc".to_string(),
|
||||
encoded: 0x8bc2,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_ORY.to_string(),
|
||||
instruction: Chip8CpuInstructions::ORY(0xa, 0x3),
|
||||
operands: "0xa, 0x3".to_string(),
|
||||
asm: "ORY 0xa, 0x3".to_string(),
|
||||
encoded: 0x8a33
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_ADDR.to_string(),
|
||||
instruction: Chip8CpuInstructions::ADDR(0x1, 0x2),
|
||||
operands: "0x1, 0x2".to_string(),
|
||||
asm: "ADDR 0x1, 0x2".to_string(),
|
||||
encoded: 0x8124
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_SUB.to_string(),
|
||||
instruction: Chip8CpuInstructions::SUB(0x4, 0x5),
|
||||
operands: "0x4, 0x5".to_string(),
|
||||
asm: "SUB 0x4, 0x5".to_string(),
|
||||
encoded: 0x8455
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_SHR.to_string(),
|
||||
instruction: Chip8CpuInstructions::SHR(0x01, 0x1),
|
||||
operands: "0x1, 0x1".to_string(),
|
||||
asm: "SHR 0x1, 0x1".to_string(),
|
||||
encoded: 0x8116,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_SUBC.to_string(),
|
||||
instruction: Chip8CpuInstructions::SUBC(0xf, 0xa),
|
||||
operands: "0xf, 0xa".to_string(),
|
||||
asm: "SUBC 0xf, 0xa".to_string(),
|
||||
encoded: 0x8fa7,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_SHL.to_string(),
|
||||
instruction: Chip8CpuInstructions::SHL(0x1, 0x4),
|
||||
operands: "0x1, 0x4".to_string(),
|
||||
asm: "SHL 0x1, 0x4".to_string(),
|
||||
encoded: 0x814e,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_SNEY.to_string(),
|
||||
instruction: Chip8CpuInstructions::SNEY(0x4, 0x5),
|
||||
operands: "0x4, 0x5".to_string(),
|
||||
asm: "SNEY 0x4, 0x5".to_string(),
|
||||
encoded: 0x9450,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDIA.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDIA(0xbee),
|
||||
operands: "0x0bee".to_string(),
|
||||
asm: "LDIA 0x0bee".to_string(),
|
||||
encoded: 0x9bee
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_JPI.to_string(),
|
||||
instruction: Chip8CpuInstructions::JPI(0xfee),
|
||||
operands: "0x0fee".to_string(),
|
||||
asm: "JPI 0x0fee".to_string(),
|
||||
encoded: 0xbfee
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_RND.to_string(),
|
||||
instruction: Chip8CpuInstructions::RND(0x1, 0xae),
|
||||
operands: "0x01, 0xae".to_string(),
|
||||
asm: "RND 0x01, 0xae".to_string(),
|
||||
encoded: 0xc1ae,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_DRW.to_string(),
|
||||
instruction: Chip8CpuInstructions::DRW(0x1, 0x2, 0xf),
|
||||
operands: "0x01, 0x02, 0x0f".to_string(),
|
||||
asm: "DRW 0x01, 0x02, 0x0f".to_string(),
|
||||
encoded: 0xd12f
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_SKP.to_string(),
|
||||
instruction: Chip8CpuInstructions::SKP(0x4),
|
||||
operands: "0x04".to_string(),
|
||||
asm: "SKP 0x04".to_string(),
|
||||
encoded: 0xe49e,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_SKNP.to_string(),
|
||||
instruction: Chip8CpuInstructions::SKNP(0x3),
|
||||
operands: "0x03".to_string(),
|
||||
asm: "SKNP 0x03".to_string(),
|
||||
encoded: 0x83a1
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDRD.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDRD(0x4),
|
||||
operands: "0x04".to_string(),
|
||||
asm: "LDRD 0x04".to_string(),
|
||||
encoded: 0xF407
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDRK.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDRK(0x6),
|
||||
operands: "0x06".to_string(),
|
||||
asm: "LDRK 0x06".to_string(),
|
||||
encoded: 0xF60A
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDD.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDD(0x02),
|
||||
operands: "0x02".to_string(),
|
||||
asm: "LDD 0x02".to_string(),
|
||||
encoded: 0xF215,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDRI.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDRI(0x01),
|
||||
operands: "0x01".to_string(),
|
||||
asm: "LDRI 0x01".to_string(),
|
||||
encoded: 0xF118,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_BCD.to_string(),
|
||||
instruction: Chip8CpuInstructions::BCD(0x4),
|
||||
operands: "0x04".to_string(),
|
||||
asm: "BCD 0x04".to_string(),
|
||||
encoded: 0xF433,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDF.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDFX(0x5),
|
||||
operands: "0x05".to_string(),
|
||||
asm: "LDF 0x05".to_string(),
|
||||
encoded: 0xF529
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDF2.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDF2(0x6),
|
||||
operands: "0x06".to_string(),
|
||||
asm: "LDF2 0x06".to_string(),
|
||||
encoded: 0xF630
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDIX.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDIX(0x5),
|
||||
operands: "0x05".to_string(),
|
||||
asm: "LDIX 0x05".to_string(),
|
||||
encoded: 0xF555
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LDIS.to_string(),
|
||||
instruction: Chip8CpuInstructions::LDIS(0xf),
|
||||
operands: "0x0f".to_string(),
|
||||
asm: "LDIS 0x0f".to_string(),
|
||||
encoded: 0xFF18
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_LIDR.to_string(),
|
||||
instruction: Chip8CpuInstructions::LIDR(0x4),
|
||||
operands: "0x04".to_string(),
|
||||
asm: "LIDR 0x04".to_string(),
|
||||
encoded: 0xF485,
|
||||
},
|
||||
InstructionTest {
|
||||
name: INST_STR.to_string(),
|
||||
instruction: Chip8CpuInstructions::STR(0xa),
|
||||
operands: "0x0a".to_string(),
|
||||
asm: "STR 0x0a".to_string(),
|
||||
encoded: 0xF000
|
||||
}
|
||||
*/
|
||||
];
|
||||
|
||||
for current in it {
|
||||
assert_eq!(current.instruction.name(), current.name);
|
||||
let i = current.instruction;
|
||||
assert!(matches!(Chip8CpuInstructions::decode(current.encoded, &Chip8), i));
|
||||
assert_eq!(i.to_string(), current.asm);
|
||||
let asm = Chip8CpuInstructions::from_str(¤t.asm);
|
||||
assert_eq!(i.to_string(), asm.to_string());
|
||||
assert_eq!(i.operands(), current.operands);
|
||||
// test quirks
|
||||
let as_chip8 = Chip8CpuInstructions::decode(current.encoded, &Chip8);
|
||||
let quirks_chip8 = current.quirks.chip8;
|
||||
let as_schip = Chip8CpuInstructions::decode(current.encoded, &SChipModern);
|
||||
let quirks_schip = current.quirks.schip;
|
||||
let as_xochip = Chip8CpuInstructions::decode(current.encoded, &XOChip);
|
||||
let quirks_xochip = current.quirks.xochip;
|
||||
|
||||
assert!(matches!(as_chip8, quirks_chip8));
|
||||
assert!(matches!(as_schip, quirks_schip));
|
||||
assert!(matches!(as_xochip, quirks_xochip));
|
||||
|
||||
}
|
||||
}
|
||||
@ -2,6 +2,7 @@ use std::path::Path;
|
||||
use clap::{command, Parser};
|
||||
use gemma::chip8::instructions::Chip8CpuInstructions;
|
||||
use gemma::chip8::instructions::Chip8CpuInstructions::XXXXERRORINSTRUCTION;
|
||||
use gemma::chip8::quirk_modes::QuirkMode::Chip8;
|
||||
|
||||
/// ch8disasm
|
||||
///
|
||||
@ -26,7 +27,7 @@ impl Disassembler {
|
||||
for (offset, byte) in from_data.iter().enumerate() {
|
||||
working_instruction = (working_instruction << 8) | (*byte as u16);
|
||||
if offset % 2 != 0 {
|
||||
let decoded = Chip8CpuInstructions::decode(working_instruction);
|
||||
let decoded = Chip8CpuInstructions::decode(working_instruction, &Chip8);
|
||||
let decoded_string = decoded.to_string();
|
||||
let mut current_parts = String::new();
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user