adds better handling for invalid instructions
adds tests for invalid instructions adds tarpaulin for generating coverage
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5
.cargo/config.toml
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5
.cargo/config.toml
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@ -0,0 +1,5 @@
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[alias]
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coverage = "tarpaulin --out Html --skip-clean"
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[build]
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rustc-wrapper = "sccache"
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@ -102,9 +102,30 @@ mod test {
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#[test]
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fn decoder_test_invalid_instructions() {
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// 'bad' instructions that should be dropped...
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// assert!(matches!(Chip8Computer::decode_instruction(0x5ab1), Chip8CpuInstructions::XXXXERRORINSTRUCTION));
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// assert!(matches!(Chip8Computer::decode_instruction(0x8ab8), Chip8CpuInstructions::XXXXERRORINSTRUCTION));
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// assert!(matches!(Chip8Computer::decode_instruction(0xeaba), Chip8CpuInstructions::XXXXERRORINSTRUCTION));
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// 5xy0 is the only valid 5 series.
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assert!(matches!(Chip8CpuInstructions::decode(0x5ab1), Chip8CpuInstructions::XXXXERRORINSTRUCTION));
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assert!(matches!(Chip8CpuInstructions::decode(0x5abf), Chip8CpuInstructions::XXXXERRORINSTRUCTION));
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// 8__8 -> 8__D and 8__F are invalid
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assert!(matches!(Chip8CpuInstructions::decode(0x8ab8), Chip8CpuInstructions::XXXXERRORINSTRUCTION));
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assert!(matches!(Chip8CpuInstructions::decode(0x8abd), Chip8CpuInstructions::XXXXERRORINSTRUCTION));
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assert!(matches!(Chip8CpuInstructions::decode(0x8abf), Chip8CpuInstructions::XXXXERRORINSTRUCTION));
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// 9__1 -> 9__F are invalid
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assert!(matches!(Chip8CpuInstructions::decode(0x9ab1), Chip8CpuInstructions::XXXXERRORINSTRUCTION));
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assert!(matches!(Chip8CpuInstructions::decode(0x9abf), Chip8CpuInstructions::XXXXERRORINSTRUCTION));
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// Only valid E suffixes are 9E and A1
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assert!(matches!(Chip8CpuInstructions::decode(0xea9d), Chip8CpuInstructions::XXXXERRORINSTRUCTION));
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assert!(matches!(Chip8CpuInstructions::decode(0xea9f), Chip8CpuInstructions::XXXXERRORINSTRUCTION));
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assert!(matches!(Chip8CpuInstructions::decode(0xeaa0), Chip8CpuInstructions::XXXXERRORINSTRUCTION));
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assert!(matches!(Chip8CpuInstructions::decode(0xeaa2), Chip8CpuInstructions::XXXXERRORINSTRUCTION));
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// oh god f is a mess.
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assert!(matches!(Chip8CpuInstructions::decode(0xf006), Chip8CpuInstructions::XXXXERRORINSTRUCTION));
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assert!(matches!(Chip8CpuInstructions::decode(0xf008), Chip8CpuInstructions::XXXXERRORINSTRUCTION));
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}
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#[test]
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@ -120,6 +141,9 @@ mod test {
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let test_computer = Chip8Computer::new_with_program(new_program);
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// ...and check the registers
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// let (high, low) = InstructionUtil::split_bytes(Chip8CpuInstructions::LdVxI(0x10).encode());
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// assert_eq!(test_computer.memory.peek(0x200), high);
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// assert_eq!(test_computer.memory.peek(0x201), low);
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}
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}
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@ -1,3 +1,4 @@
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use imgui::ColorPicker3;
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use log::debug;
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use rand::random;
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use crate::chip8::computer::{Chip8Computer};
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@ -213,7 +214,13 @@ impl Chip8CpuInstructions {
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0x5000..=0x5FF0 => {
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// 5xy0 - SE Vx, Vy
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// Skip next instruction if Vx = Vy.
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Chip8CpuInstructions::SeVxVy(x_param, y_param)
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// if the last nibble isn't 0...
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if 0xf & input > 0 {
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// ... we have a problem.
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Chip8CpuInstructions::XXXXERRORINSTRUCTION
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} else {
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Chip8CpuInstructions::SeVxVy(x_param, y_param)
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}
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}
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0x6000..=0x6FFF => {
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// 6xkk - LD Vx, byte
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@ -265,13 +272,17 @@ impl Chip8CpuInstructions {
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Chip8CpuInstructions::ShlVxVy(x_param, y_param)
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}
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_ => {
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panic!("UNABLE TO DECODE 0x8000 SERIES INSTRUCTION");
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Chip8CpuInstructions::XXXXERRORINSTRUCTION
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}
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}
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}
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0x9000..=0x9FF0 => {
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// SNE Vx, Vy
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Chip8CpuInstructions::SneVxVy(x_param, y_param)
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if 0xf & input > 0 {
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XXXXERRORINSTRUCTION
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} else {
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Chip8CpuInstructions::SneVxVy(x_param, y_param)
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}
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}
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0xA000..=0xAFFF => {
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// LD I, Addr
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