more unit tests working.
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@ -18,7 +18,7 @@ y - A 4-bit value, the upper 4 bits of the low byte of the instruction
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kk or byte - An 8-bit value, the lowest 8 bits of the instruction
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kk or byte - An 8-bit value, the lowest 8 bits of the instruction
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*/
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*/
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#[derive(Debug)]
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#[derive(Debug, Clone)]
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pub enum Chip8CpuInstructions {
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pub enum Chip8CpuInstructions {
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/// 0nnn
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/// 0nnn
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/// Exit to System Call at nnn
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/// Exit to System Call at nnn
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@ -222,26 +222,26 @@ pub enum Chip8CpuInstructions {
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LDRI(u8),
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LDRI(u8),
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XXXXERRORINSTRUCTION,
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XXXXERRORINSTRUCTION,
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/* START OF SCHIP-8 */
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/* START OF SCHIP-8 */
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/// 00CN
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/// 00CN - CHIP8 * SCHIP * XOCHIP
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///
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///
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/// Scrolll Display N Lines Down
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/// Scrolll Display N Lines Down
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SDN(u8),
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SCD(u8),
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/// 00FB
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/// 00FB
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///
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///
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/// Scroll 4 lines Right
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/// Scroll 4 lines Right
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SRT,
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SCR,
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/// 00FC
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/// 00FC
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///
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///
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/// Scroll 4 lines Left
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/// Scroll 4 lines Left
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SLF,
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SCL,
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/// 00FE
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/// 00FE
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///
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///
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/// Disable Extended Mode
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/// Disable Extended Mode
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DIS,
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LOW,
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/// 00FF
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/// 00FF
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///
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///
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/// Enable Extended Mode
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/// Enable Extended Mode
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ENA,
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HIGH,
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/// 00FD
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/// 00FD
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///
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///
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/// Exit App
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/// Exit App
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@ -293,9 +293,9 @@ impl Chip8CpuInstructions {
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Chip8CpuInstructions::OR(_, _) => INST_OR,
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Chip8CpuInstructions::OR(_, _) => INST_OR,
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Chip8CpuInstructions::RET => INST_RET,
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Chip8CpuInstructions::RET => INST_RET,
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Chip8CpuInstructions::RND(_, _) => INST_RND,
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Chip8CpuInstructions::RND(_, _) => INST_RND,
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Chip8CpuInstructions::SDN(_) => INST_SDN,
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Chip8CpuInstructions::SCD(_) => INST_SCD,
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Chip8CpuInstructions::SLF => INST_SLF,
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Chip8CpuInstructions::SCL => INST_SCL,
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Chip8CpuInstructions::SRT => INST_SRT,
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Chip8CpuInstructions::SCR => INST_SCR,
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Chip8CpuInstructions::SEX(_, _) => INST_SEX,
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Chip8CpuInstructions::SEX(_, _) => INST_SEX,
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Chip8CpuInstructions::SEY(_, _) => INST_SEY,
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Chip8CpuInstructions::SEY(_, _) => INST_SEY,
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Chip8CpuInstructions::SHL(_, _) => INST_SHL,
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Chip8CpuInstructions::SHL(_, _) => INST_SHL,
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@ -308,8 +308,8 @@ impl Chip8CpuInstructions {
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Chip8CpuInstructions::SUB(_, _) => INST_SUB,
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Chip8CpuInstructions::SUB(_, _) => INST_SUB,
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Chip8CpuInstructions::SUBC(_, _) => INST_SUBC,
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Chip8CpuInstructions::SUBC(_, _) => INST_SUBC,
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Chip8CpuInstructions::SYS(_) => INST_SYS,
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Chip8CpuInstructions::SYS(_) => INST_SYS,
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Chip8CpuInstructions::DIS => INST_DIS,
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Chip8CpuInstructions::LOW => INST_LOW,
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Chip8CpuInstructions::ENA => INST_ENA,
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Chip8CpuInstructions::HIGH => INST_HIGH,
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Chip8CpuInstructions::ORY(_, _) => INST_ORY,
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Chip8CpuInstructions::ORY(_, _) => INST_ORY,
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JPX(_, _) => INST_JPX,
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JPX(_, _) => INST_JPX,
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XXXXERRORINSTRUCTION => "XX ERROR XX",
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XXXXERRORINSTRUCTION => "XX ERROR XX",
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@ -319,7 +319,8 @@ impl Chip8CpuInstructions {
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pub fn operands(&self) -> String {
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pub fn operands(&self) -> String {
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match self {
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match self {
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JPX(x, addr) => {
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JPX(x, addr) => {
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format!("0x{x:02x}, 0x{addr:04x}")
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let addr_for_display = (*x as u16 ) << 8 | *addr;
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format!("0x{x:02x}, 0x{addr_for_display:04x}")
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}
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}
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Chip8CpuInstructions::SYS(addr) |
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Chip8CpuInstructions::SYS(addr) |
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Chip8CpuInstructions::JPI(addr) |
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Chip8CpuInstructions::JPI(addr) |
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@ -366,17 +367,17 @@ impl Chip8CpuInstructions {
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Chip8CpuInstructions::LDF2(x) |
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Chip8CpuInstructions::LDF2(x) |
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Chip8CpuInstructions::STR(x) |
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Chip8CpuInstructions::STR(x) |
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Chip8CpuInstructions::LIDR(x) |
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Chip8CpuInstructions::LIDR(x) |
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Chip8CpuInstructions::SDN(x) |
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Chip8CpuInstructions::SCD(x) |
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Chip8CpuInstructions::SKNP(x) |
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Chip8CpuInstructions::SKNP(x) |
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Chip8CpuInstructions::SKP(x) => {
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Chip8CpuInstructions::SKP(x) => {
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format!("0x{x:02x}")
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format!("0x{x:02x}")
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}
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}
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Chip8CpuInstructions::EXIT |
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Chip8CpuInstructions::EXIT |
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Chip8CpuInstructions::ENA |
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Chip8CpuInstructions::HIGH |
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Chip8CpuInstructions::DIS |
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Chip8CpuInstructions::LOW |
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Chip8CpuInstructions::SLF |
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Chip8CpuInstructions::SCL |
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Chip8CpuInstructions::XXXXERRORINSTRUCTION |
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Chip8CpuInstructions::XXXXERRORINSTRUCTION |
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Chip8CpuInstructions::SRT |
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Chip8CpuInstructions::SCR |
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Chip8CpuInstructions::CLS |
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Chip8CpuInstructions::CLS |
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Chip8CpuInstructions::RET => {
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Chip8CpuInstructions::RET => {
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String::new()
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String::new()
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@ -406,15 +407,18 @@ impl Chip8CpuInstructions {
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let param3 = u16::from_str_radix(parts.next().unwrap_or("0").trim_start_matches("0x").trim_end_matches(","), 16).unwrap_or(0);
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let param3 = u16::from_str_radix(parts.next().unwrap_or("0").trim_start_matches("0x").trim_end_matches(","), 16).unwrap_or(0);
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// println!("\tFirst part is {:?} / {:?} / {:?} / {:?}", first_part, param1 ,param2 ,param3);
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// println!("\tFirst part is {:?} / {:?} / {:?} / {:?}", first_part, param1 ,param2 ,param3);
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match first_part {
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match first_part {
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INST_ADDI => {
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ADDI(param1 as u8)
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}
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INST_ADD => {
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ADD(param1 as u8, param2 as u8)
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}
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INST_CLS => {
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INST_CLS => {
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CLS
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CLS
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}
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}
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INST_DRW => {
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INST_DRW => {
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DRW(param1 as u8, param2 as u8, param3 as u8)
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DRW(param1 as u8, param2 as u8, param3 as u8)
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}
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}
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INST_ADD => {
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ADD(param1 as u8, param2 as u8)
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}
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INST_CALL => {
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INST_CALL => {
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CALL(param1)
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CALL(param1)
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}
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}
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@ -436,23 +440,23 @@ impl Chip8CpuInstructions {
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INST_SNEB => {
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INST_SNEB => {
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SNEB(param1 as u8, param2 as u8)
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SNEB(param1 as u8, param2 as u8)
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}
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}
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INST_SDN => {
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INST_SCD => {
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SDN(param1 as u8)
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SCD(param1 as u8)
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}
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}
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INST_SRT => {
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INST_STR => {
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SRT
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STR(param1 as u8)
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}
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}
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INST_SLF => {
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INST_SCL => {
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SLF
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SCL
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}
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}
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INST_EXIT => {
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INST_EXIT => {
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EXIT
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EXIT
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}
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}
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INST_DIS => {
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INST_LOW => {
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DIS
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LOW
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}
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}
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INST_ENA => {
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INST_HIGH => {
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ENA
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HIGH
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}
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}
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INST_SEY => {
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INST_SEY => {
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SEY(param1 as u8, param2 as u8)
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SEY(param1 as u8, param2 as u8)
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@ -568,7 +572,7 @@ impl Chip8CpuInstructions {
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Chip8CpuInstructions::SNEY(x_register, y_register) => 0x9000 | ((*x_register as u16) << 8) | ((*y_register as u16) << 4),
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Chip8CpuInstructions::SNEY(x_register, y_register) => 0x9000 | ((*x_register as u16) << 8) | ((*y_register as u16) << 4),
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Chip8CpuInstructions::LDIA(addr) => 0xA000 | addr,
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Chip8CpuInstructions::LDIA(addr) => 0xA000 | addr,
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Chip8CpuInstructions::JPI(addr) => 0xB000 | addr,
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Chip8CpuInstructions::JPI(addr) => 0xB000 | addr,
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JPX(x_register, addr)=> 0xB000u16 | ((*x_register as u16) << 12) | *addr ,
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JPX(x_register, addr)=> (0xb000 | (*x_register as u16) << 8) | *addr,
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Chip8CpuInstructions::RND(x_register, byte) => 0xC000 | ((*x_register as u16) << 8) | (*byte as u16),
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Chip8CpuInstructions::RND(x_register, byte) => 0xC000 | ((*x_register as u16) << 8) | (*byte as u16),
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Chip8CpuInstructions::DRW(x_register, y_register, height) => {
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Chip8CpuInstructions::DRW(x_register, y_register, height) => {
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0xD000 | ((*x_register as u16) << 8) | ((*y_register as u16) << 4) | (*height as u16)
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0xD000 | ((*x_register as u16) << 8) | ((*y_register as u16) << 4) | (*height as u16)
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@ -584,11 +588,11 @@ impl Chip8CpuInstructions {
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Chip8CpuInstructions::BCD(x_register) => 0xF033 | ((*x_register as u16) << 8),
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Chip8CpuInstructions::BCD(x_register) => 0xF033 | ((*x_register as u16) << 8),
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Chip8CpuInstructions::LDIX(x_register) => 0xF055 | ((*x_register as u16) << 8),
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Chip8CpuInstructions::LDIX(x_register) => 0xF055 | ((*x_register as u16) << 8),
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Chip8CpuInstructions::LDRI(x_register) => 0xF065 | ((*x_register as u16) << 8),
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Chip8CpuInstructions::LDRI(x_register) => 0xF065 | ((*x_register as u16) << 8),
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Chip8CpuInstructions::SDN(x_register) => 0x00C0 | (*x_register as u16),
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Chip8CpuInstructions::SCD(x_register) => 0x00C0 | (*x_register as u16),
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Chip8CpuInstructions::SRT => 0x00FB,
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Chip8CpuInstructions::SCR => 0x00FB,
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Chip8CpuInstructions::SLF => 0x00FC,
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Chip8CpuInstructions::SCL => 0x00FC,
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Chip8CpuInstructions::DIS => 0x00FE,
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Chip8CpuInstructions::LOW => 0x00FE,
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Chip8CpuInstructions::ENA => 0x00FF,
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Chip8CpuInstructions::HIGH => 0x00FF,
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Chip8CpuInstructions::EXIT => 0x00FD,
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Chip8CpuInstructions::EXIT => 0x00FD,
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Chip8CpuInstructions::LDF2(x_register) => 0xF030 | ((*x_register as u16) << 8),
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Chip8CpuInstructions::LDF2(x_register) => 0xF030 | ((*x_register as u16) << 8),
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Chip8CpuInstructions::STR(x_register) => 0xF075 | ((*x_register as u16) << 8),
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Chip8CpuInstructions::STR(x_register) => 0xF075 | ((*x_register as u16) << 8),
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@ -613,10 +617,10 @@ impl Chip8CpuInstructions {
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XXXXERRORINSTRUCTION
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XXXXERRORINSTRUCTION
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}
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}
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QuirkMode::XOChip => {
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QuirkMode::XOChip => {
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SDN(last_nibble)
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SCD(last_nibble)
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}
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}
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QuirkMode::SChipModern => {
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QuirkMode::SChipModern => {
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SDN(last_nibble)
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SCD(last_nibble)
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}
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}
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}
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}
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},
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},
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@ -629,25 +633,54 @@ impl Chip8CpuInstructions {
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XXXXERRORINSTRUCTION
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XXXXERRORINSTRUCTION
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}
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}
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QuirkMode::XOChip => {
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QuirkMode::XOChip => {
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Chip8CpuInstructions::SRT
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Chip8CpuInstructions::SCR
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}
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}
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QuirkMode::SChipModern => {
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QuirkMode::SChipModern => {
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Chip8CpuInstructions::SRT
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Chip8CpuInstructions::SCR
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}
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}
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}
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}
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},
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},
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0x00FC => Chip8CpuInstructions::SLF,
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0x00FC => Chip8CpuInstructions::SCL,
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0x00FD => Chip8CpuInstructions::EXIT,
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0x00FD => Chip8CpuInstructions::EXIT,
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0x00FE => Chip8CpuInstructions::DIS,
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0x00FE => {
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0x00FF => Chip8CpuInstructions::ENA,
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match quirk_mode {
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0x0000..=0x0FFF => Chip8CpuInstructions::SYS(addr_param),
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QuirkMode::Chip8 => {
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0x1000..=0x1FFF => Chip8CpuInstructions::JPA(addr_param),
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XXXXERRORINSTRUCTION
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0x2000..=0x2FFF => Chip8CpuInstructions::CALL(addr_param),
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}
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0x3000..=0x3FFF => Chip8CpuInstructions::SEX(x_param, byte_param),
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QuirkMode::XOChip |
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0x4000..=0x4FFF => Chip8CpuInstructions::SNEB(x_param, byte_param),
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QuirkMode::SChipModern => {
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0x5000..=0x5FF0 if input & 0x01 == 0 => Chip8CpuInstructions::SEY(x_param, y_param),
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LOW
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0x6000..=0x6FFF => Chip8CpuInstructions::LDR(x_param, byte_param),
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}
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0x7000..=0x7FFF => Chip8CpuInstructions::ADD(x_param, byte_param),
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}
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},
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0x00FF => {
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match quirk_mode {
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QuirkMode::Chip8 => {
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XXXXERRORINSTRUCTION
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},
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QuirkMode::XOChip |
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QuirkMode::SChipModern => {
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HIGH
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}
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}
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},
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0x0000..=0x0FFF => {
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match quirk_mode {
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QuirkMode::Chip8 => {
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Chip8CpuInstructions::SYS(addr_param)
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}
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QuirkMode::XOChip | QuirkMode::SChipModern => {
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XXXXERRORINSTRUCTION
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}
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}
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},
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0x1000..=0x1FFF => JPA(addr_param),
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0x2000..=0x2FFF => CALL(addr_param),
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0x3000..=0x3FFF => SEX(x_param, byte_param),
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0x4000..=0x4FFF => SNEB(x_param, byte_param),
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0x5000..=0x5FF0 if input & 0x01 == 0 => SEY(x_param, y_param),
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0x6000..=0x6FFF => LDR(x_param, byte_param),
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0x7000..=0x7FFF => ADD(x_param, byte_param),
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0x8000..=0x8FFE => match last_nibble {
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0x8000..=0x8FFE => match last_nibble {
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0x0 => Chip8CpuInstructions::LDR_Y(x_param, y_param),
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0x0 => Chip8CpuInstructions::LDR_Y(x_param, y_param),
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0x1 => Chip8CpuInstructions::OR(x_param, y_param),
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0x1 => Chip8CpuInstructions::OR(x_param, y_param),
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@ -1088,19 +1121,36 @@ impl Chip8CpuInstructions {
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input.registers.poke_i(offset + 1);
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input.registers.poke_i(offset + 1);
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}
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}
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Chip8CpuInstructions::XXXXERRORINSTRUCTION => {}
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Chip8CpuInstructions::XXXXERRORINSTRUCTION => {}
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Chip8CpuInstructions::SDN(x) => {
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Chip8CpuInstructions::SCD(x) => {
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input.video_memory.scroll_down(*x as i32);
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match input.quirk_mode {
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QuirkMode::Chip8 => {
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panic!("Attempt to execute SCD in Chip8 Mode");
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}
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}
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Chip8CpuInstructions::SRT => {
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QuirkMode::XOChip |
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QuirkMode::SChipModern => {
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input.video_memory.scroll_down(*x as i32);
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}
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}
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}
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Chip8CpuInstructions::SCR => {
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match input.quirk_mode {
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QuirkMode::Chip8 => {
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// panic!("Attempt to execute SCR in Chip8 Mode");
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}
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QuirkMode::XOChip |
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QuirkMode::SChipModern => {
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input.video_memory.scroll_right();
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input.video_memory.scroll_right();
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}
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}
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Chip8CpuInstructions::SLF => {
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}
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}
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Chip8CpuInstructions::SCL => {
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input.video_memory.scroll_left();
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input.video_memory.scroll_left();
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}
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}
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Chip8CpuInstructions::DIS => {
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Chip8CpuInstructions::LOW => {
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input.video_memory.set_lowres();
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input.video_memory.set_lowres();
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}
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}
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Chip8CpuInstructions::ENA => {
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Chip8CpuInstructions::HIGH => {
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input.video_memory.set_highres();
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input.video_memory.set_highres();
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}
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}
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Chip8CpuInstructions::EXIT => {
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Chip8CpuInstructions::EXIT => {
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@ -46,9 +46,9 @@ pub const INST_LDRY: &str = "LDRY";
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pub const INST_OR: &str = "OR";
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pub const INST_OR: &str = "OR";
|
||||||
pub const INST_RET: &str = "RET";
|
pub const INST_RET: &str = "RET";
|
||||||
pub const INST_RND: &str = "RND";
|
pub const INST_RND: &str = "RND";
|
||||||
pub const INST_SDN: &str = "SDN";
|
pub const INST_SCD: &str = "SCD";
|
||||||
pub const INST_SRT: &str = "SRT";
|
pub const INST_SCR: &str = "SCR";
|
||||||
pub const INST_SLF: &str = "SLF";
|
pub const INST_SCL: &str = "SCL";
|
||||||
pub const INST_SEX: &str = "SEX";
|
pub const INST_SEX: &str = "SEX";
|
||||||
pub const INST_SEY: &str = "SEY";
|
pub const INST_SEY: &str = "SEY";
|
||||||
pub const INST_SHL: &str = "SHL";
|
pub const INST_SHL: &str = "SHL";
|
||||||
@ -61,8 +61,8 @@ pub const INST_STR: &str = "STR";
|
|||||||
pub const INST_SUB: &str = "SUB";
|
pub const INST_SUB: &str = "SUB";
|
||||||
pub const INST_SUBC: &str = "SUBC";
|
pub const INST_SUBC: &str = "SUBC";
|
||||||
pub const INST_SYS: &str = "SYS";
|
pub const INST_SYS: &str = "SYS";
|
||||||
pub const INST_DIS: &str = "DIS";
|
pub const INST_LOW: &str = "LOW";
|
||||||
pub const INST_ENA: &str = "ENA";
|
pub const INST_HIGH: &str = "HIGH";
|
||||||
pub const INST_ORY: &str = "ORY";
|
pub const INST_ORY: &str = "ORY";
|
||||||
|
|
||||||
pub const CHIP8_PROGRAM_LOAD_OFFSET: i32 = 0x200;
|
pub const CHIP8_PROGRAM_LOAD_OFFSET: i32 = 0x200;
|
||||||
|
|||||||
@ -61,12 +61,12 @@ fn encode_decode_test() {
|
|||||||
assert_eq!(Chip8CpuInstructions::BCD(0xd).encode(), 0xfd33);
|
assert_eq!(Chip8CpuInstructions::BCD(0xd).encode(), 0xfd33);
|
||||||
assert_eq!(Chip8CpuInstructions::LDIX(0xe).encode(), 0xfe55);
|
assert_eq!(Chip8CpuInstructions::LDIX(0xe).encode(), 0xfe55);
|
||||||
assert_eq!(Chip8CpuInstructions::LDRI(0x3).encode(), 0xf365);
|
assert_eq!(Chip8CpuInstructions::LDRI(0x3).encode(), 0xf365);
|
||||||
assert_eq!(Chip8CpuInstructions::SDN(0x1).encode(), 0x00C1);
|
assert_eq!(Chip8CpuInstructions::SCD(0x1).encode(), 0x00C1);
|
||||||
assert_eq!(Chip8CpuInstructions::SLF.encode(), 0x00FC);
|
assert_eq!(Chip8CpuInstructions::SCL.encode(), 0x00FC);
|
||||||
assert_eq!(Chip8CpuInstructions::SRT.encode(), 0x00FB);
|
assert_eq!(Chip8CpuInstructions::SCR.encode(), 0x00FB);
|
||||||
assert_eq!(Chip8CpuInstructions::EXIT.encode(), 0x00FD);
|
assert_eq!(Chip8CpuInstructions::EXIT.encode(), 0x00FD);
|
||||||
assert_eq!(Chip8CpuInstructions::ENA.encode(), 0x00FF);
|
assert_eq!(Chip8CpuInstructions::HIGH.encode(), 0x00FF);
|
||||||
assert_eq!(Chip8CpuInstructions::DIS.encode(), 0x00FE);
|
assert_eq!(Chip8CpuInstructions::LOW.encode(), 0x00FE);
|
||||||
assert_eq!(Chip8CpuInstructions::LDF2(0).encode(), 0xF030);
|
assert_eq!(Chip8CpuInstructions::LDF2(0).encode(), 0xF030);
|
||||||
assert_eq!(Chip8CpuInstructions::STR(1).encode(), 0xF175);
|
assert_eq!(Chip8CpuInstructions::STR(1).encode(), 0xF175);
|
||||||
assert_eq!(Chip8CpuInstructions::LIDR(1).encode(), 0xF185);
|
assert_eq!(Chip8CpuInstructions::LIDR(1).encode(), 0xF185);
|
||||||
@ -1343,11 +1343,11 @@ fn instructions_operands_tests() {
|
|||||||
fn instruction_ena_dis_tests() {
|
fn instruction_ena_dis_tests() {
|
||||||
let mut x = Chip8Computer::new();
|
let mut x = Chip8Computer::new();
|
||||||
assert!(!x.video_memory.is_highres());
|
assert!(!x.video_memory.is_highres());
|
||||||
Chip8CpuInstructions::ENA.execute(&mut x);
|
Chip8CpuInstructions::HIGH.execute(&mut x);
|
||||||
assert!(x.video_memory.is_highres());
|
assert!(x.video_memory.is_highres());
|
||||||
Chip8CpuInstructions::ENA.execute(&mut x);
|
Chip8CpuInstructions::HIGH.execute(&mut x);
|
||||||
assert!(x.video_memory.is_highres());
|
assert!(x.video_memory.is_highres());
|
||||||
Chip8CpuInstructions::DIS.execute(&mut x);
|
Chip8CpuInstructions::LOW.execute(&mut x);
|
||||||
assert!(!x.video_memory.is_highres());
|
assert!(!x.video_memory.is_highres());
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1355,24 +1355,24 @@ fn instruction_ena_dis_tests() {
|
|||||||
fn instruction_test_scrolling_lowres() {
|
fn instruction_test_scrolling_lowres() {
|
||||||
let mut x = Chip8Computer::new();
|
let mut x = Chip8Computer::new();
|
||||||
x.video_memory = build_checkerboard();
|
x.video_memory = build_checkerboard();
|
||||||
Chip8CpuInstructions::SRT.execute(&mut x);
|
Chip8CpuInstructions::SCR.execute(&mut x);
|
||||||
|
|
||||||
assert_eq!(read_test_result("test_scroll_right_4.asc"), x.dump_video_to_string());
|
assert_eq!(read_test_result("test_scroll_right_4.asc"), x.dump_video_to_string());
|
||||||
|
|
||||||
x = Chip8Computer::new();
|
x = Chip8Computer::new();
|
||||||
x.video_memory = build_checkerboard();
|
x.video_memory = build_checkerboard();
|
||||||
Chip8CpuInstructions::SLF.execute(&mut x);
|
Chip8CpuInstructions::SCL.execute(&mut x);
|
||||||
|
|
||||||
assert_eq!(read_test_result("test_scroll_left_4.asc"), x.dump_video_to_string());
|
assert_eq!(read_test_result("test_scroll_left_4.asc"), x.dump_video_to_string());
|
||||||
|
|
||||||
x = Chip8Computer::new();
|
x = Chip8Computer::new();
|
||||||
x.video_memory = build_checkerboard();
|
x.video_memory = build_checkerboard();
|
||||||
Chip8CpuInstructions::SDN(0x01).execute(&mut x);
|
Chip8CpuInstructions::SCD(0x01).execute(&mut x);
|
||||||
assert_eq!(read_test_result("test_video_scroll_down_1.asc"), x.dump_video_to_string());
|
assert_eq!(read_test_result("test_video_scroll_down_1.asc"), x.dump_video_to_string());
|
||||||
|
|
||||||
x = Chip8Computer::new();
|
x = Chip8Computer::new();
|
||||||
x.video_memory = build_checkerboard();
|
x.video_memory = build_checkerboard();
|
||||||
Chip8CpuInstructions::SDN(0xA).execute(&mut x);
|
Chip8CpuInstructions::SCD(0xA).execute(&mut x);
|
||||||
assert_eq!(read_test_result("test_video_scroll_down_10.asc"), x.dump_video_to_string());
|
assert_eq!(read_test_result("test_video_scroll_down_10.asc"), x.dump_video_to_string());
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
@ -3,12 +3,14 @@ use gemma::chip8::instructions::Chip8CpuInstructions::*;
|
|||||||
use gemma::chip8::quirk_modes::QuirkMode::{Chip8, SChipModern, XOChip};
|
use gemma::chip8::quirk_modes::QuirkMode::{Chip8, SChipModern, XOChip};
|
||||||
use gemma::constants::*;
|
use gemma::constants::*;
|
||||||
|
|
||||||
|
#[derive(Clone)]
|
||||||
struct InstructionTestQuirks {
|
struct InstructionTestQuirks {
|
||||||
chip8: Chip8CpuInstructions,
|
chip8: Chip8CpuInstructions,
|
||||||
schip: Chip8CpuInstructions,
|
schip: Chip8CpuInstructions,
|
||||||
xochip: Chip8CpuInstructions
|
xochip: Chip8CpuInstructions
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#[derive(Clone)]
|
||||||
struct InstructionTest {
|
struct InstructionTest {
|
||||||
name: String,
|
name: String,
|
||||||
instruction: Chip8CpuInstructions,
|
instruction: Chip8CpuInstructions,
|
||||||
@ -23,7 +25,7 @@ fn instructions_encode_decode_tests_with_quirks() {
|
|||||||
let it = vec![
|
let it = vec![
|
||||||
InstructionTest {
|
InstructionTest {
|
||||||
name: INST_SYS.to_string(),
|
name: INST_SYS.to_string(),
|
||||||
instruction: Chip8CpuInstructions::SYS(0x123),
|
instruction: SYS(0x123),
|
||||||
operands: "0x0123".to_string(),
|
operands: "0x0123".to_string(),
|
||||||
asm: "SYS 0x0123".to_string(),
|
asm: "SYS 0x0123".to_string(),
|
||||||
encoded: 0x0123,
|
encoded: 0x0123,
|
||||||
@ -35,7 +37,7 @@ fn instructions_encode_decode_tests_with_quirks() {
|
|||||||
},
|
},
|
||||||
InstructionTest {
|
InstructionTest {
|
||||||
name: INST_CLS.to_string(),
|
name: INST_CLS.to_string(),
|
||||||
instruction: Chip8CpuInstructions::CLS,
|
instruction: CLS,
|
||||||
asm: "CLS".to_string(),
|
asm: "CLS".to_string(),
|
||||||
operands: "".to_string(),
|
operands: "".to_string(),
|
||||||
encoded: 0x00E0,
|
encoded: 0x00E0,
|
||||||
@ -47,7 +49,7 @@ fn instructions_encode_decode_tests_with_quirks() {
|
|||||||
},
|
},
|
||||||
InstructionTest {
|
InstructionTest {
|
||||||
name: INST_RET.to_string(),
|
name: INST_RET.to_string(),
|
||||||
instruction: Chip8CpuInstructions::RET,
|
instruction: RET,
|
||||||
asm: "RET".to_string(),
|
asm: "RET".to_string(),
|
||||||
operands: "".to_string(),
|
operands: "".to_string(),
|
||||||
encoded: 0x00ee,
|
encoded: 0x00ee,
|
||||||
@ -57,333 +59,204 @@ fn instructions_encode_decode_tests_with_quirks() {
|
|||||||
xochip: RET
|
xochip: RET
|
||||||
}
|
}
|
||||||
},
|
},
|
||||||
InstructionTest {
|
|
||||||
name: INST_JPA.to_string(),
|
|
||||||
instruction: JPA(0x234),
|
|
||||||
asm: "JPA 0x0234".to_string(),
|
|
||||||
encoded: 0xb234,
|
|
||||||
operands: "0x0234".to_string(),
|
|
||||||
quirks: InstructionTestQuirks {
|
|
||||||
chip8: JPA(0x0234),
|
|
||||||
schip: JPA(0x0234),
|
|
||||||
xochip: JPA(0x0234)
|
|
||||||
}
|
|
||||||
},
|
|
||||||
InstructionTest {
|
InstructionTest {
|
||||||
name: INST_JPX.to_string(),
|
name: INST_JPX.to_string(),
|
||||||
instruction: Chip8CpuInstructions::JPX(0x1, 0xab),
|
instruction: JPX(0x1, 0xab),
|
||||||
operands: "0x01, 0x01ab".to_string(),
|
operands: "0x01, 0x01ab".to_string(),
|
||||||
asm: "JPX 0x01, 0x01ab".to_string(),
|
asm: "JPX 0x01, 0x01ab".to_string(),
|
||||||
encoded: 0,
|
encoded: 0xb1ab,
|
||||||
quirks: InstructionTestQuirks {
|
quirks: InstructionTestQuirks {
|
||||||
chip8: XXXXERRORINSTRUCTION,
|
chip8: XXXXERRORINSTRUCTION,
|
||||||
schip: JPX(0x1, 0xab),
|
schip: JPX(0x1, 0xab),
|
||||||
xochip: XXXXERRORINSTRUCTION,
|
xochip: XXXXERRORINSTRUCTION,
|
||||||
},
|
},
|
||||||
}
|
},
|
||||||
/*
|
|
||||||
|
|
||||||
|
|
||||||
,
|
|
||||||
InstructionTest {
|
InstructionTest {
|
||||||
name: INST_CALL.to_string(),
|
name: INST_CALL.to_string(),
|
||||||
instruction: Chip8CpuInstructions::CALL(0x123),
|
instruction: CALL(0x123),
|
||||||
asm: "CALL 0x0123".to_string(),
|
asm: "CALL 0x0123".to_string(),
|
||||||
encoded: 0x2123,
|
encoded: 0x2123,
|
||||||
operands: "0x0123".to_string()
|
operands: "0x0123".to_string(),
|
||||||
|
quirks: InstructionTestQuirks {
|
||||||
|
chip8: CALL(0x123),
|
||||||
|
schip: CALL(0x123),
|
||||||
|
xochip: CALL(0x123),
|
||||||
|
}
|
||||||
},
|
},
|
||||||
InstructionTest {
|
InstructionTest {
|
||||||
name: INST_DRW.to_string(),
|
name: INST_DRW.to_string(),
|
||||||
instruction: Chip8CpuInstructions::DRW(0x01, 0x02, 0x03),
|
instruction: DRW(0x01, 0x02, 0x03),
|
||||||
operands: "0x01, 0x02, 0x03".to_string(),
|
operands: "0x01, 0x02, 0x03".to_string(),
|
||||||
asm: "DRW 0x01, 0x02, 0x03".to_string(),
|
asm: "DRW 0x01, 0x02, 0x03".to_string(),
|
||||||
encoded: 0xd123
|
encoded: 0xd123,
|
||||||
|
quirks: InstructionTestQuirks {
|
||||||
|
chip8: DRW(0x1, 0x2, 0x3),
|
||||||
|
schip: DRW(0x1, 0x2, 0x3),
|
||||||
|
xochip: DRW(0x1, 0x2, 0x3)
|
||||||
|
}
|
||||||
},
|
},
|
||||||
InstructionTest {
|
InstructionTest {
|
||||||
name: INST_JPI.to_string(),
|
name: INST_JPI.to_string(),
|
||||||
instruction: Chip8CpuInstructions::JPI(0x321),
|
instruction: JPI(0x321),
|
||||||
operands: "0x0321".to_string(),
|
operands: "0x0321".to_string(),
|
||||||
asm: "JPI 0x0321".to_string(),
|
asm: "JPI 0x0321".to_string(),
|
||||||
encoded: 0xb321
|
encoded: 0xb321,
|
||||||
|
quirks: InstructionTestQuirks {
|
||||||
|
chip8: JPI(0x321),
|
||||||
|
schip: XXXXERRORINSTRUCTION,
|
||||||
|
xochip: JPI(0x321)
|
||||||
|
}
|
||||||
},
|
},
|
||||||
InstructionTest {
|
InstructionTest {
|
||||||
name: INST_SDN.to_string(),
|
name: INST_SCD.to_string(),
|
||||||
instruction: Chip8CpuInstructions::SDN(0x01),
|
instruction: SCD(0x01),
|
||||||
operands: "0x01".to_string(),
|
operands: "0x01".to_string(),
|
||||||
asm: "SDN 0x01".to_string(),
|
asm: "SCD 0x01".to_string(),
|
||||||
encoded: 0x00c1
|
encoded: 0x00c1,
|
||||||
|
quirks: InstructionTestQuirks {
|
||||||
|
chip8: XXXXERRORINSTRUCTION,
|
||||||
|
schip: SCD(0x1),
|
||||||
|
xochip: SCD(0x1)
|
||||||
|
}
|
||||||
},
|
},
|
||||||
InstructionTest {
|
InstructionTest {
|
||||||
name: INST_SRT.to_string(),
|
name: INST_SCR.to_string(),
|
||||||
instruction: Chip8CpuInstructions::SRT,
|
instruction: Chip8CpuInstructions::SCR,
|
||||||
operands: "".to_string(),
|
operands: "".to_string(),
|
||||||
asm: "SRT".to_string(),
|
asm: "SCR".to_string(),
|
||||||
encoded: 0x00FB
|
encoded: 0x00FB,
|
||||||
|
quirks: InstructionTestQuirks {
|
||||||
|
chip8: XXXXERRORINSTRUCTION,
|
||||||
|
schip: SCR,
|
||||||
|
xochip: SCR
|
||||||
|
}
|
||||||
},
|
},
|
||||||
InstructionTest {
|
InstructionTest {
|
||||||
name: INST_SLF.to_string(),
|
name: INST_SCL.to_string(),
|
||||||
instruction: Chip8CpuInstructions::SLF,
|
instruction: SCL,
|
||||||
operands: "".to_string(),
|
operands: "".to_string(),
|
||||||
asm: "SLF".to_string(),
|
asm: "SCL".to_string(),
|
||||||
encoded: 0x00FC,
|
encoded: 0x00FC,
|
||||||
|
quirks: InstructionTestQuirks {
|
||||||
|
chip8: XXXXERRORINSTRUCTION,
|
||||||
|
schip: SCL,
|
||||||
|
xochip: SCL
|
||||||
|
}
|
||||||
},
|
},
|
||||||
InstructionTest {
|
InstructionTest {
|
||||||
name: INST_EXIT.to_string(),
|
name: INST_EXIT.to_string(),
|
||||||
instruction: Chip8CpuInstructions::EXIT,
|
instruction: EXIT,
|
||||||
operands: "".to_string(),
|
operands: "".to_string(),
|
||||||
asm: "EXIT".to_string(),
|
asm: "EXIT".to_string(),
|
||||||
encoded: 0x00FD,
|
encoded: 0x00FD,
|
||||||
|
quirks: InstructionTestQuirks {
|
||||||
|
chip8: XXXXERRORINSTRUCTION,
|
||||||
|
schip: EXIT,
|
||||||
|
xochip: EXIT
|
||||||
|
}
|
||||||
},
|
},
|
||||||
InstructionTest {
|
InstructionTest {
|
||||||
name: INST_DIS.to_string(),
|
name: INST_LOW.to_string(),
|
||||||
instruction: Chip8CpuInstructions::DIS,
|
instruction: LOW,
|
||||||
operands: "".to_string(),
|
operands: "".to_string(),
|
||||||
asm: "DIS".to_string(),
|
asm: "LOW".to_string(),
|
||||||
encoded: 0x00FE,
|
encoded: 0x00FE,
|
||||||
|
quirks: InstructionTestQuirks {
|
||||||
|
chip8: XXXXERRORINSTRUCTION,
|
||||||
|
schip: LOW,
|
||||||
|
xochip: LOW,
|
||||||
|
}
|
||||||
},
|
},
|
||||||
InstructionTest {
|
InstructionTest {
|
||||||
name: INST_ENA.to_string(),
|
name: INST_HIGH.to_string(),
|
||||||
instruction: Chip8CpuInstructions::ENA,
|
instruction: HIGH,
|
||||||
operands: "".to_string(),
|
operands: "".to_string(),
|
||||||
asm: "ENA".to_string(),
|
asm: "HIGH".to_string(),
|
||||||
encoded: 0x00FF,
|
encoded: 0x00FF,
|
||||||
|
quirks: InstructionTestQuirks {
|
||||||
|
chip8: XXXXERRORINSTRUCTION,
|
||||||
|
schip: HIGH,
|
||||||
|
xochip: HIGH
|
||||||
|
}
|
||||||
},
|
},
|
||||||
InstructionTest {
|
InstructionTest {
|
||||||
name: INST_SEX.to_string(),
|
name: INST_SEX.to_string(),
|
||||||
instruction: Chip8CpuInstructions::SEX(0x01, 0xfa),
|
instruction: Chip8CpuInstructions::SEX(0x01, 0xfa),
|
||||||
operands: "0x01, 0xfa".to_string(),
|
operands: "0x01, 0xfa".to_string(),
|
||||||
asm: "SEX 0x01, 0xfa".to_string(),
|
asm: "SEX 0x01, 0xfa".to_string(),
|
||||||
encoded: 0x32fa,
|
encoded: 0x31fa,
|
||||||
|
quirks: InstructionTestQuirks {
|
||||||
|
chip8: Chip8CpuInstructions::SEX(0x1, 0xfa),
|
||||||
|
schip: Chip8CpuInstructions::SEX(0x1, 0xfa),
|
||||||
|
xochip: Chip8CpuInstructions::SEX(0x1, 0xfa)
|
||||||
},
|
},
|
||||||
|
},
|
||||||
|
|
||||||
InstructionTest {
|
InstructionTest {
|
||||||
name: INST_SNEB.to_string(),
|
name: INST_SNEB.to_string(),
|
||||||
instruction: Chip8CpuInstructions::SNEB(0x01, 0xab),
|
instruction: Chip8CpuInstructions::SNEB(0x01, 0xab),
|
||||||
operands: "0x01, 0xab".to_string(),
|
operands: "0x01, 0xab".to_string(),
|
||||||
asm: "SNEB 0x01, 0xab".to_string(),
|
asm: "SNEB 0x01, 0xab".to_string(),
|
||||||
encoded: 0x41ab,
|
encoded: 0x41ab,
|
||||||
|
quirks: InstructionTestQuirks {
|
||||||
|
chip8: SNEB(0x01, 0xab),
|
||||||
|
schip: SNEB(0x01, 0xab),
|
||||||
|
xochip: SNEB(0x01, 0xab),
|
||||||
|
},
|
||||||
},
|
},
|
||||||
InstructionTest {
|
InstructionTest {
|
||||||
name: INST_SEY.to_string(),
|
name: INST_SEY.to_string(),
|
||||||
instruction: Chip8CpuInstructions::SEY(0x1, 0x2),
|
instruction: Chip8CpuInstructions::SEY(0x1, 0x2),
|
||||||
operands: "0x1, 0x2".to_string(),
|
operands: "0x1, 0x2".to_string(),
|
||||||
asm: "SEY 0x1, 0x2".to_string(),
|
asm: "SEY 0x1, 0x2".to_string(),
|
||||||
encoded: 0x5120
|
encoded: 0x5120,
|
||||||
|
quirks: InstructionTestQuirks {
|
||||||
|
chip8: SEY(0x1, 0x2),
|
||||||
|
schip: SEY(0x1, 0x2),
|
||||||
|
xochip: SEY(0x1, 0x2)
|
||||||
|
}
|
||||||
},
|
},
|
||||||
InstructionTest {
|
InstructionTest {
|
||||||
name: INST_LDR.to_string(),
|
name: INST_LDR.to_string(),
|
||||||
instruction: Chip8CpuInstructions::LDR(0xa, 0xbe),
|
instruction: LDR(0xa, 0xbe),
|
||||||
operands: "0x0a, 0xbe".to_string(),
|
operands: "0x0a, 0xbe".to_string(),
|
||||||
asm: "LDR 0x0a, 0xbe".to_string(),
|
asm: "LDR 0x0a, 0xbe".to_string(),
|
||||||
encoded: 0x6abe,
|
encoded: 0x6abe,
|
||||||
|
quirks: InstructionTestQuirks {
|
||||||
|
chip8: LDR(0xa, 0xbe),
|
||||||
|
schip: LDR(0xa, 0xbe),
|
||||||
|
xochip: LDR(0xa, 0xbe)
|
||||||
|
},
|
||||||
},
|
},
|
||||||
InstructionTest {
|
InstructionTest {
|
||||||
name: INST_ADD.to_string(),
|
name: INST_ADD.to_string(),
|
||||||
instruction: Chip8CpuInstructions::ADD(0x01, 0xab),
|
instruction: Chip8CpuInstructions::ADD(0x01, 0xab),
|
||||||
operands: "0x01, 0xab".to_string(),
|
operands: "0x01, 0xab".to_string(),
|
||||||
asm: "ADD 0x01, 0xab".to_string(),
|
asm: "ADD 0x01, 0xab".to_string(),
|
||||||
encoded: 0x71ab
|
encoded: 0x71ab,
|
||||||
|
quirks: InstructionTestQuirks {
|
||||||
|
chip8: ADD(0x01, 0xab),
|
||||||
|
schip: ADD(0x01, 0xab),
|
||||||
|
xochip: ADD(0x01, 0xab),
|
||||||
},
|
},
|
||||||
InstructionTest {
|
|
||||||
name: INST_LDRY.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::LDR_Y(0x1, 0x2),
|
|
||||||
operands: "0x1, 0x2".to_string(),
|
|
||||||
asm: "LDRY 0x1, 0x2".to_string(),
|
|
||||||
encoded: 0x8120,
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_OR.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::OR(0x1, 0x2),
|
|
||||||
operands: "0x1, 0x2".to_string(),
|
|
||||||
asm: "OR 0x1, 0x2".to_string(),
|
|
||||||
encoded: 0x8121
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_AND.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::AND(0xb, 0xc),
|
|
||||||
operands: "0xb, 0xc".to_string(),
|
|
||||||
asm: "AND 0xb, 0xc".to_string(),
|
|
||||||
encoded: 0x8bc2,
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_ORY.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::ORY(0xa, 0x3),
|
|
||||||
operands: "0xa, 0x3".to_string(),
|
|
||||||
asm: "ORY 0xa, 0x3".to_string(),
|
|
||||||
encoded: 0x8a33
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_ADDR.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::ADDR(0x1, 0x2),
|
|
||||||
operands: "0x1, 0x2".to_string(),
|
|
||||||
asm: "ADDR 0x1, 0x2".to_string(),
|
|
||||||
encoded: 0x8124
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_SUB.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::SUB(0x4, 0x5),
|
|
||||||
operands: "0x4, 0x5".to_string(),
|
|
||||||
asm: "SUB 0x4, 0x5".to_string(),
|
|
||||||
encoded: 0x8455
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_SHR.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::SHR(0x01, 0x1),
|
|
||||||
operands: "0x1, 0x1".to_string(),
|
|
||||||
asm: "SHR 0x1, 0x1".to_string(),
|
|
||||||
encoded: 0x8116,
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_SUBC.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::SUBC(0xf, 0xa),
|
|
||||||
operands: "0xf, 0xa".to_string(),
|
|
||||||
asm: "SUBC 0xf, 0xa".to_string(),
|
|
||||||
encoded: 0x8fa7,
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_SHL.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::SHL(0x1, 0x4),
|
|
||||||
operands: "0x1, 0x4".to_string(),
|
|
||||||
asm: "SHL 0x1, 0x4".to_string(),
|
|
||||||
encoded: 0x814e,
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_SNEY.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::SNEY(0x4, 0x5),
|
|
||||||
operands: "0x4, 0x5".to_string(),
|
|
||||||
asm: "SNEY 0x4, 0x5".to_string(),
|
|
||||||
encoded: 0x9450,
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_LDIA.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::LDIA(0xbee),
|
|
||||||
operands: "0x0bee".to_string(),
|
|
||||||
asm: "LDIA 0x0bee".to_string(),
|
|
||||||
encoded: 0x9bee
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_JPI.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::JPI(0xfee),
|
|
||||||
operands: "0x0fee".to_string(),
|
|
||||||
asm: "JPI 0x0fee".to_string(),
|
|
||||||
encoded: 0xbfee
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_RND.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::RND(0x1, 0xae),
|
|
||||||
operands: "0x01, 0xae".to_string(),
|
|
||||||
asm: "RND 0x01, 0xae".to_string(),
|
|
||||||
encoded: 0xc1ae,
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_DRW.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::DRW(0x1, 0x2, 0xf),
|
|
||||||
operands: "0x01, 0x02, 0x0f".to_string(),
|
|
||||||
asm: "DRW 0x01, 0x02, 0x0f".to_string(),
|
|
||||||
encoded: 0xd12f
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_SKP.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::SKP(0x4),
|
|
||||||
operands: "0x04".to_string(),
|
|
||||||
asm: "SKP 0x04".to_string(),
|
|
||||||
encoded: 0xe49e,
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_SKNP.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::SKNP(0x3),
|
|
||||||
operands: "0x03".to_string(),
|
|
||||||
asm: "SKNP 0x03".to_string(),
|
|
||||||
encoded: 0x83a1
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_LDRD.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::LDRD(0x4),
|
|
||||||
operands: "0x04".to_string(),
|
|
||||||
asm: "LDRD 0x04".to_string(),
|
|
||||||
encoded: 0xF407
|
|
||||||
},
|
},
|
||||||
InstructionTest {
|
InstructionTest {
|
||||||
name: INST_LDRK.to_string(),
|
name: INST_LDRK.to_string(),
|
||||||
instruction: Chip8CpuInstructions::LDRK(0x6),
|
instruction: Chip8CpuInstructions::LDRK(0x6),
|
||||||
operands: "0x06".to_string(),
|
operands: "0x06".to_string(),
|
||||||
asm: "LDRK 0x06".to_string(),
|
asm: "LDRK 0x06".to_string(),
|
||||||
encoded: 0xF60A
|
encoded: 0xF60A,
|
||||||
|
quirks: InstructionTestQuirks {
|
||||||
|
chip8: Chip8CpuInstructions::LDRK(0x6),
|
||||||
|
schip: Chip8CpuInstructions::LDRK(0x6),
|
||||||
|
xochip: Chip8CpuInstructions::LDRK(0x6),
|
||||||
},
|
},
|
||||||
InstructionTest {
|
|
||||||
name: INST_LDD.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::LDD(0x02),
|
|
||||||
operands: "0x02".to_string(),
|
|
||||||
asm: "LDD 0x02".to_string(),
|
|
||||||
encoded: 0xF215,
|
|
||||||
},
|
},
|
||||||
InstructionTest {
|
|
||||||
name: INST_LDRI.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::LDRI(0x01),
|
|
||||||
operands: "0x01".to_string(),
|
|
||||||
asm: "LDRI 0x01".to_string(),
|
|
||||||
encoded: 0xF118,
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_BCD.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::BCD(0x4),
|
|
||||||
operands: "0x04".to_string(),
|
|
||||||
asm: "BCD 0x04".to_string(),
|
|
||||||
encoded: 0xF433,
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_LDF.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::LDFX(0x5),
|
|
||||||
operands: "0x05".to_string(),
|
|
||||||
asm: "LDF 0x05".to_string(),
|
|
||||||
encoded: 0xF529
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_LDF2.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::LDF2(0x6),
|
|
||||||
operands: "0x06".to_string(),
|
|
||||||
asm: "LDF2 0x06".to_string(),
|
|
||||||
encoded: 0xF630
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_LDIX.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::LDIX(0x5),
|
|
||||||
operands: "0x05".to_string(),
|
|
||||||
asm: "LDIX 0x05".to_string(),
|
|
||||||
encoded: 0xF555
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_LDIS.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::LDIS(0xf),
|
|
||||||
operands: "0x0f".to_string(),
|
|
||||||
asm: "LDIS 0x0f".to_string(),
|
|
||||||
encoded: 0xFF18
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_LIDR.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::LIDR(0x4),
|
|
||||||
operands: "0x04".to_string(),
|
|
||||||
asm: "LIDR 0x04".to_string(),
|
|
||||||
encoded: 0xF485,
|
|
||||||
},
|
|
||||||
InstructionTest {
|
|
||||||
name: INST_STR.to_string(),
|
|
||||||
instruction: Chip8CpuInstructions::STR(0xa),
|
|
||||||
operands: "0x0a".to_string(),
|
|
||||||
asm: "STR 0x0a".to_string(),
|
|
||||||
encoded: 0xF000
|
|
||||||
}
|
|
||||||
*/
|
|
||||||
];
|
];
|
||||||
|
|
||||||
for current in it {
|
for current in it {
|
||||||
assert_eq!(current.instruction.name(), current.name);
|
let instruction = current.clone().instruction;
|
||||||
let i = current.instruction;
|
|
||||||
assert!(matches!(Chip8CpuInstructions::decode(current.encoded, &Chip8), i));
|
|
||||||
assert_eq!(i.to_string(), current.asm);
|
|
||||||
let asm = Chip8CpuInstructions::from_str(¤t.asm);
|
let asm = Chip8CpuInstructions::from_str(¤t.asm);
|
||||||
assert_eq!(i.to_string(), asm.to_string());
|
|
||||||
assert_eq!(i.operands(), current.operands);
|
|
||||||
// test quirks
|
|
||||||
let as_chip8 = Chip8CpuInstructions::decode(current.encoded, &Chip8);
|
let as_chip8 = Chip8CpuInstructions::decode(current.encoded, &Chip8);
|
||||||
let quirks_chip8 = current.quirks.chip8;
|
let quirks_chip8 = current.quirks.chip8;
|
||||||
let as_schip = Chip8CpuInstructions::decode(current.encoded, &SChipModern);
|
let as_schip = Chip8CpuInstructions::decode(current.encoded, &SChipModern);
|
||||||
@ -391,9 +264,224 @@ fn instructions_encode_decode_tests_with_quirks() {
|
|||||||
let as_xochip = Chip8CpuInstructions::decode(current.encoded, &XOChip);
|
let as_xochip = Chip8CpuInstructions::decode(current.encoded, &XOChip);
|
||||||
let quirks_xochip = current.quirks.xochip;
|
let quirks_xochip = current.quirks.xochip;
|
||||||
|
|
||||||
|
// ** CONVERSION **
|
||||||
|
// -> Integer to Instruction
|
||||||
|
assert!(matches!(Chip8CpuInstructions::decode(current.encoded, &Chip8), i));
|
||||||
|
// -> Instruction to Integer
|
||||||
|
println!("TESTING INSTRUCTION TO INTEGER FOR {:?} / {:04x} {:04x}", current.instruction, current.encoded, instruction.encode());
|
||||||
|
assert_eq!(current.encoded, instruction.encode());
|
||||||
|
// -> Instruction to String
|
||||||
|
assert_eq!(instruction.to_string(), current.asm);
|
||||||
|
assert_eq!(instruction.operands(), current.operands);
|
||||||
|
assert_eq!(current.instruction.name(), current.name);
|
||||||
|
// -> String to Instruction
|
||||||
|
assert!(matches!(Chip8CpuInstructions::from_str(¤t.name), asm));
|
||||||
|
// ** QUIRKS **
|
||||||
assert!(matches!(as_chip8, quirks_chip8));
|
assert!(matches!(as_chip8, quirks_chip8));
|
||||||
assert!(matches!(as_schip, quirks_schip));
|
assert!(matches!(as_schip, quirks_schip));
|
||||||
assert!(matches!(as_xochip, quirks_xochip));
|
assert!(matches!(as_xochip, quirks_xochip));
|
||||||
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_LDRY.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::LDR_Y(0x1, 0x2),
|
||||||
|
operands: "0x1, 0x2".to_string(),
|
||||||
|
asm: "LDRY 0x1, 0x2".to_string(),
|
||||||
|
encoded: 0x8120,
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_OR.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::OR(0x1, 0x2),
|
||||||
|
operands: "0x1, 0x2".to_string(),
|
||||||
|
asm: "OR 0x1, 0x2".to_string(),
|
||||||
|
encoded: 0x8121
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_AND.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::AND(0xb, 0xc),
|
||||||
|
operands: "0xb, 0xc".to_string(),
|
||||||
|
asm: "AND 0xb, 0xc".to_string(),
|
||||||
|
encoded: 0x8bc2,
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_ORY.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::ORY(0xa, 0x3),
|
||||||
|
operands: "0xa, 0x3".to_string(),
|
||||||
|
asm: "ORY 0xa, 0x3".to_string(),
|
||||||
|
encoded: 0x8a33
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_ADDR.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::ADDR(0x1, 0x2),
|
||||||
|
operands: "0x1, 0x2".to_string(),
|
||||||
|
asm: "ADDR 0x1, 0x2".to_string(),
|
||||||
|
encoded: 0x8124
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_SUB.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::SUB(0x4, 0x5),
|
||||||
|
operands: "0x4, 0x5".to_string(),
|
||||||
|
asm: "SUB 0x4, 0x5".to_string(),
|
||||||
|
encoded: 0x8455
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_SHR.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::SHR(0x01, 0x1),
|
||||||
|
operands: "0x1, 0x1".to_string(),
|
||||||
|
asm: "SHR 0x1, 0x1".to_string(),
|
||||||
|
encoded: 0x8116,
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_SUBC.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::SUBC(0xf, 0xa),
|
||||||
|
operands: "0xf, 0xa".to_string(),
|
||||||
|
asm: "SUBC 0xf, 0xa".to_string(),
|
||||||
|
encoded: 0x8fa7,
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_SHL.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::SHL(0x1, 0x4),
|
||||||
|
operands: "0x1, 0x4".to_string(),
|
||||||
|
asm: "SHL 0x1, 0x4".to_string(),
|
||||||
|
encoded: 0x814e,
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_SNEY.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::SNEY(0x4, 0x5),
|
||||||
|
operands: "0x4, 0x5".to_string(),
|
||||||
|
asm: "SNEY 0x4, 0x5".to_string(),
|
||||||
|
encoded: 0x9450,
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_LDIA.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::LDIA(0xbee),
|
||||||
|
operands: "0x0bee".to_string(),
|
||||||
|
asm: "LDIA 0x0bee".to_string(),
|
||||||
|
encoded: 0x9bee
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_JPI.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::JPI(0xfee),
|
||||||
|
operands: "0x0fee".to_string(),
|
||||||
|
asm: "JPI 0x0fee".to_string(),
|
||||||
|
encoded: 0xbfee
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_RND.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::RND(0x1, 0xae),
|
||||||
|
operands: "0x01, 0xae".to_string(),
|
||||||
|
asm: "RND 0x01, 0xae".to_string(),
|
||||||
|
encoded: 0xc1ae,
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_DRW.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::DRW(0x1, 0x2, 0xf),
|
||||||
|
operands: "0x01, 0x02, 0x0f".to_string(),
|
||||||
|
asm: "DRW 0x01, 0x02, 0x0f".to_string(),
|
||||||
|
encoded: 0xd12f
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_SKP.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::SKP(0x4),
|
||||||
|
operands: "0x04".to_string(),
|
||||||
|
asm: "SKP 0x04".to_string(),
|
||||||
|
encoded: 0xe49e,
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_SKNP.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::SKNP(0x3),
|
||||||
|
operands: "0x03".to_string(),
|
||||||
|
asm: "SKNP 0x03".to_string(),
|
||||||
|
encoded: 0x83a1
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_LDRD.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::LDRD(0x4),
|
||||||
|
operands: "0x04".to_string(),
|
||||||
|
asm: "LDRD 0x04".to_string(),
|
||||||
|
encoded: 0xF407
|
||||||
|
}
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_LDD.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::LDD(0x02),
|
||||||
|
operands: "0x02".to_string(),
|
||||||
|
asm: "LDD 0x02".to_string(),
|
||||||
|
encoded: 0xF215,
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_LDRI.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::LDRI(0x01),
|
||||||
|
operands: "0x01".to_string(),
|
||||||
|
asm: "LDRI 0x01".to_string(),
|
||||||
|
encoded: 0xF118,
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_BCD.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::BCD(0x4),
|
||||||
|
operands: "0x04".to_string(),
|
||||||
|
asm: "BCD 0x04".to_string(),
|
||||||
|
encoded: 0xF433,
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_LDF.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::LDFX(0x5),
|
||||||
|
operands: "0x05".to_string(),
|
||||||
|
asm: "LDF 0x05".to_string(),
|
||||||
|
encoded: 0xF529
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_LDF2.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::LDF2(0x6),
|
||||||
|
operands: "0x06".to_string(),
|
||||||
|
asm: "LDF2 0x06".to_string(),
|
||||||
|
encoded: 0xF630
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_LDIX.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::LDIX(0x5),
|
||||||
|
operands: "0x05".to_string(),
|
||||||
|
asm: "LDIX 0x05".to_string(),
|
||||||
|
encoded: 0xF555
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_LDIS.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::LDIS(0xf),
|
||||||
|
operands: "0x0f".to_string(),
|
||||||
|
asm: "LDIS 0x0f".to_string(),
|
||||||
|
encoded: 0xFF18
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_LIDR.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::LIDR(0x4),
|
||||||
|
operands: "0x04".to_string(),
|
||||||
|
asm: "LIDR 0x04".to_string(),
|
||||||
|
encoded: 0xF485,
|
||||||
|
},
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_STR.to_string(),
|
||||||
|
instruction: Chip8CpuInstructions::STR(0xa),
|
||||||
|
operands: "0x0a".to_string(),
|
||||||
|
asm: "STR 0x0a".to_string(),
|
||||||
|
encoded: 0xF000
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
InstructionTest {
|
||||||
|
name: INST_JPA.to_string(),
|
||||||
|
instruction: JPA(0x234),
|
||||||
|
asm: "JPA 0x0234".to_string(),
|
||||||
|
encoded: 0xb234,
|
||||||
|
operands: "0x0234".to_string(),
|
||||||
|
quirks: InstructionTestQuirks {
|
||||||
|
chip8: JPA(0x0234),
|
||||||
|
schip: JPA(0x0234),
|
||||||
|
xochip: JPA(0x0234)
|
||||||
|
}
|
||||||
|
},
|
||||||
|
*/
|
||||||
@ -11,7 +11,7 @@ use gemma::chip8::system_memory::Chip8SystemMemory;
|
|||||||
use crate::ImGuiUiState;
|
use crate::ImGuiUiState;
|
||||||
use crate::support::gui_file_list::GuiFileList;
|
use crate::support::gui_file_list::GuiFileList;
|
||||||
|
|
||||||
const ROM_ROOT: &str = "/home/tmerritt/Projects/chip8_toy/resources/roms";
|
const ROM_ROOT: &str = "resources/roms";
|
||||||
|
|
||||||
pub struct GemmaImguiSupport {}
|
pub struct GemmaImguiSupport {}
|
||||||
|
|
||||||
@ -21,7 +21,7 @@ const CELL_HEIGHT: i32 = 5i32;
|
|||||||
impl GemmaImguiSupport {
|
impl GemmaImguiSupport {
|
||||||
pub fn keypad_display(system_to_display: &Chip8Computer, ui: &Ui) {
|
pub fn keypad_display(system_to_display: &Chip8Computer, ui: &Ui) {
|
||||||
ui.window("Keypad".to_string())
|
ui.window("Keypad".to_string())
|
||||||
.size([100.0, 100.0], Condition::FirstUseEver)
|
.position([100.0, 640.0], Condition::FirstUseEver)
|
||||||
.build(|| {
|
.build(|| {
|
||||||
for row in CHIP8_KEYBOARD {
|
for row in CHIP8_KEYBOARD {
|
||||||
for key in row {
|
for key in row {
|
||||||
@ -46,11 +46,8 @@ impl GemmaImguiSupport {
|
|||||||
let cell_width = ((draw_area_size[0] as i32 / width) * 6) / 10;
|
let cell_width = ((draw_area_size[0] as i32 / width) * 6) / 10;
|
||||||
let cell_height = ((draw_area_size[1] as i32 / height) * 6) / 10;
|
let cell_height = ((draw_area_size[1] as i32 / height) * 6) / 10;
|
||||||
|
|
||||||
ui.window(format!("Display {cell_width}x{cell_height}"))
|
|
||||||
.size([300.0, 300.0], Condition::Once)
|
|
||||||
.build(|| {
|
|
||||||
let origin = ui.cursor_pos();
|
let origin = ui.cursor_pos();
|
||||||
let fg = ui.get_window_draw_list();
|
let fg = ui.get_foreground_draw_list();
|
||||||
if system_to_control.video_memory.is_highres() {
|
if system_to_control.video_memory.is_highres() {
|
||||||
// ui.text("High Def Video here");
|
// ui.text("High Def Video here");
|
||||||
for current_row in 0..=height {
|
for current_row in 0..=height {
|
||||||
@ -87,12 +84,11 @@ impl GemmaImguiSupport {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
});
|
|
||||||
}
|
}
|
||||||
pub fn system_controls(system_to_control: &mut Chip8ComputerManager, gui_state: &mut ImGuiUiState, ui: &Ui) {
|
pub fn system_controls(system_to_control: &mut Chip8ComputerManager, gui_state: &mut ImGuiUiState, ui: &Ui) {
|
||||||
// let mut state: Chip8Computer = system_to_control;
|
// let mut state: Chip8Computer = system_to_control;
|
||||||
ui.window("!!!! CONTROLS !!!!")
|
ui.window("!!!! CONTROLS !!!!")
|
||||||
.size([345.0, 200.0], Condition::FirstUseEver)
|
.position([100.0, 640.0], Condition::FirstUseEver)
|
||||||
.build(|| {
|
.build(|| {
|
||||||
/* System Step Counter */
|
/* System Step Counter */
|
||||||
ui.text(format!("Step {:04x}", system_to_control.num_cycles()).as_str());
|
ui.text(format!("Step {:04x}", system_to_control.num_cycles()).as_str());
|
||||||
@ -155,7 +151,7 @@ impl GemmaImguiSupport {
|
|||||||
|
|
||||||
pub fn registers_view(system: &Chip8Computer, ui: &Ui) {
|
pub fn registers_view(system: &Chip8Computer, ui: &Ui) {
|
||||||
ui.window("Registers")
|
ui.window("Registers")
|
||||||
.size([400.0, 500.0], Condition::FirstUseEver)
|
.position([100.0, 640.0], Condition::FirstUseEver)
|
||||||
.build(|| {
|
.build(|| {
|
||||||
ui.text("Registers");
|
ui.text("Registers");
|
||||||
for i in 1..0x10 {
|
for i in 1..0x10 {
|
||||||
@ -179,7 +175,7 @@ impl GemmaImguiSupport {
|
|||||||
let rows = position.0;
|
let rows = position.0;
|
||||||
let cols = position.1;
|
let cols = position.1;
|
||||||
ui.window("System Memory")
|
ui.window("System Memory")
|
||||||
.size([400.0, 300.0], Condition::FirstUseEver)
|
.position([100.0, 640.0], Condition::FirstUseEver)
|
||||||
.build(|| {
|
.build(|| {
|
||||||
let mut current_x_hover: i32 = 0;
|
let mut current_x_hover: i32 = 0;
|
||||||
let mut current_y_hover: i32 = 0;
|
let mut current_y_hover: i32 = 0;
|
||||||
|
|||||||
@ -13,6 +13,7 @@ impl GuiFileList {
|
|||||||
|
|
||||||
let mut known_files: Vec<OsString> = vec![];
|
let mut known_files: Vec<OsString> = vec![];
|
||||||
|
|
||||||
|
println!("STARTING AT {:?}", std::env::current_dir());
|
||||||
for entry in read_dir(root.as_path()).unwrap() {
|
for entry in read_dir(root.as_path()).unwrap() {
|
||||||
known_files.push(entry.unwrap().file_name());
|
known_files.push(entry.unwrap().file_name());
|
||||||
}
|
}
|
||||||
|
|||||||
@ -31,6 +31,7 @@ fn main() {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#[cfg(test)]
|
||||||
mod test {
|
mod test {
|
||||||
use pest::Parser;
|
use pest::Parser;
|
||||||
use crate::{Chip8AsmParser, Rule};
|
use crate::{Chip8AsmParser, Rule};
|
||||||
|
|||||||
@ -80,13 +80,3 @@ fn main() {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
mod test {
|
|
||||||
#[test]
|
|
||||||
fn smoke() { assert!(true); }
|
|
||||||
|
|
||||||
#[test]
|
|
||||||
fn assemble_test_file() {
|
|
||||||
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@ -1,3 +0,0 @@
|
|||||||
#[test]
|
|
||||||
fn smoke() { assert!(true) }
|
|
||||||
|
|
||||||
Loading…
x
Reference in New Issue
Block a user