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MOS6520 looking mostly there.

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This commit is contained in:
Trevor Merritt
2025-07-29 13:12:33 -04:00
parent 8f6f9cb64d
commit 7ac8bd86ba
58 changed files with 742 additions and 422 deletions
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core/src/computers/beneater/backplane.rs
+52
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@@ -0,0 +1,52 @@
use crate::computers::beneater::BenEater;
use crate::traits::backplane::Backplane;
impl Backplane for BenEater {
fn data_bus(&self) -> u8 {
self.data_bus
}
fn address_bus(&self) -> u16 {
self.address_bus
}
fn read_mode(&self) -> bool {
self.read_mode
}
fn set_read_mode(&mut self, new_mode: bool) {
self.read_mode = new_mode
}
fn set_data_bus(&mut self, new_value: u8) {
self.data_bus = new_value
}
fn set_address_bus(&mut self, new_value: u16) {
self.address_bus = new_value
}
fn tick(&mut self) {
println!("Tick the system.");
self.tick_ram(self.address_bus, self.data_bus, true, true, true);
self.tick_rom(self.address_bus, true, true);
self.tick_via(self.address_bus, self.data_bus, true, true, self.read_mode, true, true);
}
fn tick_ram(&mut self, address: u16, data: u8, cs: bool, oe: bool, we: bool) -> u8 {
println!("Ticking RAM");
0x00
}
fn tick_rom(&mut self, address: u16, cs: bool, oe: bool) -> u8 {
println!("Ticking ROM");
0x00
}
fn tick_via(&mut self, address: u16, data: u8, cs0: bool, cs1: bool, rw: bool, rs0: bool, rs1: bool) -> (u8, bool, bool) {
println!("Ticking VIA 6522");
let (new_address, new_data) = self.via.tick(self.address_bus, self.data_bus, false, self.read_mode);
(new_data, false, false)
}
}
core/src/computers/beneater/beneater.rs
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core/src/computers/beneater/mod.rs
+12 -1
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@@ -1 +1,12 @@
pub mod beneater;
mod backplane;
use crate::mos6502cpu::Mos6502Cpu;
use crate::periph::mos6522::mos6522::Mos6522;
pub struct BenEater {
cpu: Mos6502Cpu,
via: Mos6522,
data_bus: u8,
address_bus: u16,
read_mode: bool
}
core/src/computers/kim1/mod.rs
-5
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@@ -2,14 +2,9 @@ pub mod new;
pub mod tick;
pub mod reset;
use std::fs;
use std::path::Path;
use crate::constants::constants_system::SIZE_1KB;
use crate::mos6502cpu::Mos6502Cpu;
use crate::periph::at28c256::At28C256;
use crate::periph::hm62256::Hm62256;
use crate::periph::kim1_keypad::Kim1Keypad;
use crate::periph::mos6522::mos6522::Mos6522;
use crate::periph::mos6530::mos6530::Mos6530;
/// Represents a KIM-1
core/src/computers/mod.rs
+1
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@@ -2,3 +2,4 @@ pub mod beneater;
pub mod rom_only;
pub mod kim1;
pub mod ram_rom;
pub mod tim1;
core/src/computers/ram_rom/backplane.rs
+11 -8
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@@ -1,9 +1,9 @@
use log::debug;
use crate::computers::ram_rom::RamRomComputer;
use crate::periph::at28c256::At28C256;
use crate::traits::backplane::Backplane;
use crate::periph::hm62256::Hm62256;
impl Backplane for RamRomComputer {
fn data_bus(&self) -> u8 {
self.data_bus
@@ -45,7 +45,7 @@ impl Backplane for RamRomComputer {
0x4000..=0x7fff => {
// ROM
println!("ADDRESSING ROM");
let (rom_address_bus, rom_data_bus) = self.rom.tick(self.address_bus, self.data_bus, self.read_mode);
let rom_data_bus = self.rom.signal_tick(self.address_bus, self.data_bus, true, true, true);
self.data_bus = rom_data_bus;
}
_ => {
@@ -54,16 +54,19 @@ impl Backplane for RamRomComputer {
}
}
fn tick_ram(&mut self, address: u16, data: u8, cs: bool, oe: bool, we: bool) {
todo!()
fn tick_ram(&mut self, address: u16, data: u8, cs: bool, oe: bool, we: bool) -> u8 {
debug!("Ticking ram with A${address:04x} D${data:02x} CS:{cs} OE:{oe} WE:{we}");
0
}
fn tick_rom(&mut self, address: u16, data: u8, cs: bool, oe: bool, we: bool) -> (u8) {
todo!()
fn tick_rom(&mut self, address: u16, cs: bool, oe: bool) -> u8 {
debug!("Ticking rom with A${address:04x} CS:{cs} OE:{oe}");
0
}
fn tick_via(&mut self, address: u16, data: u8, cs: bool, rw: bool, ce: bool) -> (u8, u8, bool) {
todo!()
fn tick_via(&mut self, address: u16, data: u8, cs0: bool, cs1: bool, rw: bool, rs0: bool, rs1: bool) -> (u8, bool, bool) {
debug!("Ticking Via with A${address:04x} D${data:02x} cs0:{cs0} cs1:{cs1} rw:{rw} rs0:{rs0} rs1:{rs1}");
(0, false, false)
}
}
core/src/computers/ram_rom/tick2.rs
+1 -1
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@@ -44,7 +44,7 @@ impl RamRomComputer {
}
_ => {}
};
let (_, rom_data_bus) = self.rom.tick(address, data, control == 1);
let rom_data_bus = self.rom.signal_tick(self.address_bus ,self.data_bus, true ,true , true);
let (_, ram_data_bus) = self.ram.tick(address, data, control == 1, true);
0
}
core/src/computers/rom_only/backplane.rs
+15 -13
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@@ -17,27 +17,29 @@ impl Backplane for RomOnlyComputer {
}
fn tick(&mut self) {
println!("COMPUTER: Preparing to tick.");
// println!("COMPUTER: Preparing to tick.");
// do are we being addressed?
println!("COMPUTER: BUSSES PRE: 0x{:04x} 0x{:02x} {}", self.address_bus, self.data_bus, self.read_mode);
let (new_addr, new_data) = self.rom.tick(self.address_bus, self.data_bus, self.read_mode);
self.set_address_bus(new_addr);
// println!("COMPUTER: BUSSES PRE: 0x{:04x} 0x{:02x} {}", self.address_bus, self.data_bus, self.read_mode);
let new_data = self.rom.signal_tick(self.address_bus, self.data_bus, true, true, true);
// tick(self.address_bus, self.data_bus, self.read_mode);
self.set_address_bus(self.address_bus);
self.set_data_bus(new_data);
println!("COMPUTER: BUSSES POST: 0x{:04x} 0x{:02x} {}", self.address_bus, self.data_bus, self.read_mode);
println!("COMPUTER: Done ticking.");
// println!("COMPUTER: BUSSES POST: 0x{:04x} 0x{:02x} {}", self.address_bus, self.data_bus, self.read_mode);
// println!("COMPUTER: Done ticking.");
}
fn tick_ram(&mut self, address: u16, data: u8, cs: bool, oe: bool, we: bool) {
fn tick_ram(&mut self, address: u16, data: u8, cs: bool, oe: bool, we: bool) -> u8 {
debug!("This system has no ram. ROM only.");
0x00
}
fn tick_rom(&mut self, address: u16, data: u8, cs: bool, oe: bool, we: bool) -> (u8) {
let (_, data) = self.rom.tick(address, data, true);
data
fn tick_rom(&mut self, address: u16, cs: bool, oe: bool) -> u8 {
let data = self.rom.signal_tick(address, self.data_bus, cs, oe, true);
data
}
fn tick_via(&mut self, address: u16, data: u8, cs: bool, rw: bool, ce: bool) -> (u8, u8, bool) {
debug!("This system has no VIA controllers. ROM only");
(0,0,true)
fn tick_via(&mut self, address: u16, data: u8, cs0: bool, cs1: bool, rw: bool, rs0: bool, rs1: bool) -> (u8, bool, bool) {
debug!("This system has no VIA controllers. ROM only");
(0,false,false)
}
}
core/src/computers/rom_only/mod.rs
+1 -1
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@@ -19,7 +19,7 @@ impl RomOnlyComputer {
// tick the parts...
println!("WIDETICK: A:${address:04x} D:${data:02x} C:b{control:08b}");
let (_, new_data) = self.rom.tick(address, data, control == 0x01);
let new_data = self.rom.signal_tick(self.address_bus, self.data_bus, true, true, true);
println!("\nNew Data : {new_data:02x}");
self.set_data_bus(new_data);
new_data
core/src/computers/tim1/mod.rs
+8
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@@ -0,0 +1,8 @@
use crate::mos6502cpu::Mos6502Cpu;
use crate::periph::mos6530::mos6530::Mos6530;
pub struct Tim1 {
cpu: Mos6502Cpu,
pia: Mos6530
}