MOS6520 looking mostly there.

core/src/periph/mos6530/viachip.rs

@@ -1,11 +1,39 @@
 use log::debug;
 use crate::constants::constants_system::{SIZE_1KB, SIZE_32KB};
 use crate::periph::mos6530::mos6530::Mos6530;
+use crate::traits::bus_device::BusDevice;
 use crate::traits::memory_chip::MemoryChip;
 use crate::traits::ram_chip::RamChip;
 use crate::traits::rom_chip::RomChip;
 use crate::traits::via_chip::ViaChip;
 
+impl BusDevice for Mos6530 {
+    fn min_offset(&self) -> u16 {
+        self.ram_offset
+    }
+
+    fn max_offset(&self) -> u16 {
+        self.min_offset() + SIZE_1KB as u16
+    }
+
+    fn address_bus(&self) -> u16 {
+        self.address_bus
+    }
+
+    fn data_bus(&self) -> u8 {
+        self.data_bus
+    }
+
+    fn set_address_bus(&mut self, new_value: u16) {
+        self.address_bus = new_value
+    }
+
+    fn set_data_bus(&mut self, new_value: u8) {
+        self.data_bus = new_value
+    }
+
+}
+
 impl RamChip for Mos6530 {
     fn write(&mut self, offset: &u16, value: &u8) {
         debug!("🐙 Writing ${value:02x} to ${offset:04x}");
@@ -49,4 +77,3 @@ impl ViaChip for Mos6530 {
         debug!("🐙Setting PORT{port_index} to {value:02x}");
     }
 }
-