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fixes address mode of instructions for BCC, BCS, TYA

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This commit is contained in:
Trevor Merritt 2025-07-17 08:56:01 -04:00
parent 6fcf1547d1
commit cad8d5eaa3
2 changed files with 9 additions and 9 deletions
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16
core/src/instruction.rs
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@ -245,7 +245,7 @@ mod test {
vec![0x10, 0xab],
Instruction {
op: BPL,
mode: Implied,
mode: Immediate,
operand: Operand::Byte(0xab),
},
),
@ -253,7 +253,7 @@ mod test {
vec![0x30, 0xab],
Instruction {
op: BMI,
mode: Implied,
mode: Immediate,
operand: Operand::Byte(0xab),
},
),
@ -261,7 +261,7 @@ mod test {
vec![0x50, 0xab],
Instruction {
op: BVC,
mode: Implied,
mode: Immediate,
operand: Operand::Byte(0xab),
},
),
@ -269,7 +269,7 @@ mod test {
vec![0x70, 0xab],
Instruction {
op: BVS,
mode: Implied,
mode: Immediate,
operand: Operand::Byte(0xab),
},
),
@ -277,7 +277,7 @@ mod test {
vec![0x90, 0xab],
Instruction {
op: BCC,
mode: Implied,
mode: Immediate,
operand: Operand::Byte(0xab),
},
),
@ -285,7 +285,7 @@ mod test {
vec![0xb0, 0xab],
Instruction {
op: BCS,
mode: Implied,
mode: Immediate,
operand: Operand::Byte(0xab),
},
),
@ -293,7 +293,7 @@ mod test {
vec![0xd0, 0xab],
Instruction {
op: BNE,
mode: Implied,
mode: Immediate,
operand: Operand::Byte(0xab),
},
),
@ -301,7 +301,7 @@ mod test {
vec![0xf0, 0xab],
Instruction {
op: BEQ,
mode: Implied,
mode: Immediate,
operand: Operand::Byte(0xab),
},
),

2
core/src/instruction_table.rs
View File

@ -215,7 +215,7 @@ pub const INSTRUCTION_TABLE: [Option<OpInfo>; 256] = {
table[ISA_OP_BCC as usize] = Some(OpInfo {
operation: BCC,
mode: AddressMode::Implied,
mode: AddressMode::Immediate,
length: 2,
cycles: 2,
format_prefix: "BCC $",