19 Commits

Author SHA1 Message Date
tmerritt 8c08555003 writes bins better now 2025-07-07 16:28:13 -04:00
tmerritt 9c672741ed start of rom_only PC 2025-07-07 07:36:41 -04:00
tmerritt b9242b1943 rustfmt cleanup 2025-07-06 13:38:55 -04:00
tmerritt cf14804df2 more stuff 2025-07-05 11:49:04 -04:00
tmerritt 2cfd570789 more stuff i worked on 2025-07-03 16:32:55 -04:00
tmerritt e4405cc225 attempt chatgpt emulator for display 2025-07-03 11:41:54 -04:00
tmerritt 8509b20109 improved matrix display stuff 2025-07-03 09:29:46 -04:00
tmerritt 1a53f1d782 more instructions and tests passing. 2025-07-01 16:58:59 -04:00
tmerritt 9b9462c98c fixed size from 32mb to 32kb 2025-07-01 13:14:01 -04:00
tmerritt f9c938757f box swap 2025-07-01 13:08:23 -04:00
tmerritt d97774e97b some instructions have code and tests 2025-06-30 13:55:35 -04:00
tmerritt 9e0e8b5910 closer to ticking.
has microsteps in the UI
decodes from a NOP only binary
some basic instructions are starting to move data around
2025-06-30 08:50:18 -04:00
tmerritt 8ed93fc90e closer to being able to run a cycle? 2025-06-30 07:17:17 -04:00
tmerritt 0c475127f6 BUGFIX: Decoder now decodes instructions without parameters 2025-06-29 10:55:47 -04:00
tmerritt e5c2319803 removes sccache
updates display of ben eater pc
doesnt blow up when creating a rom chip anymore
doesnt blow up when creating a pc anymore
2025-06-28 12:37:01 -04:00
tmerritt d89fc1cd2b decodes all instructions i think.
start of a beneater pc
2025-06-27 12:14:54 -04:00
tmerritt 57544589b3 applies chatgpt suggestions.
...
does not appear to decode everything
2025-06-25 09:34:19 -04:00
tmerritt 1b2fb2c221 from_bytes needs tests
instruction.to_string() passes all its tests.
2025-06-24 11:05:02 -04:00
tmerritt 768e83dfb8 more decode and encode code 2025-06-23 15:35:36 -04:00
91 changed files with 677 additions and 5952 deletions
+5
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@@ -0,0 +1,5 @@
# Default ignored files
/shelf/
/workspace.xml
# Editor-based HTTP Client requests
/httpRequests/
+8
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@@ -0,0 +1,8 @@
<?xml version="1.0" encoding="UTF-8"?>
<project version="4">
<component name="ProjectModuleManager">
<modules>
<module fileurl="file://$PROJECT_DIR$/.idea/mos6502.iml" filepath="$PROJECT_DIR$/.idea/mos6502.iml" />
</modules>
</component>
</project>
+13
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@@ -0,0 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<module type="EMPTY_MODULE" version="4">
<component name="NewModuleRootManager">
<content url="file://$MODULE_DIR$">
<sourceFolder url="file://$MODULE_DIR$/cli/src" isTestSource="false" />
<sourceFolder url="file://$MODULE_DIR$/core/src" isTestSource="false" />
<sourceFolder url="file://$MODULE_DIR$/macroquad/src" isTestSource="false" />
<excludeFolder url="file://$MODULE_DIR$/target" />
</content>
<orderEntry type="inheritedJdk" />
<orderEntry type="sourceFolder" forTests="false" />
</component>
</module>
+6
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@@ -0,0 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<project version="4">
<component name="VcsDirectoryMappings">
<mapping directory="" vcs="Git" />
</component>
</project>
-2
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@@ -1,3 +1 @@
/target
*produced.asm
*produced.bin
-479
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@@ -1,479 +0,0 @@
STA $f3 ; [ 0x85 0xf3 ]
PLA ; [ 0x68 ]
STA $f1 ; [ 0x85 0xf1 ]
PLA ; [ 0x68 ]
STA $ef ; [ 0x85 0xef ]
STA $fa ; [ 0x85 0xfa ]
PLA ; [ 0x68 ]
STA $f0 ; [ 0x85 0xf0 ]
STA $fb ; [ 0x85 0xfb ]
STY $f4 ; [ 0x84 0xf4 ]
STX $f5 ; [ 0x86 0xf5 ]
TSX ; [ 0xba ]
STX $f2 ; [ 0x86 0xf2 ]
JSR $1e88 ; [ 0x20 0x88 0x1e ]
JMP $1c4f ; [ 0x4c 0x4f 0x1c ]
JMP ($17fa) ; [ 0x6c 0xfa 0x17 ]
JMP ($17fe) ; [ 0x6c 0xfe 0x17 ]
LDX #$ff ; [ 0xa2 0xff ]
TXS ; [ 0x9a ]
STX $f2 ; [ 0x86 0xf2 ]
JSR $1e88 ; [ 0x20 0x88 0x1e ]
LDA #$ff ; [ 0xa9 0xff ]
STA $17f3 ; [ 0x8d 0xf3 0x17 ]
LDA #$01 ; [ 0xa9 0x01 ]
BIT $1740 ; [ 0x2c 0x40 0x17 ]
BNE #$19 ; [ 0xd0 0x19 ]
BMI #$f9 ; [ 0x30 0xf9 ]
LDA #$fc ; [ 0xa9 0xfc ]
CLC ; [ 0x18 ]
ADC #$01 ; [ 0x69 0x01 ]
BCC $03 ; [ 0x90 0x03 ]
INC $17f3 ; [ 0xee 0xf3 0x17 ]
LDY $1740 ; [ 0xac 0x40 0x17 ]
BPL #$f3 ; [ 0x10 0xf3 ]
STA $17f2 ; [ 0x8d 0xf2 0x17 ]
LDX #$08 ; [ 0xa2 0x08 ]
JSR $1e6a ; [ 0x20 0x6a 0x1e ]
JSR $1e8c ; [ 0x20 0x8c 0x1e ]
LDA #$01 ; [ 0xa9 0x01 ]
BIT $1740 ; [ 0x2c 0x40 0x17 ]
BNE #$1e ; [ 0xd0 0x1e ]
JSR $1e2f ; [ 0x20 0x2f 0x1e ]
LDX #$0a ; [ 0xa2 0x0a ]
JSR $1e31 ; [ 0x20 0x31 0x1e ]
JMP $1daf ; [ 0x4c 0xaf 0x1d ]
LDA #$00 ; [ 0xa9 0x00 ]
STA $f8 ; [ 0x85 0xf8 ]
STA $f9 ; [ 0x85 0xf9 ]
JSR $1e5a ; [ 0x20 0x5a 0x1e ]
CMP #$01 ; [ 0xc9 0x01 ]
BEQ $06 ; [ 0xf0 0x06 ]
JSR $1fac ; [ 0x20 0xac 0x1f ]
JMP $1ddb ; [ 0x4c 0xdb 0x1d ]
JSR $1f19 ; [ 0x20 0x19 0x1f ]
BNE #$d3 ; [ 0xd0 0xd3 ]
LDA #$01 ; [ 0xa9 0x01 ]
BIT $1740 ; [ 0x2c 0x40 0x17 ]
BEQ $cc ; [ 0xf0 0xcc ]
JSR $1f19 ; [ 0x20 0x19 0x1f ]
BEQ $f4 ; [ 0xf0 0xf4 ]
JSR $1f19 ; [ 0x20 0x19 0x1f ]
BEQ $ef ; [ 0xf0 0xef ]
JSR $1f6a ; [ 0x20 0x6a 0x1f ]
CMP #$15 ; [ 0xc9 0x15 ]
BPL #$bb ; [ 0x10 0xbb ]
CMP #$14 ; [ 0xc9 0x14 ]
BEQ $44 ; [ 0xf0 0x44 ]
CMP #$10 ; [ 0xc9 0x10 ]
BEQ $2c ; [ 0xf0 0x2c ]
CMP #$11 ; [ 0xc9 0x11 ]
BEQ $2c ; [ 0xf0 0x2c ]
CMP #$12 ; [ 0xc9 0x12 ]
BEQ $2f ; [ 0xf0 0x2f ]
CMP #$13 ; [ 0xc9 0x13 ]
BEQ $31 ; [ 0xf0 0x31 ]
ASL ; [ 0x0a ]
ASL ; [ 0x0a ]
ASL ; [ 0x0a ]
ASL ; [ 0x0a ]
STA $fc ; [ 0x85 0xfc ]
LDX #$04 ; [ 0xa2 0x04 ]
LDY $ff ; [ 0xa4 0xff ]
BNE #$0a ; [ 0xd0 0x0a ]
LDA ($fa),Y ; [ 0xb1 0xfa ]
ASL $fc ; [ 0x06 0xfc ]
ROL ; [ 0x2a ]
STA ($fa),Y ; [ 0x91 0xfa ]
JMP $1cc3 ; [ 0x4c 0xc3 0x1c ]
ASL ; [ 0x0a ]
ROL $fa ; [ 0x26 0xfa ]
ROL $fb ; [ 0x26 0xfb ]
DEX ; [ 0xca ]
BNE #$ea ; [ 0xd0 0xea ]
BEQ $08 ; [ 0xf0 0x08 ]
LDA #$01 ; [ 0xa9 0x01 ]
BNE #$02 ; [ 0xd0 0x02 ]
LDA #$00 ; [ 0xa9 0x00 ]
STA $ff ; [ 0x85 0xff ]
JMP $1c4f ; [ 0x4c 0x4f 0x1c ]
JSR $1f63 ; [ 0x20 0x63 0x1f ]
JMP $1c4f ; [ 0x4c 0x4f 0x1c ]
JMP $1dc8 ; [ 0x4c 0xc8 0x1d ]
LDA $ef ; [ 0xa5 0xef ]
STA $fa ; [ 0x85 0xfa ]
LDA $f0 ; [ 0xa5 0xf0 ]
STA $fb ; [ 0x85 0xfb ]
JMP $1c4f ; [ 0x4c 0x4f 0x1c ]
JSR $1e5a ; [ 0x20 0x5a 0x1e ]
CMP #$3b ; [ 0xc9 0x3b ]
BNE #$f9 ; [ 0xd0 0xf9 ]
LDA #$00 ; [ 0xa9 0x00 ]
STA $f7 ; [ 0x85 0xf7 ]
STA $f6 ; [ 0x85 0xf6 ]
JSR $1f9d ; [ 0x20 0x9d 0x1f ]
TAX ; [ 0xaa ]
JSR $1f91 ; [ 0x20 0x91 0x1f ]
JSR $1f9d ; [ 0x20 0x9d 0x1f ]
STA $fb ; [ 0x85 0xfb ]
JSR $1f91 ; [ 0x20 0x91 0x1f ]
JSR $1f9d ; [ 0x20 0x9d 0x1f ]
STA $fa ; [ 0x85 0xfa ]
JSR $1f91 ; [ 0x20 0x91 0x1f ]
TXA ; [ 0x8a ]
BEQ $0f ; [ 0xf0 0x0f ]
JSR $1f9d ; [ 0x20 0x9d 0x1f ]
STA ($fa),Y ; [ 0x91 0xfa ]
JSR $1f91 ; [ 0x20 0x91 0x1f ]
JSR $1f63 ; [ 0x20 0x63 0x1f ]
DEX ; [ 0xca ]
BNE #$f2 ; [ 0xd0 0xf2 ]
INX ; [ 0xe8 ]
JSR $1f9d ; [ 0x20 0x9d 0x1f ]
CMP $f6 ; [ 0xc5 0xf6 ]
BNE #$17 ; [ 0xd0 0x17 ]
JSR $1f9d ; [ 0x20 0x9d 0x1f ]
CMP $f7 ; [ 0xc5 0xf7 ]
BNE #$13 ; [ 0xd0 0x13 ]
TXA ; [ 0x8a ]
BNE #$b9 ; [ 0xd0 0xb9 ]
LDX #$0c ; [ 0xa2 0x0c ]
LDA #$27 ; [ 0xa9 0x27 ]
STA $1742 ; [ 0x8d 0x42 0x17 ]
JSR $1e31 ; [ 0x20 0x31 0x1e ]
JMP $1c4f ; [ 0x4c 0x4f 0x1c ]
JSR $1f9d ; [ 0x20 0x9d 0x1f ]
LDX #$11 ; [ 0xa2 0x11 ]
BNE #$ee ; [ 0xd0 0xee ]
LDA #$00 ; [ 0xa9 0x00 ]
STA $f8 ; [ 0x85 0xf8 ]
STA $f9 ; [ 0x85 0xf9 ]
LDA #$00 ; [ 0xa9 0x00 ]
STA $f6 ; [ 0x85 0xf6 ]
STA $f7 ; [ 0x85 0xf7 ]
JSR $1e2f ; [ 0x20 0x2f 0x1e ]
LDA #$3b ; [ 0xa9 0x3b ]
JSR $1ea0 ; [ 0x20 0xa0 0x1e ]
LDA $fa ; [ 0xa5 0xfa ]
CMP $17f7 ; [ 0xcd 0xf7 0x17 ]
LDA $fb ; [ 0xa5 0xfb ]
SBC $17f8 ; [ 0xed 0xf8 0x17 ]
BCC $18 ; [ 0x90 0x18 ]
LDA #$00 ; [ 0xa9 0x00 ]
JSR $1e3b ; [ 0x20 0x3b 0x1e ]
JSR $1fcc ; [ 0x20 0xcc 0x1f ]
JSR $1e1e ; [ 0x20 0x1e 0x1e ]
LDA $f6 ; [ 0xa5 0xf6 ]
JSR $1e3b ; [ 0x20 0x3b 0x1e ]
LDA $f7 ; [ 0xa5 0xf7 ]
JSR $1e3b ; [ 0x20 0x3b 0x1e ]
JMP $1c64 ; [ 0x4c 0x64 0x1c ]
LDA #$18 ; [ 0xa9 0x18 ]
TAX ; [ 0xaa ]
JSR $1e3b ; [ 0x20 0x3b 0x1e ]
JSR $1f91 ; [ 0x20 0x91 0x1f ]
JSR $1e1e ; [ 0x20 0x1e 0x1e ]
LDY #$00 ; [ 0xa0 0x00 ]
LDA ($fa),Y ; [ 0xb1 0xfa ]
JSR $1e3b ; [ 0x20 0x3b 0x1e ]
JSR $1f91 ; [ 0x20 0x91 0x1f ]
JSR $1f63 ; [ 0x20 0x63 0x1f ]
DEX ; [ 0xca ]
BNE #$f0 ; [ 0xd0 0xf0 ]
LDA $f6 ; [ 0xa5 0xf6 ]
JSR $1e3b ; [ 0x20 0x3b 0x1e ]
LDA $f7 ; [ 0xa5 0xf7 ]
JSR $1e3b ; [ 0x20 0x3b 0x1e ]
INC $f8 ; [ 0xe6 0xf8 ]
BNE #$02 ; [ 0xd0 0x02 ]
INC $f9 ; [ 0xe6 0xf9 ]
JMP $1d48 ; [ 0x4c 0x48 0x1d ]
JSR $1fcc ; [ 0x20 0xcc 0x1f ]
JSR $1e2f ; [ 0x20 0x2f 0x1e ]
JSR $1e1e ; [ 0x20 0x1e 0x1e ]
JSR $1e9e ; [ 0x20 0x9e 0x1e ]
LDY #$00 ; [ 0xa0 0x00 ]
LDA ($fa),Y ; [ 0xb1 0xfa ]
JSR $1e3b ; [ 0x20 0x3b 0x1e ]
JSR $1e9e ; [ 0x20 0x9e 0x1e ]
JMP $1c64 ; [ 0x4c 0x64 0x1c ]
JSR $1f63 ; [ 0x20 0x63 0x1f ]
JMP $1dac ; [ 0x4c 0xac 0x1d ]
LDX $f2 ; [ 0xa6 0xf2 ]
TXS ; [ 0x9a ]
LDA $fb ; [ 0xa5 0xfb ]
PHA ; [ 0x48 ]
LDA $fa ; [ 0xa5 0xfa ]
PHA ; [ 0x48 ]
LDA $f1 ; [ 0xa5 0xf1 ]
PHA ; [ 0x48 ]
LDX $f5 ; [ 0xa6 0xf5 ]
LDY $f4 ; [ 0xa4 0xf4 ]
LDA $f3 ; [ 0xa5 0xf3 ]
RTI ; [ 0x40 ]
CMP #$20 ; [ 0xc9 0x20 ]
BEQ $ca ; [ 0xf0 0xca ]
CMP #$7f ; [ 0xc9 0x7f ]
BEQ $1b ; [ 0xf0 0x1b ]
CMP #$0d ; [ 0xc9 0x0d ]
BEQ $db ; [ 0xf0 0xdb ]
CMP #$0a ; [ 0xc9 0x0a ]
BEQ $1c ; [ 0xf0 0x1c ]
CMP #$2e ; [ 0xc9 0x2e ]
BEQ $26 ; [ 0xf0 0x26 ]
CMP #$47 ; [ 0xc9 0x47 ]
BEQ $d5 ; [ 0xf0 0xd5 ]
CMP #$51 ; [ 0xc9 0x51 ]
BEQ $0a ; [ 0xf0 0x0a ]
CMP #$4c ; [ 0xc9 0x4c ]
BEQ $09 ; [ 0xf0 0x09 ]
JMP $1c6a ; [ 0x4c 0x6a 0x1c ]
JMP $1c4f ; [ 0x4c 0x4f 0x1c ]
JMP $1d42 ; [ 0x4c 0x42 0x1d ]
JMP $1ce7 ; [ 0x4c 0xe7 0x1c ]
SEC ; [ 0x38 ]
LDA $fa ; [ 0xa5 0xfa ]
SBC #$01 ; [ 0xe9 0x01 ]
STA $fa ; [ 0x85 0xfa ]
BCS $02 ; [ 0xb0 0x02 ]
DEC $fb ; [ 0xc6 0xfb ]
JMP $1dac ; [ 0x4c 0xac 0x1d ]
LDY #$00 ; [ 0xa0 0x00 ]
LDA $f8 ; [ 0xa5 0xf8 ]
STA ($fa),Y ; [ 0x91 0xfa ]
JMP $1dc2 ; [ 0x4c 0xc2 0x1d ]
LDA $fb ; [ 0xa5 0xfb ]
JSR $1e3b ; [ 0x20 0x3b 0x1e ]
JSR $1f91 ; [ 0x20 0x91 0x1f ]
LDA $fa ; [ 0xa5 0xfa ]
JSR $1e3b ; [ 0x20 0x3b 0x1e ]
JSR $1f91 ; [ 0x20 0x91 0x1f ]
RTS ; [ 0x60 ]
LDX #$07 ; [ 0xa2 0x07 ]
LDA $1fd5,X ; [ 0xbd 0xd5 0x1f ]
JSR $1ea0 ; [ 0x20 0xa0 0x1e ]
DEX ; [ 0xca ]
BPL #$f7 ; [ 0x10 0xf7 ]
RTS ; [ 0x60 ]
STA $fc ; [ 0x85 0xfc ]
LSR ; [ 0x4a ]
LSR ; [ 0x4a ]
LSR ; [ 0x4a ]
LSR ; [ 0x4a ]
JSR $1e4c ; [ 0x20 0x4c 0x1e ]
LDA $fc ; [ 0xa5 0xfc ]
JSR $1e4c ; [ 0x20 0x4c 0x1e ]
LDA $fc ; [ 0xa5 0xfc ]
RTS ; [ 0x60 ]
AND #$0f ; [ 0x29 0x0f ]
CMP #$0a ; [ 0xc9 0x0a ]
CLC ; [ 0x18 ]
BMI #$02 ; [ 0x30 0x02 ]
ADC #$07 ; [ 0x69 0x07 ]
ADC #$30 ; [ 0x69 0x30 ]
JMP $1ea0 ; [ 0x4c 0xa0 0x1e ]
STX $fd ; [ 0x86 0xfd ]
LDX #$08 ; [ 0xa2 0x08 ]
LDA #$01 ; [ 0xa9 0x01 ]
BIT $1740 ; [ 0x2c 0x40 0x17 ]
BNE #$22 ; [ 0xd0 0x22 ]
BMI #$f9 ; [ 0x30 0xf9 ]
JSR $1ed4 ; [ 0x20 0xd4 0x1e ]
JSR $1eeb ; [ 0x20 0xeb 0x1e ]
LDA $1740 ; [ 0xad 0x40 0x17 ]
AND #$80 ; [ 0x29 0x80 ]
LSR $fe ; [ 0x46 0xfe ]
ORA $fe ; [ 0x05 0xfe ]
STA $fe ; [ 0x85 0xfe ]
JSR $1ed4 ; [ 0x20 0xd4 0x1e ]
DEX ; [ 0xca ]
BNE #$ef ; [ 0xd0 0xef ]
JSR $1eeb ; [ 0x20 0xeb 0x1e ]
LDX $fd ; [ 0xa6 0xfd ]
LDA $fe ; [ 0xa5 0xfe ]
ROL ; [ 0x2a ]
LSR ; [ 0x4a ]
RTS ; [ 0x60 ]
LDX #$01 ; [ 0xa2 0x01 ]
STX $ff ; [ 0x86 0xff ]
LDX #$00 ; [ 0xa2 0x00 ]
STX $1741 ; [ 0x8e 0x41 0x17 ]
LDX #$3f ; [ 0xa2 0x3f ]
STX $1743 ; [ 0x8e 0x43 0x17 ]
LDX #$07 ; [ 0xa2 0x07 ]
STX $1742 ; [ 0x8e 0x42 0x17 ]
CLD ; [ 0xd8 ]
SEI ; [ 0x78 ]
RTS ; [ 0x60 ]
LDA #$20 ; [ 0xa9 0x20 ]
STA $fe ; [ 0x85 0xfe ]
STX $fd ; [ 0x86 0xfd ]
JSR $1ed4 ; [ 0x20 0xd4 0x1e ]
LDA $1742 ; [ 0xad 0x42 0x17 ]
AND #$fe ; [ 0x29 0xfe ]
STA $1742 ; [ 0x8d 0x42 0x17 ]
JSR $1ed4 ; [ 0x20 0xd4 0x1e ]
LDX #$08 ; [ 0xa2 0x08 ]
LDA $1742 ; [ 0xad 0x42 0x17 ]
AND #$fe ; [ 0x29 0xfe ]
LSR $fe ; [ 0x46 0xfe ]
ADC #$00 ; [ 0x69 0x00 ]
STA $1742 ; [ 0x8d 0x42 0x17 ]
JSR $1ed4 ; [ 0x20 0xd4 0x1e ]
DEX ; [ 0xca ]
BNE #$ee ; [ 0xd0 0xee ]
LDA $1742 ; [ 0xad 0x42 0x17 ]
ORA #$01 ; [ 0x09 0x01 ]
STA $1742 ; [ 0x8d 0x42 0x17 ]
JSR $1ed4 ; [ 0x20 0xd4 0x1e ]
LDX $fd ; [ 0xa6 0xfd ]
RTS ; [ 0x60 ]
LDA $17f3 ; [ 0xad 0xf3 0x17 ]
STA $17f4 ; [ 0x8d 0xf4 0x17 ]
LDA $17f2 ; [ 0xad 0xf2 0x17 ]
SEC ; [ 0x38 ]
SBC #$01 ; [ 0xe9 0x01 ]
BCS $03 ; [ 0xb0 0x03 ]
DEC $17f4 ; [ 0xce 0xf4 0x17 ]
LDY $17f4 ; [ 0xac 0xf4 0x17 ]
BPL #$f3 ; [ 0x10 0xf3 ]
RTS ; [ 0x60 ]
LDA $17f3 ; [ 0xad 0xf3 0x17 ]
STA $17f4 ; [ 0x8d 0xf4 0x17 ]
LDA $17f2 ; [ 0xad 0xf2 0x17 ]
LSR ; [ 0x4a ]
LSR $17f4 ; [ 0x4e 0xf4 0x17 ]
BCC $e3 ; [ 0x90 0xe3 ]
ORA #$80 ; [ 0x09 0x80 ]
BCS $e0 ; [ 0xb0 0xe0 ]
LDY #$03 ; [ 0xa0 0x03 ]
LDX #$01 ; [ 0xa2 0x01 ]
LDA #$ff ; [ 0xa9 0xff ]
STX $1742 ; [ 0x8e 0x42 0x17 ]
INX ; [ 0xe8 ]
INX ; [ 0xe8 ]
AND $1740 ; [ 0x2d 0x40 0x17 ]
DEY ; [ 0x88 ]
BNE #$f5 ; [ 0xd0 0xf5 ]
LDY #$07 ; [ 0xa0 0x07 ]
STY $1742 ; [ 0x8c 0x42 0x17 ]
ORA #$80 ; [ 0x09 0x80 ]
EOR #$ff ; [ 0x49 0xff ]
RTS ; [ 0x60 ]
LDY #$00 ; [ 0xa0 0x00 ]
LDA ($fa),Y ; [ 0xb1 0xfa ]
STA $f9 ; [ 0x85 0xf9 ]
LDA #$7f ; [ 0xa9 0x7f ]
STA $1741 ; [ 0x8d 0x41 0x17 ]
LDX #$09 ; [ 0xa2 0x09 ]
LDY #$03 ; [ 0xa0 0x03 ]
LDA $00f8,Y ; [ 0xb9 0xf8 0x00 ]
LSR ; [ 0x4a ]
LSR ; [ 0x4a ]
LSR ; [ 0x4a ]
LSR ; [ 0x4a ]
JSR $1f48 ; [ 0x20 0x48 0x1f ]
LDA $00f8,Y ; [ 0xb9 0xf8 0x00 ]
AND #$0f ; [ 0x29 0x0f ]
JSR $1f48 ; [ 0x20 0x48 0x1f ]
DEY ; [ 0x88 ]
BNE #$eb ; [ 0xd0 0xeb ]
STX $1742 ; [ 0x8e 0x42 0x17 ]
LDA #$00 ; [ 0xa9 0x00 ]
STA $1741 ; [ 0x8d 0x41 0x17 ]
JMP $1efe ; [ 0x4c 0xfe 0x1e ]
STY $fc ; [ 0x84 0xfc ]
TAY ; [ 0xa8 ]
LDA $1fe7,Y ; [ 0xb9 0xe7 0x1f ]
LDY #$00 ; [ 0xa0 0x00 ]
STY $1740 ; [ 0x8c 0x40 0x17 ]
STX $1742 ; [ 0x8e 0x42 0x17 ]
STA $1740 ; [ 0x8d 0x40 0x17 ]
LDY #$7f ; [ 0xa0 0x7f ]
DEY ; [ 0x88 ]
BNE #$fd ; [ 0xd0 0xfd ]
INX ; [ 0xe8 ]
INX ; [ 0xe8 ]
LDY $fc ; [ 0xa4 0xfc ]
RTS ; [ 0x60 ]
INC $fa ; [ 0xe6 0xfa ]
BNE #$02 ; [ 0xd0 0x02 ]
INC $fb ; [ 0xe6 0xfb ]
RTS ; [ 0x60 ]
LDX #$21 ; [ 0xa2 0x21 ]
LDY #$01 ; [ 0xa0 0x01 ]
JSR $1f02 ; [ 0x20 0x02 0x1f ]
BNE #$07 ; [ 0xd0 0x07 ]
CPX #$27 ; [ 0xe0 0x27 ]
BNE #$f5 ; [ 0xd0 0xf5 ]
LDA #$15 ; [ 0xa9 0x15 ]
RTS ; [ 0x60 ]
LDY #$ff ; [ 0xa0 0xff ]
ASL ; [ 0x0a ]
BCS $03 ; [ 0xb0 0x03 ]
INY ; [ 0xc8 ]
BPL #$fa ; [ 0x10 0xfa ]
TXA ; [ 0x8a ]
AND #$0f ; [ 0x29 0x0f ]
LSR ; [ 0x4a ]
TAX ; [ 0xaa ]
TYA ; [ 0x98 ]
BPL #$03 ; [ 0x10 0x03 ]
CLC ; [ 0x18 ]
ADC #$07 ; [ 0x69 0x07 ]
DEX ; [ 0xca ]
BNE #$fa ; [ 0xd0 0xfa ]
RTS ; [ 0x60 ]
CLC ; [ 0x18 ]
ADC $f7 ; [ 0x65 0xf7 ]
STA $f7 ; [ 0x85 0xf7 ]
LDA $f6 ; [ 0xa5 0xf6 ]
ADC #$00 ; [ 0x69 0x00 ]
STA $f6 ; [ 0x85 0xf6 ]
RTS ; [ 0x60 ]
JSR $1e5a ; [ 0x20 0x5a 0x1e ]
JSR $1fac ; [ 0x20 0xac 0x1f ]
JSR $1e5a ; [ 0x20 0x5a 0x1e ]
JSR $1fac ; [ 0x20 0xac 0x1f ]
LDA $f8 ; [ 0xa5 0xf8 ]
RTS ; [ 0x60 ]
CMP #$30 ; [ 0xc9 0x30 ]
BMI #$1b ; [ 0x30 0x1b ]
CMP #$47 ; [ 0xc9 0x47 ]
BPL #$17 ; [ 0x10 0x17 ]
CMP #$40 ; [ 0xc9 0x40 ]
BMI #$03 ; [ 0x30 0x03 ]
CLC ; [ 0x18 ]
ADC #$09 ; [ 0x69 0x09 ]
ROL ; [ 0x2a ]
ROL ; [ 0x2a ]
ROL ; [ 0x2a ]
ROL ; [ 0x2a ]
LDY #$04 ; [ 0xa0 0x04 ]
ROL ; [ 0x2a ]
ROL $f8 ; [ 0x26 0xf8 ]
ROL $f9 ; [ 0x26 0xf9 ]
DEY ; [ 0x88 ]
BNE #$f8 ; [ 0xd0 0xf8 ]
LDA #$00 ; [ 0xa9 0x00 ]
RTS ; [ 0x60 ]
LDA $f8 ; [ 0xa5 0xf8 ]
STA $fa ; [ 0x85 0xfa ]
LDA $f9 ; [ 0xa5 0xf9 ]
STA $fb ; [ 0x85 0xfb ]
RTS ; [ 0x60 ]
BRK ; [ 0x00 ]
BRK ; [ 0x00 ]
BRK ; [ 0x00 ]
BRK ; [ 0x00 ]
BRK ; [ 0x00 ]
BRK ; [ 0x00 ]
ASL ; [ 0x0a ]
ORA $494d ; [ 0x0d 0x4d 0x49 ]
JSR $5213 ; [ 0x20 0x13 0x52 ]
EOR $20 ; [ 0x45 0x20 ]
STX $db ; [ 0x86 0xdb ]
INC $ed ; [ 0xe6 0xed ]
SBC $ff87,X ; [ 0xfd 0x87 0xff ]
LDA $f9de,Y ; [ 0xb9 0xde 0xf9 ]
SBC ($ff),Y ; [ 0xf1 0xff ]
Generated
+231 -3119
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File diff suppressed because it is too large Load Diff
+8 -8
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@@ -8,7 +8,6 @@ use core::mos6502cpu::cpu::Mos6502Cpu;
use core::periph::at28c256::At28C256;
use core::periph::hm62256::Hm62256;
use core::constants::constants_system::*;
use std::fs;
/// BenEater computer represents the 'Ben Eater' 6502 breadboard computer.
/// This was built along watching the video series where Ben builds a
@@ -21,19 +20,20 @@ pub struct BenEater {
}
impl BenEater {
// pub fn new(rom: &[u8; SIZE_32KB]) -> BenEater {
//
// }
pub fn new(rom: &[u8; SIZE_32KB]) -> BenEater {
}
}
#[macroquad::main("Ben Eaters PC")]
async fn main() {
println!("Taxation is Theft");
// let rom_to_run = fs::read("resources/beneater/roms/ror.bin");
// let mut pc = BenEater::new(&rom_to_run);
//
// let mut backplane = Backplane::new();
let rom_to_run = fs::read("resources/beneater/roms/ror.bin");
let mut pc = BenEater::new(&rom_to_run);
let mut backplane = Backplane::new();
// backplane.load_rom("resources/beneater/roms/ror.bin");
// let mut dm = DisplayMatrix::new(200.0, 50.0);
+1 -11
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@@ -21,34 +21,24 @@ fn main() {
// Fill with 0xea -> NOP
let mut vec: [u8; SIZE_32KB] = [ISA_OP_NOP; SIZE_32KB];
// Load to A
vec[0] = ISA_OP_LDA_I; // LDA #$ab
vec[1] = 0b1010_1011; // 1010 1011
// Jump to rotate cycle
vec[2] = 0x02; // --
vec[3] = 0x03; // --
// Jump to Main
vec[0x2210] = ISA_OP_JMP_ABS;
vec[0x2211] = 0x00;
vec[0x2212] = 0x40;
// load to a
vec[0x4000] = ISA_OP_LDA_I;
vec[0x4001] = 0b0101_0100;
// jump to top of load to a
vec[0x4002] = ISA_OP_JMP_ABS;
vec[0x4003] = 0x00;
vec[0x4004] = 0x40;
vec[0x4005] = ISA_OP_NOP;
vec[0x7ffa] = 0x22; // NMI Vector
vec[0x7ffb] = 0x11;
vec[0x7ffc] = 0x12; // Reset Vector
vec[0x7ffd] = 0x34;
vec[0x7ffe] = 0x43; // Interrupt Vector
vec[0x7fff] = 0x21;
vec = le_swap(&vec);
// write the rom to disk
+1 -5
View File
@@ -8,10 +8,6 @@ fn main() {
let mut backplane = Backplane::new();
for i in 0..12 {
backplane.tick();
}
//backplane.load_rom();
println!("Backplane is live.");
@@ -20,7 +16,7 @@ fn main() {
new_program[(OFFSET_RESET_VECTOR + 1 - SIZE_32KB as u16) as usize] = 0x60;
println!("Set offset in rom...");
println!(
"VALUE AT OFFSET_RESET_VECTOR = 0x{:04x} ",
"VALUE AT OFFSET_RESET_VECTOR = 0x{:02x} ",
new_program[(OFFSET_RESET_VECTOR - SIZE_32KB as u16) as usize]
);
// println!("{:?}", new_program);
+2 -2
View File
@@ -19,7 +19,7 @@ pub struct Backplane {
// pub for dev
pub cpu: Mos6502Cpu,
pub via: VIA6522,
pub memory: Box<[u8]>,
pub memory: Box<[u8; SIZE_32KB]>,
pub rom: At28C256,
data_bus: u8,
address_bus: u16
@@ -38,7 +38,7 @@ impl Backplane {
}
pub fn load_rom(&mut self, to_load: &[u8; SIZE_32KB]) {
self.rom.program((*to_load).into());
self.rom.program(to_load);
}
pub fn tick(&mut self) {
+1 -1
View File
@@ -7,7 +7,7 @@ pub struct CpuDisplay {}
impl CpuDisplay {
pub fn render(cpu: &Mos6502Cpu, x_offset: f32, y_offset: f32) {
// get the data to display...
let (pc, a, x, y, address_bus, data_bus, microsteps_remaining, reset_vector, interrupt_vector, nmi_vector) = cpu.dump_data();
let (pc, a, x, y, address_bus, data_bus, microsteps_remaining, reset_vector, interrupt_vector) = cpu.dump_data();
// ...build the interface
Self::draw_square(x_offset, y_offset, x_offset + 300.0, y_offset + 85.0, BLACK);
-1
View File
@@ -201,7 +201,6 @@ mod tests {
}
#[test]
#[ignore]
fn test_write_data() {
let mut lcd = HD44780::new();
lcd.set_data_bus(0x41); // 'A'
-4
View File
@@ -162,7 +162,6 @@ mod tests {
}
#[test]
#[ignore]
fn test_timer1_write_and_tick() {
let mut via = VIA6522::new();
@@ -181,7 +180,6 @@ mod tests {
}
#[test]
#[ignore]
fn test_timer2_write_and_tick() {
let mut via = VIA6522::new();
via.t2_enabled = true;
@@ -196,7 +194,6 @@ mod tests {
}
#[test]
#[ignore]
fn test_interrupt_enable_disable() {
let mut via = VIA6522::new();
@@ -208,7 +205,6 @@ mod tests {
}
#[test]
#[ignore]
fn test_clear_interrupt_flags() {
let mut via = VIA6522::new();
via.ifr = 0xFF;
-223
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@@ -1,223 +0,0 @@
/*
64tass -a -o instructions.bin -b instructions.asm &&
cargo run --bin de6502 -- -v instructions.bin instructions_produced.asm &&
64tass -a -b instructions_produced.asm -o instructions_produced.bin
*/
use std::collections::HashMap;
use std::fs;
use std::fs::File;
use std::path::PathBuf;
use std::thread::current;
use core::constants::constants_system::*;
use core::constants::constants_isa_op::*;
use clap::{Parser, Subcommand};
use core::instruction_table::INSTRUCTION_TABLE;
use std::io::Write;
#[derive(Parser)]
#[command(version, about, long_about = None)]
struct CliOptions {
/// File to Decompile
input: PathBuf,
/// File to write
output: PathBuf,
/// Verbose output
#[arg(short, action = clap::ArgAction::Count)]
verbose: u8
}
#[derive(Debug)]
struct DecompiledLine {
offset: u16,
text: String,
label: Option<String>,
bytes: Vec<u8>
}
impl DecompiledLine {
/// is_jump
///
/// Check if the current line is a type of a jump
pub fn is_jump(&self) -> bool {
self.bytes[0] == ISA_OP_JMP_ABS || self.bytes[0] == ISA_OP_JMP_IND
}
/// is_branch
///
/// Check if the current line is a branch
pub fn is_branch(&self) -> bool {
self.bytes[0] == ISA_OP_BCC || self.bytes[0] == ISA_OP_BCS ||
self.bytes[0] == ISA_OP_BEQ || self.bytes[0] == ISA_OP_BMI ||
self.bytes[0] == ISA_OP_BNE || self.bytes[0] == ISA_OP_BPL ||
self.bytes[0] == ISA_OP_BVS || self.bytes[0] == ISA_OP_BVC
}
}
/// WorkingProgram
///
/// Where we keep the program being decompiled
struct WorkingProgram {
data: [u8; SIZE_64KB],
lines: Vec<DecompiledLine>
}
impl WorkingProgram {
}
fn parse_to_decompiled_lines(data: &[u8]) -> HashMap<u16, DecompiledLine> {
println!("PARSE GOT {}b", data.len());
let mut current_data_position = 0;
let mut lines: HashMap<u16, DecompiledLine> = HashMap::new();
while current_data_position < data.len() as u16 {
// read the next byte.
let next_byte = data[current_data_position as usize];
let mut bytes = vec![next_byte];
println!("Bytes = {bytes:?}");
let target_op = INSTRUCTION_TABLE[next_byte as usize].clone();
if let Some(top) = target_op {
// println!("Instruction {:?}/{:?} needs {:?} bytes.", top.operation, top.mode, top.length);
let num_bytes_to_load = top.length - 1;
// println!("Need {num_bytes_to_load} more bytes.");
let mut formatted_asm = String::from(top.format_prefix);
let mut param = None;
if num_bytes_to_load == 1 {
bytes.push(data[current_data_position as usize + 1]);
formatted_asm = format!("{}{:02x}{}", formatted_asm, bytes[1], top.format_postfix);
};
if num_bytes_to_load == 2 {
bytes.push(data[current_data_position as usize + 1]);
bytes.push(data[current_data_position as usize + 2]);
// 16 bit parameter.
param = Some(((bytes[2] as u16) << 8) | bytes[1] as u16);
formatted_asm = format!("{}{:04x}{}", formatted_asm, param.unwrap(), top.format_postfix);
};
// figure out how long the instruction is and read that much more data
lines.insert(current_data_position, DecompiledLine {
offset: current_data_position,
text: String::from(formatted_asm),
label: None,
bytes,
});
current_data_position = current_data_position + top.length as u16;
} else {
// invalid instruction
println!("Byte sequence 0x{} invalid.", next_byte);
current_data_position += 1;
}
}
lines
}
fn decompile(data: &Vec<u8>) -> Vec<(u16, DecompiledLine)> {
println!("Preparing to decompile {}b", data.len());
let mut current_data_position: u16 = 0;
let mut lines: HashMap<u16, DecompiledLine> = parse_to_decompiled_lines(data);
println!("Found {} instructions in pass 1. Adding labels for jumps.", lines.len());
//let targets = vec![];
let mut items: Vec<_> = lines.into_iter().collect();
items.sort_by(|a, b| a.0.cmp(&b.0));
// loop through the lines for JSR and label the 'target' as SUB<index>
// let mut jump_targets = vec![];
for (line_index, working_line) in &mut items {
if working_line.is_jump() {
println!("There are {}b in bytes", working_line.bytes.len());
let target = read_word(&working_line.bytes[1..=2]);
println!("Found a jump at index {line_index} / 0x{line_index} with target of 0x{:04x}", target);;
// Derp -> this doesnt work.
// items[target as usize].1.label = Some("Label1".parse().unwrap());
}
}
// // check the vectors to label those entrypoints.
// let (mut main, mut nmi, mut irq) = (0, 0, 0);
// match data.len() {
// SIZE_32KB | SIZE_64KB => {
// main = read_word(&data[OFFSET_RESET_VECTORS..=OFFSET_RESET_VECTORS + 1]);
// nmi = read_word(&data[OFFSET_NMI_VECTORS..=OFFSET_NMI_VECTORS + 1]);
// irq = read_word(&data[OFFSET_INT_VECTORS..=OFFSET_INT_VECTORS]);
// }
// _ => {
// // dont know where to look for our offsets. :(
// }
// }
// -> main
// -> NMI
// -> IRQ
items
}
/// read_word
///
/// Read a word from the provided data with first byte being
/// LSB
fn read_word(from: &[u8]) -> u16 {
(from[1] as u16) << 8 | from[0] as u16
}
/// read_word_swap
///
/// Read a word from the provided data with first byte being
/// MSB
fn read_word_swap(from: &[u8]) -> u16 {
(from[0] as u16) << 8 | from[1] as u16
}
/// format_bytes
///
/// formats data for stuff
fn format_bytes(from: &Vec<u8>) -> String {
let mut to_return = String::from("[");
for index in 0..from.len() {
to_return = format!("{} 0x{:02x}", to_return, from[index]);
}
to_return = format!("{} ]", to_return);
to_return
}
fn main() {
let opts = CliOptions::parse();
println!("Taxation is theft.");
// Load program to an array...
let data = vec![
0xa9, 0xab, 0x4c, 0x00, 0x40, 0xa9, 0x54, 0x4c, 0x00, 0x40,
ISA_OP_TYA, ISA_OP_TXA, ISA_OP_TSX
];
let loaded_data = fs::read(opts.input).unwrap();
println!("Loaded {}b", loaded_data.len());
// ...load the array to the WorkingProgram structure...
let result = decompile(&loaded_data);
let mut output_file = File::create(opts.output).unwrap();
// ...reap the decompiled code.
for (_, line) in &result {
let formatted_bytes = format_bytes(&line.bytes);
let output_line =format!("{:width$}; {}", line.text, formatted_bytes, width=30 );
// do we need a label
if let Some(label) = &line.label {
println!("There is a label - {label}");
}
if opts.verbose > 0 {
println!("{}", output_line);
}
writeln!(output_file, "{}", output_line).expect("cant write output file. you picked the red snapper.");
}
println!("OPTS = {}", opts.verbose);
}
+2
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@@ -18,4 +18,6 @@ fn main() {
for (op, bytes) in instructions {
assert_eq!(Instruction::decode(bytes), Some(op));
}
// let instruction = Instruction::decode(&[0xea]);
// println!("NOP Decoded -> {:?}", instruction);
}
+5
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@@ -0,0 +1,5 @@
fn main() {
println!("Taxation is theft.");
println!("TODO:");
println!(" Load specified binary and parse it out to ASM");
}
-26
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@@ -1,26 +0,0 @@
use core::computers::kim1::Kim1;
fn main() {
println!("Taxation is theft.");
let mut kim = Kim1::new();
let mut num_ticks = 0;
kim.running = true;
while kim.running {
kim.tick();
num_ticks += 1;
if num_ticks == MOS6502_RESET_CYCLE_COUNT {
println!("Got our 11 ticks. time to hotwire this pc.");
kim.running = true;
kim.dump();
}
if num_ticks == 15 {
kim.running = false;
kim.dump();
}
}
}
-48
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@@ -1,48 +0,0 @@
use core::computers::ram_rom::backplane::RamRomComputer;
use core::periph::backplane::Backplane;
use std::fs;
fn main() {
println!("Taxation is Theft");
// let opts = CliOptions::parse();
let path = "/home/tmerritt/Projects/mos6502/resources/test/periph/at28c256/checksum.bin";
let bytes = match fs::read(path) {
Ok(bytes) => {
println!("Read {} bytes.", bytes.len());
bytes
},
Err(e) => {
eprintln!("FAIL to read rom.");
panic!("No rom no run.");
vec![]
}
};
let mut computer = RamRomComputer::new();
// Read byte from ROM 0x4000
println!("-- ");
computer.set_read_mode(true);
computer.set_address_bus(0x4020);
computer.tick();
println!("-- ");
// Data Bus contains value from ROM
let read_from_rom = computer.data_bus();
// Write byte to RAM 0x0000
computer.set_read_mode(false);
computer.set_address_bus(0x0001);
computer.tick();
println!("-- ");
// Read byte from RAM
computer.set_read_mode(true);
computer.set_address_bus(0x0001);
computer.tick();
println!("-- ");
let read_from_ram = computer.data_bus();
assert_eq!(read_from_rom, read_from_ram);
println!("Test passed. We read the same from ROM as we did from RAM - {} == {}", read_from_rom, read_from_ram);
}
+5 -34
View File
@@ -1,7 +1,5 @@
use std::fs;
use clap::Parser;
use core::computers::rom_only::RomOnlyComputer;
use core::periph::backplane::Backplane;
use core::computers::rom_only::backplane::Backplane;
#[derive(Parser)]
struct CliOptions {
@@ -13,35 +11,8 @@ struct CliOptions {
fn main() {
println!("Taxation is theft");
// let opts = CliOptions::parse();
let path = "/home/tmerritt/Projects/mos6502/resources/test/periph/at28c256/checksum.bin";
let bytes = match fs::read(path) {
Ok(bytes) => {
println!("Read {} bytes.", bytes.len());
bytes
},
Err(e) => {
eprintln!("FAIL to read rom.");
panic!("No rom no run.");
vec![]
}
};
let opts = CliOptions::parse();
let mut rom_only = RomOnlyComputer::program((&bytes[..]).to_vec());
rom_only.set_read_mode(true);
rom_only.set_address_bus(0x05);
rom_only.tick();
println!("COMPUTER: Read {:02x} from ROM", rom_only.data_bus()) ;
println!("COMPUTER: Read {:04x} from Address Bus", rom_only.address_bus());
println!("----");
rom_only.set_read_mode(true);
rom_only.set_address_bus(0x07);
rom_only.tick();
println!("COMPUTER: Read {:02x} from ROM", rom_only.data_bus()) ;
println!("COMPUTER: Read {:04x} from Address Bus", rom_only.address_bus());
println!("----");
}
let mut rom_only = Backplane::new();
rom_only.tick()
}
-1
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@@ -5,4 +5,3 @@ edition = "2024"
[dependencies]
log = "0.4"
rand = "0.9.0"
once_cell = "0.1"
-28
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@@ -1,28 +0,0 @@
pub mod new;
pub mod tick;
pub mod reset;
use std::fs;
use std::path::Path;
use crate::constants::constants_system::SIZE_1KB;
use crate::mos6502cpu::Mos6502Cpu;
use crate::periph::at28c256::At28C256;
use crate::periph::hm62256::Hm62256;
use crate::periph::kim1_keypad::Kim1Keypad;
use crate::periph::mos6522::mos6522::Mos6522;
use crate::periph::mos6530::mos6530::Mos6530;
/// Represents a KIM-1
///
///
pub struct Kim1 {
pub running: bool,
pub cpu: Mos6502Cpu,
rriot1: Mos6530,
rriot2: Mos6530,
ram: Hm62256,
pub(crate) keypad: Kim1Keypad,
address_bus: u16,
data_bus: u8,
cpu_read: bool
}
-31
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@@ -1,31 +0,0 @@
use crate::computers::kim1::Kim1;
use crate::periph::hm62256::Hm62256;
use crate::periph::kim1_keypad::Kim1Keypad;
use crate::periph::mos6530::mos6530::Mos6530;
impl Kim1 {
pub fn dump(&self) {
println!("DUMPING KIM-1 PC STATE");
self.cpu.dump();
self.rriot1.dump();
self.rriot2.dump();
self.keypad.dump();
}
pub fn new() -> Self {
let rriot1_rom = include_bytes!("/home/tmerritt/Projects/mos6502/resources/kim1/6530-002_fillerbyte00-0x1c00.bin");
let rriot2_rom = include_bytes!("/home/tmerritt/Projects/mos6502/resources/kim1/6530-003_fillerbyte00-0x1800.bin");
Self {
cpu: Default::default(),
rriot1: Mos6530::new(0x1700, 0x1780, 0x1800, &rriot1_rom),
rriot2: Mos6530::new(0x1740, 0x17C0, 0x1C00, &rriot2_rom),
ram: Hm62256::new(0x0000),
keypad: Kim1Keypad::new(),
address_bus: 0,
data_bus: 0,
cpu_read: false,
running: false
}
}
}
-18
View File
@@ -1,18 +0,0 @@
use crate::computers::kim1::Kim1;
use crate::periph::hm62256::Hm62256;
use crate::periph::mos6530::mos6530::Mos6530;
impl Kim1 {
pub fn reset(&mut self) {
let rriot1_rom = include_bytes!("/home/tmerritt/Projects/mos6502/resources/kim1/6530-002_fillerbyte00-0x1c00.bin");
let rriot2_rom = include_bytes!("/home/tmerritt/Projects/mos6502/resources/kim1/6530-003_fillerbyte00-0x1800.bin");
self.cpu = Default::default();
self.rriot1 = Mos6530::new(0x1700, 0x1780, 0x1800, rriot1_rom.as_array().unwrap());
self.rriot2 = Mos6530::new(0x1740, 0x17c0, 0x1c00, rriot2_rom.as_array().unwrap());
self.ram = Hm62256::new(0x0000);
self.address_bus = 0x0000;
self.data_bus = 0x0000;
self.cpu_read = true;
self.cpu.pc = 0x0000;
}
}
-26
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@@ -1,26 +0,0 @@
use crate::computers::kim1::Kim1;
impl Kim1 {
pub fn tick(&mut self) {
println!("<- START KIM-1 Backplane Tick");
let (address_bus, data, rw) = self.cpu.tick2(self.address_bus, self.data_bus);
self.address_bus = address_bus;
self.data_bus = data;
self.cpu_read = rw;
// now tick the various items connected
self.rriot1.tick(self.address_bus, self.data_bus, false, self.cpu_read);
self.rriot2.tick(self.address_bus, self.data_bus, false, self.cpu_read);
self.ram.tick(self.address_bus, self.data_bus, self.cpu_read, true);
let (rr1_io, rr1_ram, rr1_rom) = self.rriot1.dump_data();
let (rr2_io, rr2_ram, rr2_rom) = self.rriot2.dump_data();
println!(" 0x0000 -> RAM / {}", self.ram.dump_data());
println!(" 0x1700 -> RRIOT 1 / 0x{rr1_io:04x}/0x{rr1_ram:04x}/0x{rr1_rom:04x}");
println!(" 0x1740 -> RRIOT 2 / 0x{rr2_io:04x}/0x{rr2_ram:04x}/0x{rr2_rom:04x}");
// display the memory map and device states
println!("-> FINISH KIM-1 Backplane Tick");
}
}
-2
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@@ -1,4 +1,2 @@
pub mod beneater;
pub mod rom_only;
pub mod kim1;
pub mod ram_rom;
-75
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@@ -1,75 +0,0 @@
use crate::periph::at28c256::At28C256;
use crate::periph::backplane::Backplane;
use crate::periph::hm62256::Hm62256;
pub struct RamRomComputer {
rom: At28C256,
ram: Hm62256,
data_bus: u8,
address_bus: u16,
read_mode: bool,
}
impl Backplane for RamRomComputer {
fn data_bus(&self) -> u8 {
self.data_bus
}
fn address_bus(&self) -> u16 {
self.address_bus
}
fn read_mode(&self) -> bool {
self.read_mode
}
fn tick(&mut self) {
println!("Preparing to tick the backplane. - ${:04x} ${:02x} {}", self.address_bus, self.data_bus, self.read_mode);
// who are we talking to?
match self.address_bus {
0x0000..=0x3fff => {
// RAM
println!("ADDRESSING RAM");
let (ram_address_bus, ram_data_bus) = self.ram.tick(self.address_bus, self.data_bus, self.read_mode, true);
if self.read_mode {
self.data_bus = ram_data_bus;
}
},
0x4000..=0x7fff => {
// ROM
println!("ADDRESSING ROM");
let (rom_address_bus, rom_data_bus) = self.rom.tick(self.address_bus, self.data_bus, self.read_mode);
self.data_bus = rom_data_bus;
}
_ => {
// Out of range
}
}
}
fn set_read_mode(&mut self, new_mode: bool) {
self.read_mode = new_mode;
}
fn set_address_bus(&mut self, new_value: u16) {
self.address_bus = new_value;
}
fn set_data_bus(&mut self, new_value: u8) {
self.data_bus = new_value;
}
}
impl RamRomComputer {
pub fn new() -> RamRomComputer {
let rom = At28C256::new(0x4000, 0x7fff, (0..255).collect());
RamRomComputer {
rom,
ram: Hm62256::default(),
data_bus: 0x00,
address_bus: 0x0000,
/// is the CPU reading from the 'other' device?
read_mode: true
}
}
}
-1
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@@ -1 +0,0 @@
pub mod backplane;
+25 -25
View File
@@ -1,29 +1,29 @@
use crate::computers::rom_only::RomOnlyComputer;
use crate::periph::backplane::Backplane;
use crate::constants::constants_system::{SIZE_32KB, SIZE_64KB};
use crate::periph::hm62256::Hm62256;
use crate::periph::rom_chip::RomChip;
impl Backplane for RomOnlyComputer {
fn data_bus(&self) -> u8 { self.data_bus }
fn address_bus(&self) -> u16 { self.address_bus }
fn read_mode(&self) -> bool { self.read_mode }
fn set_read_mode(&mut self, new_mode: bool) {
self.read_mode = new_mode
}
fn set_data_bus(&mut self, new_value: u8) {
self.data_bus = new_value
}
fn set_address_bus(&mut self, new_value: u16) {
self.address_bus = new_value
}
pub struct Backplane {
rom: Hm62256,
data_bus: u8,
address_bus: u16
}
fn tick(&mut self) {
println!("COMPUTER: Preparing to tick.");
// do are we being addressed?
println!("COMPUTER: BUSSES PRE: 0x{:04x} 0x{:02x} {}", self.address_bus, self.data_bus, self.read_mode);
let (new_addr, new_data) = self.rom.tick(self.address_bus, self.data_bus, self.read_mode);
self.set_address_bus(new_addr);
self.set_data_bus(new_data);
println!("COMPUTER: BUSSES POST: 0x{:04x} 0x{:02x} {}", self.address_bus, self.data_bus, self.read_mode);
println!("COMPUTER: Done ticking.");
impl Backplane {
pub fn new() -> Backplane {
Backplane::program(&[0x00; SIZE_32KB])
}
pub fn program(rom: &[u8; SIZE_32KB]) -> Backplane {
Backplane {
rom: *Hm62256::program(rom),
address_bus: 0x0000,
data_bus: 0x00
}
}
pub fn tick(&mut self) {
println!("Preparing to tick.");
println!("Done ticking.");
}
}
@@ -1,13 +0,0 @@
use crate::computers::rom_only::RomOnlyComputer;
impl RomOnlyComputer {
pub fn debug_memory(&self, start_offset: u16, end_offset: u16) -> Vec<u8> {
let mut data = vec![];
let size = end_offset - start_offset;
for index in 0..size {
println!("Index {index} for {}", index + start_offset);
}
data
}
}
-13
View File
@@ -1,14 +1 @@
use crate::periph::at28c256::At28C256;
pub mod backplane;
pub mod new;
pub mod program;
pub mod debug_memory;
mod rom_chunks;
pub struct RomOnlyComputer {
pub(crate) rom: At28C256,
pub(crate) data_bus: u8,
pub(crate) address_bus: u16,
pub(crate) read_mode: bool,
}
-13
View File
@@ -1,13 +0,0 @@
use crate::computers::rom_only::RomOnlyComputer;
use crate::constants::constants_system::SIZE_32KB;
impl RomOnlyComputer {
pub fn new() -> RomOnlyComputer {
let mut working = vec![0x00u8; SIZE_32KB];
for index in 0..SIZE_32KB {
working[index] = index as u8;
}
RomOnlyComputer::program(working)
}
}
-14
View File
@@ -1,14 +0,0 @@
use crate::computers::rom_only::RomOnlyComputer;
use crate::constants::constants_system::SIZE_32KB;
use crate::periph::at28c256::At28C256;
impl RomOnlyComputer {
pub fn program(rom: Vec<u8>) -> RomOnlyComputer {
RomOnlyComputer {
rom: At28C256::new(0x000, 0x3fff, rom),
address_bus: 0x0000,
data_bus: 0x00,
read_mode: true,
}
}
}
@@ -1,8 +0,0 @@
use std::slice::Chunks;
use crate::computers::rom_only::RomOnlyComputer;
impl RomOnlyComputer {
pub fn rom_chunks(&self, size: usize) -> Chunks<u8> {
self.rom.chunks(size)
}
}
-23
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@@ -1,23 +0,0 @@
pub const MOS6530_DRA: u8 = 0x00;
pub const MOS6530_DDRA: u8 = 0x01;
pub const MOS6530_DRB: u8 = 0x02;
pub const MOS6530_DDRB: u8 = 0x03;
/*
0 X Data Register A
1 X Data Direction Register A
2 X Data Register B
3 X Data Direction Register B
4 0 Count down from value, divide by 1, disable IRQ 1 ???
5 0 Count down from value, divide by 8, disable IRQ 1 ???
6 0 Count down from value, divide by 64, disable IRQ 1 Read current counter value, disable IRQ
7 0 Count down from value, divide by 1024, disable IRQ 1 Read counter status, bit7 = 1 means counter past zero
8 X Data Register A (mirror ?)
9 X Data Direction Register A (mirror ?)
A X Data Register B (mirror ?)
B X Data Direction Register B (mirror ?)
C 0 Count down from value, divide by 1, enable IRQ 1 ???
D 0 Count down from value, divide by 8, enable IRQ 1 ???
E 0 Count down from value, divide by 64, enable IRQ 1 Read current counter value, enable IRQ
F 0 Count down from value, divide by 1024, enable IRQ 1 Read counter status, bit7 = 1 means counter past zero
*/
-9
View File
@@ -2,15 +2,6 @@ pub const SIZE_1KB: usize = 1024;
pub const SIZE_32KB: usize = SIZE_1KB * 32;
pub const SIZE_64KB: usize = SIZE_1KB * 64;
// S Suffixed constants are for indexing slices
pub const OFFSET_NMI_VECTOR: u16 = 0xfffa;
pub const OFFSET_NMI_VECTORS: usize = 0xfffa;
pub const OFFSET_RESET_VECTOR: u16 = 0xfffc;
pub const OFFSET_RESET_VECTORS: usize = 0xffff;
pub const OFFSET_INT_VECTOR: u16 = 0xfffe;
pub const OFFSET_INT_VECTORS: usize = 0xfffe;
// 7 cycles for internal reset
// 6 to read the vectors from RAM
pub const MOS6502_RESET_CYCLE_COUNT: u16 = 8;
-7
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@@ -1,7 +0,0 @@
use std::borrow::ToOwned;
use once_cell::unsync::Lazy;
pub const TEST_RESOURCES_ROOT: &str = "/home/tmerritt/Projects/resources/test";
pub const TEST_PERIPH_ROOT: &str = "/home/tmerritt/Projects/resources/test/periph";
pub const TEST_PERIPH_AT28C256_ROOT: &str = "/home/tmerritt/Projects/mos6502/resources/test/periph/at28c256";
-2
View File
@@ -2,5 +2,3 @@ pub mod constants_isa_op;
pub mod constants_isa_stub;
pub mod constants_system;
pub mod constants_via6522;
pub mod constants_mos6530;
pub mod constants_test;
+9 -9
View File
@@ -19,7 +19,7 @@ impl Instruction {
pub fn opinfo(bytes: &[u8]) -> Option<OpInfo> {
trace!("DECODING : {bytes:?}");
let opcode = bytes.get(0).copied()?;
Some(INSTRUCTION_TABLE[opcode as usize].clone())?
Some(INSTRUCTION_TABLE[opcode as usize])?
}
pub fn decode(bytes: &[u8]) -> Option<Instruction> {
@@ -245,7 +245,7 @@ mod test {
vec![0x10, 0xab],
Instruction {
op: BPL,
mode: Immediate,
mode: Implied,
operand: Operand::Byte(0xab),
},
),
@@ -253,7 +253,7 @@ mod test {
vec![0x30, 0xab],
Instruction {
op: BMI,
mode: Immediate,
mode: Implied,
operand: Operand::Byte(0xab),
},
),
@@ -261,7 +261,7 @@ mod test {
vec![0x50, 0xab],
Instruction {
op: BVC,
mode: Immediate,
mode: Implied,
operand: Operand::Byte(0xab),
},
),
@@ -269,7 +269,7 @@ mod test {
vec![0x70, 0xab],
Instruction {
op: BVS,
mode: Immediate,
mode: Implied,
operand: Operand::Byte(0xab),
},
),
@@ -277,7 +277,7 @@ mod test {
vec![0x90, 0xab],
Instruction {
op: BCC,
mode: Immediate,
mode: Implied,
operand: Operand::Byte(0xab),
},
),
@@ -285,7 +285,7 @@ mod test {
vec![0xb0, 0xab],
Instruction {
op: BCS,
mode: Immediate,
mode: Implied,
operand: Operand::Byte(0xab),
},
),
@@ -293,7 +293,7 @@ mod test {
vec![0xd0, 0xab],
Instruction {
op: BNE,
mode: Immediate,
mode: Implied,
operand: Operand::Byte(0xab),
},
),
@@ -301,7 +301,7 @@ mod test {
vec![0xf0, 0xab],
Instruction {
op: BEQ,
mode: Immediate,
mode: Implied,
operand: Operand::Byte(0xab),
},
),
File diff suppressed because it is too large Load Diff
-3
View File
@@ -1,5 +1,3 @@
#![feature(slice_as_array)]
pub mod computers;
pub mod address_mode;
pub mod constants;
@@ -11,4 +9,3 @@ pub mod op_info;
pub mod operand;
pub mod operation;
pub mod periph;
pub mod traits;
-20
View File
@@ -1,20 +0,0 @@
use crate::mos6502cpu::Mos6502Cpu;
use crate::traits::bus_device::BusDevice;
impl BusDevice for Mos6502Cpu {
fn address_bus(&self) -> u16 {
self.address_bus
}
fn data_bus(&self) -> u8 {
self.data_bus
}
fn set_address_bus(&mut self, new_value: u16) {
self.address_bus = new_value;
}
fn set_data_bus(&mut self, new_value: u8) {
self.data_bus = new_value;
}
}
+110 -77
View File
@@ -9,17 +9,87 @@ use crate::op_info::OpInfo;
use crate::operand::Operand;
use crate::operation::Operation;
use log::trace;
use crate::mos6502cpu::Mos6502Cpu;
use crate::mos6502cpu::tick_stages::Mos6502TickStates;
use crate::mos6502cpu::tick_stages::Mos6502TickStates::*;
enum Mos6502Registers {
A,
X,
Y
pub struct Mos6502Cpu {
pub(crate) memory: [u8; SIZE_64KB],
/// accumulator
pub(crate) a: u8,
/// x register
pub(crate) x: u8,
/// y register
pub(crate) y: u8,
/// cpu flags
pub(crate) flags: Mos6502Flags,
/// program counter
pub pc: u16,
/// stack offset
pub(crate) s: u8,
pub microcode_step: u8,
pub(crate) address_bus: u16,
pub(crate) data_bus: u8,
pub(crate) ir: Instruction, // Instruction Register
pub(crate) oi: OpInfo,
pub(crate) has_reset: bool,
pub(crate) iv: u16, // Interrupt Vector
pub(crate) cycle_carry: u16, // Value to hold between microsteps
pub(crate) ir_bytes: [u8; 4],
/// CPU Read signal
pub read_signal: bool,
pub(crate) reset_vector: u16,
pub(crate) int_vector: u16
}
impl Mos6502Cpu {
/// set_data_bus
///
/// Sets data on the data bus.
/// Used when CPU is in "R" mode
pub fn set_data_bus(&mut self, to_set: u8) {
self.data_bus = to_set;
}
}
impl Default for Mos6502Cpu {
fn default() -> Self {
let mut working = Mos6502Cpu {
memory: [0x00; SIZE_64KB],
a: 0x00,
x: 0x00,
y: 0x00,
flags: Default::default(),
pc: 0xfffd,
s: 0x00,
microcode_step: 0x00,
address_bus: 0x00,
data_bus: 0x00,
ir: Instruction {
op: Operation::NOP,
mode: AddressMode::Implied,
operand: Operand::None,
},
oi: INSTRUCTION_TABLE[ISA_OP_NOP as usize].unwrap(),
has_reset: false,
iv: 0xfffe,
cycle_carry: 0x0000,
ir_bytes: [0x00; 4],
read_signal: true,
reset_vector: 0x0000,
int_vector: 0x0000
};
working.reset_cpu();
working
}
}
impl Mos6502Cpu {
pub fn address_bus(&self) -> u16 {
self.address_bus
}
pub fn data_bus(&self) -> u8 {
self.data_bus
}
//
// fn read_word(&self, offset: &u16) -> u16 {
// println!("READING OFFSET 0x{offset:04x} and 0x{:04x}", offset + 1);
@@ -32,22 +102,6 @@ impl Mos6502Cpu {
// result
// }
pub fn peek_register(&self, register_to_peek: Mos6502Registers) -> u8 {
match register_to_peek {
Mos6502Registers::A => self.a,
Mos6502Registers::X => self.x,
Mos6502Registers::Y => self.y
}
}
pub fn poke_register(&mut self, register_to_poke: Mos6502Registers, new_value: u8) {
match register_to_poke {
Mos6502Registers::A => self.a = new_value,
Mos6502Registers::X => self.x = new_value,
Mos6502Registers::Y => self.y = new_value
}
}
pub fn peek_flag(&self, flag_to_read: Mos6502Flag) -> bool {
self.flags.flag(flag_to_read)
}
@@ -59,15 +113,42 @@ impl Mos6502Cpu {
}
}
pub fn peek_memory(&self, offset: u16) -> u8 {
pub fn peek(&self, offset: u16) -> u8 {
self.memory[offset as usize]
}
pub fn poke_memory(&mut self, offset: u16, value: u8) {
pub fn poke(&mut self, offset: u16, value: u8) {
println!("Setting memory at {offset:04x} to {value:02x}");
self.memory[offset as usize] = value
}
pub fn peek_a(&self) -> u8 {
println!("Readding register A => 0x{:02x}", self.a);
self.a
}
pub fn poke_a(&mut self, new_a: u8) {
println!("Updating register A from [{}] to [{}]", self.a, new_a);
self.a = new_a;
}
pub fn peek_x(&self) -> u8 {
println!("Readding register X => 0x{}", self.x);
self.x
}
pub fn poke_x(&mut self, new_x: u8) {
println!("Updating register X from [{}] to [{}]", self.x, new_x);
self.x = new_x
}
pub fn peek_y(&self) -> u8 {
self.y
}
pub fn poke_y(&mut self, new_y: u8) {
self.y = new_y
}
fn advance_pc(&mut self, how_far: u16) {
self.pc += how_far;
}
@@ -79,47 +160,6 @@ impl Mos6502Cpu {
/// Ticks the CPU
pub fn tick(&mut self) {
println!("PREPARiNG TO TICK CPU AT PC 0x{:04x}", self.pc);
match self.tick_stage {
LoadingInstruction => {
println!("Loading instruction from data bus -> {}", self.data_bus);
let instruction = INSTRUCTION_TABLE[self.data_bus as usize].clone();
if let Some(inst) = instruction {
println!("DECODED INSTRUCTION [{:?}]/[{:?}]", inst.operation, inst.mode);
match inst.mode {
AddressMode::Absolute | AddressMode::AbsoluteX | AddressMode::AbsoluteY => {
println!("NEED TO LOAD a 16bit VALUE FOR INSTRUCTION");
self.tick_stage = Loading16BitParameter1;
}
AddressMode::Immediate => {
println!("LOADING A 8BIT VALUE FOR INSTRUCTION");
self.tick_stage = Loading8BitParameter;
}
_ => {}
}
} else {
println!("INVALID DECODE OF [${:02x}", self.data_bus);
}
}
Loading8BitParameter => {
println!("Loading parameter for 8bit ");
},
Loading16BitParameter1 => {
println!("Loading high bits of parameter");
},
Loading16BitParameter2 => {
println!("Loading low bits of parameter");
},
Stall(length) => {
println!("PREPARING TO STALL FOR {} CYCLES", length);
},
Waiting => {
println!("CPU IS WAITING.");
}
}
if self.microcode_step == 0 {
println!("OUT OF MICROSTEPS. Decoding the next instruction");
let offset = self.pc as usize;
@@ -233,7 +273,7 @@ impl Mos6502Cpu {
Operation::DEX => {
if self.microcode_step == 1 {
let (new_x, new_carry) = self.x.overflowing_sub(1);
self.poke_register(Mos6502Registers::X, new_x);
self.poke_x(new_x);
self.poke_flag(Carry, new_carry);
}
}
@@ -247,7 +287,7 @@ impl Mos6502Cpu {
Operation::INX => {
if self.microcode_step == 1 {
let (new_x, new_carry) = self.x.overflowing_add(1);
self.poke_register(Mos6502Registers::X, new_x);
self.poke_x(new_x);
self.poke_flag(Carry, new_carry);
self.address_bus = self.pc;
self.data_bus = 0x00;
@@ -256,7 +296,7 @@ impl Mos6502Cpu {
Operation::INY => {
if self.microcode_step == 1 {
let (new_y, new_carry) = self.y.overflowing_add(1);
self.poke_register(Mos6502Registers::Y, new_y);
self.poke_y(new_y);
self.poke_flag(Carry, new_carry);
self.address_bus = self.pc;
self.data_bus = 0x00;
@@ -438,7 +478,7 @@ impl Mos6502Cpu {
}
}
}
/*
#[cfg(test)]
mod test {
use super::*;
@@ -449,12 +489,6 @@ mod test {
fn clc() {
// setup the CPU for our test
let mut cpu = Mos6502Cpu::default();
// tick through the reset cycle
while !cpu.has_reset {
cpu.tick();
}
println!("DONE RESET TICKS");
cpu.flags.set_flag(Carry);
// Load our 'test program'
cpu.memory[0x6000] = ISA_OP_CLC;
@@ -681,4 +715,3 @@ mod test {
assert_eq!(cpu.memory[0xab], 0b1010_1010);;
}
}
*/
+5 -9
View File
@@ -1,11 +1,11 @@
use crate::mos6502cpu::Mos6502Cpu;
use crate::mos6502cpu::cpu::Mos6502Cpu;
impl Mos6502Cpu {
/// dump_data
///
/// returns
/// PC, A, X, Y, Address_Bus, Data_Bus, Microcode_Step
pub fn dump_data(&self) -> (u16, u8, u8, u8, u16, u8, u8, u16, u16, u16) {
pub fn dump_data(&self) -> (u16, u8, u8, u8, u16, u8, u8, u16, u16) {
(
self.pc,
self.a,
@@ -15,14 +15,13 @@ impl Mos6502Cpu {
self.data_bus,
self.microcode_step,
self.reset_vector,
self.int_vector,
self.nmi_vector
self.int_vector
)
}
pub fn dump(&self) {
println!(
"CPU State: PC: ${:04x} / A: ${:02x} / X: ${:02x} / Y: ${:02x} / ADDRESS: ${:04x} / DATA: ${:02x} / MICROSTEPS: {:02} / S: {} / NMI: ${:04x} / RST: ${:04x} / INT: ${:04x}",
"CPU State: PC: {:04x} / A: {:02x} / X: {:02x} / Y: {:02x} / ADDRESS: {:04x} / DATA: {:02x} / MICROSTEPS: {:02x} / S: {}",
self.pc,
self.a,
self.x,
@@ -30,10 +29,7 @@ impl Mos6502Cpu {
self.address_bus,
self.data_bus,
self.microcode_step,
self.flags.dump(),
self.nmi_vector,
self.reset_vector,
self.int_vector
self.flags.dump()
);
}
}
-43
View File
@@ -1,43 +0,0 @@
use crate::address_mode::AddressMode;
use crate::constants::constants_isa_op::ISA_OP_NOP;
use crate::constants::constants_system::SIZE_64KB;
use crate::instruction::Instruction;
use crate::instruction_table::INSTRUCTION_TABLE;
use crate::mos6502cpu::Mos6502Cpu;
use crate::mos6502cpu::tick_stages::Mos6502TickStates::LoadingInstruction;
use crate::operand::Operand;
use crate::operation::Operation;
impl Default for Mos6502Cpu {
fn default() -> Self {
let mut working = Mos6502Cpu {
memory: [0x00; SIZE_64KB],
a: 0x00,
x: 0x00,
y: 0x00,
flags: Default::default(),
pc: 0xfffd,
s: 0x00,
microcode_step: 0x00,
address_bus: 0x00,
data_bus: 0x00,
ir: Instruction {
op: Operation::NOP,
mode: AddressMode::Implied,
operand: Operand::None,
},
oi: INSTRUCTION_TABLE[ISA_OP_NOP as usize].clone().unwrap(),
has_reset: false,
iv: 0xfffe,
cycle_carry: 0x0000,
ir_bytes: [0x00; 4],
read_signal: true,
reset_vector: 0x0000,
int_vector: 0x0000,
nmi_vector: 0x0000,
tick_stage: LoadingInstruction
};
working.reset_cpu();
working
}
}
+3 -41
View File
@@ -1,44 +1,6 @@
use crate::constants::constants_system::SIZE_64KB;
use crate::instruction::Instruction;
use crate::mos6502cpu::tick_stages::Mos6502TickStates;
use crate::mos6502flags::Mos6502Flags;
use crate::op_info::OpInfo;
pub mod cpu;
pub mod new;
pub mod tick2;
pub mod dbg;
pub mod tick_stages;
pub mod default;
pub mod bus_device;
pub struct Mos6502Cpu {
pub(crate) memory: [u8; SIZE_64KB],
/// accumulator
pub(crate) a: u8,
/// x register
pub(crate) x: u8,
/// y register
pub(crate) y: u8,
/// cpu flags
pub(crate) flags: Mos6502Flags,
/// program counter
pub pc: u16,
/// stack offset
pub(crate) s: u8,
pub microcode_step: u8,
pub(crate) address_bus: u16,
pub(crate) data_bus: u8,
pub(crate) ir: Instruction, // Instruction Register
pub(crate) oi: OpInfo,
pub(crate) has_reset: bool,
pub(crate) iv: u16, // Interrupt Vector
pub(crate) cycle_carry: u16, // Value to hold between microsteps
pub(crate) ir_bytes: [u8; 4],
/// CPU Read signal
pub read_signal: bool,
pub(crate) reset_vector: u16,
pub(crate) int_vector: u16,
pub(crate) nmi_vector: u16,
pub tick_stage: Mos6502TickStates
}
pub mod tick2;
mod dbg;
mod tick_stages;
+7 -5
View File
@@ -1,5 +1,5 @@
use crate::constants::constants_system::{MOS6502_RESET_CYCLE_COUNT, OFFSET_RESET_VECTOR, SIZE_64KB};
use crate::mos6502cpu::Mos6502Cpu;
use crate::constants::constants_system::{OFFSET_RESET_VECTOR, SIZE_64KB};
use crate::mos6502cpu::cpu::Mos6502Cpu;
impl Mos6502Cpu {
pub fn new() -> Mos6502Cpu {
@@ -13,12 +13,14 @@ impl Mos6502Cpu {
working
}
pub(crate) fn reset_cpu(&mut self) {
self.microcode_step = MOS6502_RESET_CYCLE_COUNT as u8;
self.microcode_step = 7 + 4;
// self = &mut Mos6502Cpu::default();
println!("Should tick 7 times, then 6 cycles to read the reset and int vectors.");
// read the value at 0xfffa 0xfffb for our NMI vector.
println!("Should tick 7 times, then 4 cycles to read the reset and int vectors.");
// read the value at 0xfffc 0xfffd for our reset vector.
// read the value at 0xfffe 0xffff for our int vector
}
}
+44 -72
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@@ -1,69 +1,7 @@
use crate::constants::constants_system::{OFFSET_INT_VECTOR, OFFSET_RESET_VECTOR};
use crate::mos6502cpu::Mos6502Cpu;
enum Mos6502ResetSteps {
/// there are 6 of these
DummyRead(u8),
ReadRstVectorLow,
ReadRstVectorHigh,
ReadPcLow,
ReadPcHigh
}
use crate::mos6502cpu::cpu::Mos6502Cpu;
impl Mos6502Cpu {
fn reset_step(&mut self, address_bus: u16, data_bus: u8, read: bool) -> (u16, u8, bool) {
println!("Reset microstep {}", self.microcode_step);
// we need to do the reset steps
// reduce the number of remaining microsteps
self.read_signal = true;
match self.microcode_step {
6 => {
// NMI High byte
}
5 => {
// NMI low byte
}
4 => {
// read first byte of reset vector
self.address_bus = OFFSET_RESET_VECTOR;
}
3 => {
// at this point data holds the upper byte of our reset vector
self.reset_vector = (data_bus as u16) << 8;
println!("Loaded reset vector of 0x{:04x}", self.reset_vector);
// read secondd byte of reset vector
self.address_bus = OFFSET_RESET_VECTOR + 1;
}
2 => {
self.reset_vector |= data_bus as u16;
println!("Loaded reset vector of 0x{:04x}", self.reset_vector);
// read first byte of interrupt vector
self.address_bus = OFFSET_INT_VECTOR;
}
1 => {
// read second byte of interrupt vector
self.address_bus = OFFSET_INT_VECTOR + 1;
}
0 => {
self.int_vector |= data_bus as u16;
println!("Loaded interrupt vector of 0x{:04x}", self.int_vector);
self.pc = self.reset_vector;
println!("Set PC to Reset Vector. Giddy-up!");
println!("START HACK HACK HACK HACK HACK HACK HACK HACK HACK HACK");
// the KIM-1 uses 0x0000 for its initial PC
self.pc = 0x0000;
println!("END HACK HACK HACK HACK HACK HACK HACK HACK HACK HACK");
self.has_reset = true;
}
_ => {
}
}
if self.microcode_step > 0 {
self.microcode_step -= 1;
}
(address_bus, data_bus, read)
}
/// AccurateTick
///
/// In: address_bus > Address of data operationm
@@ -76,16 +14,50 @@ impl Mos6502Cpu {
/// read_bus > lets rest of the computer know if the CPU is reading from the address
/// provided or if we are writing to the address
pub fn tick2(&mut self, address_bus: u16, data_bus: u8) -> (u16, u8, bool) {
println!("STARTING TICK2");
if !self.has_reset { return self.reset_step(address_bus, data_bus, self.read_signal) }
// we have completed the reset cycle
if self.read_signal {
// we should see new data in the data_bus for us
let read_data = data_bus;
println!("READ 0x{read_data:02x} from data bus.");
self.data_bus = read_data;
if self.has_reset {
// we have completed the reset cycle
if self.read_signal {
// we should see new data in the data_bus for us
let read_data = data_bus;
} else {
// we are writing to the bus.
}
} else {
// we are writing to the bus.
println!("Reset microstep {}", self.microcode_step);
// we need to do the reset steps
// reduce the number of remaining microsteps
self.read_signal = true;
match self.microcode_step {
4 => {
// read first byte of reset vector
self.address_bus = OFFSET_RESET_VECTOR;
}
3 => {
// at this point data holds the upper byte of our reset vector
self.reset_vector = (data_bus as u16) << 8;
// read secondd byte of reset vector
self.address_bus = OFFSET_RESET_VECTOR + 1;
}
2 => {
self.reset_vector |= data_bus as u16;
println!("Loaded reset vector of 0x{:04x}", self.reset_vector);
// read first byte of interrupt vector
self.address_bus = OFFSET_INT_VECTOR;
}
1 => {
// read second byte of interrupt vector
self.address_bus = OFFSET_INT_VECTOR + 1;
}
0 => {
self.int_vector |= data_bus as u16;
println!("Loaded interrupt vector of 0x{:04x}", self.int_vector);
self.pc = self.reset_vector;
println!("Set PC to Reset Vector. Giddy-up!");
}
_ => {
}
}
self.microcode_step -= 1;
}
(self.address_bus, self.data_bus, self.read_signal)
}
+3 -3
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@@ -3,7 +3,7 @@
///
/// The set of what a tick can be doing
///
pub enum Mos6502TickStates {
enum Mos6502TickStates {
/// Loading the first byte into the IR
LoadingInstruction,
/// Loading an 8 bit parameter
@@ -14,6 +14,6 @@ pub enum Mos6502TickStates {
Loading16BitParameter2,
/// Stalling for accurate emulation
Stall(u8),
/// Waiting for the next instruction
Waiting
/// Completed the instruction
Complete
}
+2 -5
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@@ -1,7 +1,7 @@
use crate::address_mode::AddressMode;
use crate::operation::Operation;
#[derive(Debug, Clone)]
#[derive(Debug, Copy, Clone)]
pub struct OpInfo {
/// What is the operation
pub operation: Operation,
@@ -11,7 +11,4 @@ pub struct OpInfo {
pub length: u8,
/// CPU Cycles to complete the instruction
pub cycles: u8,
/// Format string for disassembly
pub format_prefix: &'static str,
pub format_postfix: &'static str
}
}
-37
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@@ -1,37 +0,0 @@
use std::slice::Chunks;
use crate::periph::at28c256::At28C256;
impl At28C256 {
pub fn chunks(&self, size: usize) -> Chunks<u8> {
self.data.chunks(size)
}
}
#[cfg(test)]
mod test {
use super::*;
#[test]
fn smoke() { assert!(true); }
#[test]
fn full_chunks_come_back_ok() {
let test_data = (0..255).collect();
let mut chip = At28C256::new(0x0000, 0x3fff, test_data);
let chunks = chip.chunks(16);
assert_eq!(chunks.len(), 16);
}
#[test]
fn partial_blocks_come_back_ok() {
let test_data = (0..=3).collect();
let mut chip = At28C256::new(0x0000, 0x3fff, test_data);
let chunks = chip.chunks(16);
assert_eq!(chunks.len(), 1);
for chunk in chunks {
assert_eq!(chunk.len(), 4);
}
}
}
-80
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@@ -1,80 +0,0 @@
use crate::constants::constants_system::SIZE_32KB;
use crate::periph::at28c256::At28C256;
use crate::constants::constants_test::*;
impl At28C256 {
/// checksum
///
/// calculates and returns the checksum for the loaded binary.
/// files with all zero will calculate to zero
pub fn checksum(&self) -> u8 {
At28C256::checksum_static(&self.data[..])
}
pub fn checksum_static(data: &[u8]) -> u8 {
data.iter().fold(0u8, |acc, &b| acc.wrapping_add(b))
}
}
#[cfg(test)]
mod test {
use std::fs;
use std::path::Path;
use crate::constants::constants_system::SIZE_1KB;
use crate::periph::rom_chip::RomChip;
use super::*;
#[test]
fn smoke() { assert!(true); }
#[test]
fn programmed_data_reads_back_same() {
let mut data = At28C256::default();
for i in 0..SIZE_32KB {
data.data[i] = 0xeau8;
}
for offset in 0..SIZE_32KB {
if offset.is_multiple_of(SIZE_1KB) {};
assert_eq!(0xea, data.read(&(offset as u16)));
}
}
#[test]
fn checksums_calculate_correctly_for_zero() {
let data1 = [0x00u8; SIZE_32KB];
assert_eq!(0x00, At28C256::checksum_static(&data1));
}
#[test]
fn checksums_calculate_for_1_byte() {
let data = [0xff; 1];
assert_eq!(0xff, At28C256::checksum_static(&data));
}
#[test]
fn checksums_calculate_for_2_bytes() {
let data = [0xff; 2];
// 0xff + 0xff = 0x1fe
assert_eq!(0xfe, At28C256::checksum_static(&data));
}
#[test]
fn checksums_calculate_for_first_80_bytes() {
println!("STARTING TEST");
let mut checksum = 0x00;
let path = format!("{}{}", TEST_PERIPH_AT28C256_ROOT, "/checksum.bin");
println!("READING [{path}]");
let data = fs::read(path);
match data {
Ok(bytes) => {
println!("Read {} bytes", bytes.len());
checksum = At28C256::checksum_static(&bytes);
println!("Checksum: 0x{:02x}", checksum);
}
Err(e) => eprintln!("Failed to read file: {}", e),
}
assert_eq!(0x58, checksum);
println!("TEST COMPLETE");
}
}
+1 -7
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@@ -9,13 +9,7 @@ impl Default for At28C256 {
let boxed_array: Box<[u8; SIZE_32KB]> = boxed_slice
.try_into()
.expect("Failed to convert Vec to boxed array");
At28C256 {
data: boxed_array,
address_bus: 0x0000,
data_bus: 0x00,
offset: 0x0000,
max_offset: 0x3fff,
}
At28C256 { data: boxed_array }
}
}
-15
View File
@@ -1,15 +0,0 @@
use crate::periph::at28c256::At28C256;
pub struct At28C256State {
offset: u16,
max_offset: u16
}
impl At28C256 {
pub fn dump(&self) -> At28C256State {
At28C256State {
offset: self.offset,
max_offset: self.max_offset
}
}
}
+27 -12
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@@ -1,11 +1,8 @@
pub mod default;
pub mod rom_chip;
pub mod tick;
pub mod new;
pub mod program;
pub mod dump;
pub mod checksum;
pub mod blocks;
mod new;
mod program;
use crate::constants::constants_system::SIZE_32KB;
use crate::periph::rom_chip::RomChip;
@@ -13,15 +10,33 @@ use std::io::Read;
/// At28C256
///
/// Represents a single At28C256 EEPROM Chip
/// Represents a single At28C256 Chip
///
/// 256kbit storage
/// 32kbyte storage
pub struct At28C256 {
data_bus: u8,
address_bus: u16,
data: Box<[u8]>,
// where in the computer memory map do we live?
offset: u16,
max_offset: u16
data: Box<[u8; SIZE_32KB]>,
}
#[cfg(test)]
mod test {
use super::*;
use crate::constants::constants_system::SIZE_1KB;
#[test]
fn smoke() {
assert!(true)
}
#[test]
fn programmed_data_reads_back_same() {
let mut data = At28C256::default();
for i in 0..SIZE_32KB {
data.data[i] = 0xea;
}
for offset in 0..SIZE_32KB {
if offset.is_multiple_of(SIZE_1KB) {};
assert_eq!(0xea, data.read(&(offset as u16)));
}
}
}
+2 -8
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@@ -2,15 +2,9 @@ use crate::constants::constants_system::SIZE_32KB;
use crate::periph::at28c256::At28C256;
impl At28C256 {
pub fn new(offset: u16, max_offset: u16, data: Vec<u8>) -> Self {
println!("NEW At28C256 with checksum ${:02x}", At28C256::checksum_static(&data[..]));
pub fn new(data: &[u8; SIZE_32KB]) -> Self {
At28C256 {
data: data.into_boxed_slice(),
address_bus: 0x0000,
data_bus: 0x00,
offset,
max_offset
data: (*data).into()
}
}
}
+2 -22
View File
@@ -2,29 +2,9 @@ use crate::constants::constants_system::SIZE_32KB;
use crate::periph::at28c256::At28C256;
impl At28C256 {
pub fn program(&mut self, new_program: Box<[u8]>) {
pub fn program(&mut self, new_program: &[u8; SIZE_32KB]) {
// panic!("FAIL. Cant program the chip.");
// println!("PROGRAMMING {:?}", new_program);
self.data = new_program;
}
}
#[cfg(test)]
mod test {
use crate::periph::rom_chip::RomChip;
use super::*;
#[test]
fn smoke() { assert!(true) }
#[test]
fn programming_chip_changes_contents() {
let mut chip = At28C256::new(0x0000, 0x3fff, vec![]);
assert_eq!(0x00, chip.read(&0x0000));
let new_data: Vec<u8> = vec![0xff, 0xff, 0xff, 0xff];
chip.program(new_data.into());
assert_eq!(0xff, chip.read(&0x0000));
self.data = Box::new(*new_program);
}
}
+1 -21
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@@ -3,30 +3,10 @@ use crate::periph::at28c256::At28C256;
use crate::periph::rom_chip::RomChip;
impl RomChip for At28C256 {
/// read
///
/// Reads a byte from memory.
/// Returns a 0x00 if there is no data at that location but is still in ROM address range
fn read(&self, offset: &u16) -> u8 {
println!("STARTING READ FROM At28C256 ${:04x} | ${:04x} | ${:04x}", self.offset, offset, self.max_offset);
if offset < &self.offset || offset > &self.max_offset {
println!("Unable to read from ${offset:04x} as it it out of range.");
return 0x00;
} else {
println!("OK READ FROM GOOD AREA total len = {}", self.data.len());
}
if *offset >= self.data.len() as u16 {
0x00
} else {
self.data[*offset as usize]
}
self.data[*offset as usize]
}
/// program
///
/// Writes new data to the memory chip
fn program(new_data: &[u8; SIZE_32KB]) -> Box<At28C256> {
println!("Writing new chip.");
let mut working = At28C256::default();
+11 -48
View File
@@ -1,70 +1,33 @@
use crate::constants::constants_system::SIZE_32KB;
use crate::periph::at28c256::At28C256;
use crate::periph::hm62256::Hm62256;
impl At28C256 {
fn talking_to_me(&self, address: u16) -> bool {
//println!("Checking on {address:04x} in range of {:04x} {:04x}", self.offset, self.max_offset);
address >= self.offset && address < self.max_offset
}
pub fn tick(&mut self, address_bus: u16, data_bus: u8, read_mode: bool) -> (u16, u8) {
print!("At28C256: Tick starting for A${address_bus:04x} D${data_bus:02x} R{read_mode}");
// we aren't being addressed
// OR
// we arent reading from the ROM...
if !self.talking_to_me(address_bus) ||
!read_mode {
// ...go away.
// println!("At28C256 Tick not for me.");
return (address_bus, data_bus)
}
// print!("At28C256 tick for me.");
let effective = address_bus - self.offset;
if effective < self.max_offset {
if effective < self.data.len() as u16 {
self.data_bus = self.data[effective as usize];
} else {
self.data_bus = 0x00;
}
fn tick(&mut self, address_bus: u16, data_bus: u8, read_mode: bool) -> (u16, u8) {
if read_mode {
panic!("UNABLE TO WRITE TO ROM");
} else {
println!("At28C256: OUTSIDE RANGE. :(");
// has to be read mode. its a rom.
return (address_bus, data_bus)
}
// print!("At28C256: Read... {:02x}", self.data_bus);
(address_bus, self.data_bus)
(address_bus, self.data[address_bus as usize])
}
}
#[cfg(test)]
mod test {
use std::fs;
use crate::periph::rom_chip::RomChip;
use super::*;
#[test]
fn smoke() { assert!(true); }
#[test]
fn checksum_binary_loads() {
let path = "/home/tmerritt/Projects/mos6502/resources/test/periph/at28c256/checksum.bin";
let bytes = match fs::read(path) {
Ok(bytes) => {
println!("Read {} bytes.", bytes.len());
bytes
},
Err(e) => {
eprintln!("FAIL to read rom.");
panic!("No rom no run.");
vec![]
}
};
fn write_to_memory_read_back_works_at_0() {
let mut rom = At28C256::default();
let mut rom = At28C256::new(0x0000, 0x3fff, bytes);
rom.tick(0x0000, 0xab, false);
let (_, new_data) = rom.tick(0x0000, 0x00, true);
assert_eq!(rom.checksum(), 0x58);
assert_eq!(new_data, 0xab);
}
}
-10
View File
@@ -1,10 +0,0 @@
pub trait Backplane {
fn data_bus(&self) -> u8;
fn address_bus(&self) -> u16;
fn read_mode(&self) -> bool;
fn set_read_mode(&mut self, new_mode: bool);
fn set_data_bus(&mut self, new_value: u8);
fn set_address_bus(&mut self, new_value: u16);
fn tick(&mut self);
}
-3
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@@ -1,3 +0,0 @@
pub trait BusDevice {
fn talking_to_me(&self, address: u16) -> bool;
}
-17
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@@ -1,17 +0,0 @@
use crate::constants::constants_system::SIZE_32KB;
use crate::periph::hm62256::Hm62256;
impl Default for Hm62256 {
fn default() -> Self {
let vec = vec![0x00; SIZE_32KB];
let boxed_slice: Box<[u8]> = vec.into_boxed_slice();
let boxed_array: Box<[u8; SIZE_32KB]> =
boxed_slice.try_into().expect("Unable to box the ram");
Hm62256 {
offset: 0x0000,
data: boxed_array,
address_bus: 0x0000,
data_bus: 0x00
}
}
}
-17
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@@ -1,17 +0,0 @@
use crate::periph::hm62256::Hm62256;
pub struct Hm62256State {
pub offset: u16
}
impl Hm62256 {
pub fn dump(&self) -> Hm62256State {
Hm62256State {
offset: self.offset
}
}
pub fn dump_data(&self) -> (u16) {
self.offset
}
}
+14 -10
View File
@@ -3,23 +3,27 @@
pub mod ramchip;
pub mod romchip;
pub mod tick;
pub mod default;
pub mod new;
pub mod dump;
use crate::constants::constants_system::SIZE_32KB;
use crate::periph::ram_chip::RamChip;
use crate::periph::rom_chip::RomChip;
use log::debug;
/// Hitachi Semiconductor
/// 8 Bit High Speed Static Ram
/// 32KByte
pub struct Hm62256 {
pub(crate) offset: u16,
pub(crate) base_offset: u16,
pub(crate) data: Box<[u8]>,
pub(crate) address_bus: u16,
pub(crate) data_bus: u8
}
impl Default for Hm62256 {
fn default() -> Self {
let vec = vec![0x00; SIZE_32KB];
let boxed_slice: Box<[u8]> = vec.into_boxed_slice();
let boxed_array: Box<[u8; SIZE_32KB]> =
boxed_slice.try_into().expect("Unable to box the ram");
Hm62256 {
base_offset: 0x0000,
data: boxed_array,
}
}
}
#[cfg(test)]
-13
View File
@@ -1,13 +0,0 @@
use crate::constants::constants_system::SIZE_32KB;
use crate::periph::hm62256::Hm62256;
impl Hm62256 {
pub fn new(base_offset: u16) -> Self {
Self {
offset: base_offset,
data: vec![0; SIZE_32KB].into_boxed_slice(),
address_bus: 0x0000,
data_bus: 0x00
}
}
}
+8 -34
View File
@@ -1,42 +1,16 @@
use crate::constants::constants_system::SIZE_32KB;
use crate::periph::hm62256::Hm62256;
impl Hm62256 {
fn max_address(&self) -> u16 {
self.offset + SIZE_32KB as u16
}
pub fn tick(&mut self, address_bus: u16, data_bus: u8, read_mode: bool, cs: bool) -> (u16, u8) {
println!("HM62256RAM TICK START -> 0x{address_bus:04x} 0x{data_bus:02x} {read_mode} {cs}");
if !(address_bus >= self.offset && address_bus < self.max_address()) {
return (address_bus, data_bus);
}
self.address_bus = address_bus;
self.data_bus = data_bus;
let addr = address_bus.wrapping_sub(self.offset) + self.offset;
// did we want to talk to the chip...
if !cs {
return (address_bus, data_bus);
}
// ...or are we outside the range?
if (addr - self.offset) > SIZE_32KB as u16 {
return (address_bus, data_bus);
}
// ok. lets see what we are dealing with
self.data_bus = if read_mode {
let new_value = self.data[addr as usize];
new_value
fn tick(&mut self, address_bus: u16, data_bus: u8, read_mode: bool) -> (u16, u8) {
let new_data_bus = if read_mode {
// reading from ram
self.data[address_bus as usize]
} else {
// writing to ram
self.data[addr as usize] = data_bus.into();
self.data[address_bus as usize] = data_bus.into();
data_bus
};
(self.address_bus, self.data_bus)
(address_bus, new_data_bus)
}
}
@@ -52,9 +26,9 @@ mod test {
let mut ram = Hm62256::default();
// load the data to ram
ram.tick(0x0000, 0xab, false, true);
ram.tick(0x0000, 0xab, false);
// read the data back
let (_, new_data) = ram.tick(0x0000, 0x00, true, true);
let (_, new_data) = ram.tick(0x0000, 0x00, true);
assert_eq!(new_data, 0xab);
}
-105
View File
@@ -1,105 +0,0 @@
/*
+---+---+---+---+---+---+
| 0 | 1 | 2 | 3 | 4 | 5 |
+---+---+---+---+---+---+
| 6 | 7 | 8 | 9 | A | B |
+---+---+---+---+---+---+
| C | D | E | F | AD| DA|
+---+---+---+---+---+---+
| + | PC| ST| RS| | |
+---+---+---+---+---+---+
*/
pub struct Kim1Keypad {
keys: [bool; 23],
stepping: bool
}
impl Kim1Keypad {
pub fn dump(&self) {
println!("Dumping state of keypad");
}
}
impl Kim1Keypad {
fn keyid(from: u8) -> usize{
(from % 23) as usize
}
pub fn new() -> Self {
Kim1Keypad {
keys: [false; 23],
stepping: false
}
}
pub fn toggle_stepping(&mut self) {
self.stepping = !self.stepping;;
}
pub fn set_stepping(&mut self, new_state: bool) {
self.stepping = new_state
}
pub fn press_key(&mut self, key_to_press: u8) {
self.keys[Self::keyid(key_to_press)] = true;
}
pub fn release_key(&mut self, key_to_release: u8) {
self.keys[Self::keyid(key_to_release)] = false;
}
pub fn is_pressed(&self, key: u8) -> bool {
self.keys[Self::keyid(key)]
}
}
#[cfg(test)]
mod test {
use super::*;
#[test]
fn smoke() { assert!(true); }
#[test]
fn keys_are_pressed() {
let mut kb = Kim1Keypad::new();
for index in 0..23 {
assert!(!kb.is_pressed(index));
kb.press_key(index);
assert!(kb.is_pressed(index));
kb.release_key(index);
assert!(!kb.is_pressed(index));
}
}
#[test]
fn stepping_changes() {
let mut kb = Kim1Keypad::new();
kb.set_stepping(false);
assert!(!kb.stepping);
kb.toggle_stepping();
assert!(kb.stepping);
kb.toggle_stepping();
kb.toggle_stepping();
kb.toggle_stepping();
kb.toggle_stepping();
kb.toggle_stepping();
assert!(!kb.stepping);
}
#[test]
fn out_of_range() {
let mut kb = Kim1Keypad::new();
kb.press_key(24);
assert!(kb.is_pressed(1));
}
}
+1 -4
View File
@@ -1,9 +1,6 @@
pub mod rom_chip;
pub mod at28c256;
pub mod hm62256;
pub mod ram_chip;
pub mod mos6522;
pub mod mos6530;
pub mod kim1_keypad;
mod bus_device;
pub mod backplane;
+1 -3
View File
@@ -1,4 +1,2 @@
pub mod mos6522;
mod registers;
mod new;
mod tick;
mod registers;
+101 -45
View File
@@ -5,49 +5,104 @@ use crate::constants::constants_via6522::*;
#[derive(Default)]
pub struct Mos6522 {
/// data direction
pub(crate) dda: u8,
pub(crate) ddb: u8,
dda: u8,
ddb: u8,
/// bottom 4 address bits
pub(crate) rs0: u8,
pub(crate) rs1: u8,
pub(crate) rs2: u8,
pub(crate) rs3: u8,
rs0: u8,
rs1: u8,
rs2: u8,
rs3: u8,
/// external data bus
pub(crate) data_bus: u8,
data_bus: u8,
pub(crate) cs1: bool,
pub(crate) cs2: bool,
// when true CPU is reading
pub(crate) rw: bool,
cs1: bool,
cs2: bool,
rw: bool,
/// reset circuit - true when reset inited
pub(crate) reset: bool,
reset: bool,
/// IRQ - true when interrupt waiting
pub(crate) irq: bool,
irq: bool,
pub(crate) ira: u8,
pub(crate) ora: u8,
pub(crate) porta: u8,
pub(crate) irb: u8,
pub(crate) orb: u8,
pub(crate) portb: u8,
ira: u8,
ora: u8,
porta: u8,
irb: u8,
orb: u8,
portb: u8,
pub(crate) ca1: bool,
pub(crate) ca2: bool,
pub(crate) cb1: bool,
pub(crate) cb2: bool,
// memory offset for where in the computers memory map this fits
pub(crate) offset: u16,
pub(crate) address_bus: u16,
ca1: bool,
ca2: bool,
cb1: bool,
cb2: bool,
}
impl Mos6522 {
pub fn max_offset(&self) -> u16 {
self.offset + 0x10
pub fn new() -> Self {
Mos6522::default()
}
/// tick
///
/// data_bus -> 8 bits from the data bus
/// control -> 4 bits to identify which register to control
pub fn tick(&mut self, data_bus: u8, control: u8, rw: bool) -> (u8) {
println!("Mos6522 Tick Start -> 0x{data_bus:02x} / 0x{control:02x} / {rw}");
if rw {
// RW true = CPU is writing
self.data_bus = data_bus;
match control {
VIA6522_DDRA => {
debug!("Setting DDA to 0x{data_bus:02x}");
// setting the Data Direction for Port A
self.dda = data_bus;
},
VIA6522_DDRB => {
debug!("Setting DDB to 0x{data_bus:02x}");
// setting the data direction for port b
self.ddb = data_bus;
},
VIA6522_ORB => {
// writing data to ORB
let masked_data = data_bus & self.ddb;
debug!("Setting ORB to 0x{data_bus:02x} / masked at 0x{masked_data:02x}");
self.portb = masked_data;
},
VIA6522_ORA => {
// writing data to ORA
let masked_data = data_bus & self.dda;
debug!("Setting ORA to 0x{data_bus:02x} / masked at 0x{masked_data:02x}");
self.porta = masked_data;
},
_ => {}
}
} else {
// RW false = CPU is reading
self.data_bus = match control {
VIA6522_DDRA => {
self.dda
}
VIA6522_DDRB => {
self.ddb
}
VIA6522_ORA => {
self.porta & self.dda
}
VIA6522_ORB => {
self.portb & self.ddb
}
_ => {
debug!("VIA got request for b{:08b} / 0x{:02x}", control, control);
// do nothing. bad address for VIA
self.data_bus
}
}
}
(self.data_bus)
}
pub fn start_clocks(&mut self) {
@@ -60,6 +115,7 @@ impl Mos6522 {
}
}
#[cfg(test)]
mod test {
use super::*;
@@ -70,40 +126,40 @@ mod test {
#[test]
fn registers() {
let mut x = Mos6522::new();
x.tick(VIA6522_DDRA as u16, 0b0000_0000, false, true);
x.tick(0b0000_0000, VIA6522_DDRA, true);
assert_eq!(x.dda, 0b0000_0000);
x.tick(VIA6522_DDRA as u16, 0b1111_1111, false, true);
x.tick(0b1111_1111, VIA6522_DDRA, true);
assert_eq!(x.dda, 0b1111_1111);
x.tick(VIA6522_DDRB as u16, 0b0000_0000, false, true);
x.tick(0b0000_0000, VIA6522_DDRB, true);
assert_eq!(x.ddb, 0b0000_0000);
x.tick(VIA6522_DDRB as u16, 0b1111_1111, false, true);
x.tick(0b1111_1111, VIA6522_DDRB, true);
assert_eq!(x.ddb, 0b1111_1111);
x.tick(VIA6522_ORA as u16, 0b0000_0000, false, true);
assert_eq!(x.ora, 0b0000_0000);
x.tick(VIA6522_ORA as u16, 0b1111_1111, false, true);
assert_eq!(x.ora, 0b1111_1111);
x.tick(0b0000_0000, VIA6522_ORA, true);
assert_eq!(x.porta, 0b0000_0000);
x.tick(0b1111_1111, VIA6522_ORA, true);
assert_eq!(x.porta, 0b1111_1111);
x.tick(VIA6522_ORB as u16, 0b0000_0000, false, true);
assert_eq!(x.orb, 0b0000_0000);
x.tick(VIA6522_ORB as u16, 0b1111_1111, false, true);
assert_eq!(x.orb, 0b1111_1111);
x.tick(0b0000_0000, VIA6522_ORB, true);
assert_eq!(x.portb, 0b0000_0000);
x.tick(0b1111_1111, VIA6522_ORB, true);
assert_eq!(x.portb, 0b1111_1111);
}
#[test]
fn partial_output_porta() {
let mut x = Mos6522::new();
x.tick(VIA6522_DDRA as u16, 0b1010_1010, false, true);
x.tick(VIA6522_ORA as u16,0b1111_1111, false, true);
x.tick(0b1010_1010, VIA6522_DDRA, true);
x.tick(0b1111_1111, VIA6522_ORA, true);
assert_eq!(x.porta, 0b1010_1010);
}
#[test]
fn partial_output_portb() {
let mut x = Mos6522::new();
x.tick(VIA6522_DDRB as u16, 0b0101_0101, false, true);
x.tick(VIA6522_ORB as u16, 0b1111_1111, false, true);
x.tick(0b0101_0101, VIA6522_DDRB, true);
x.tick(0b1111_1111, VIA6522_ORB, true);
assert_eq!(x.portb, 0b0101_0101);
}
}
-7
View File
@@ -1,7 +0,0 @@
use crate::periph::mos6522::mos6522::Mos6522;
impl Mos6522 {
pub fn new() -> Self {
Mos6522::default()
}
}
-89
View File
@@ -1,89 +0,0 @@
use log::debug;
use crate::constants::constants_system::SIZE_32KB;
use crate::constants::constants_via6522::{VIA6522_DDRA, VIA6522_DDRB, VIA6522_ORA, VIA6522_ORB};
use crate::periph::mos6522::mos6522::Mos6522;
impl Mos6522 {
fn max_address(&self) -> u16 {
self.offset + SIZE_32KB as u16
}
/// tick
///
/// data_bus -> 8 bits from the data bus
/// control -> 4 bits to identify which register to control
pub fn tick(&mut self, address_bus: u16, data_bus: u8,reset: bool, rw: bool) -> (u16, u8) {
if !(address_bus >= self.offset && address_bus.le(&self.max_address())) {
return (address_bus, data_bus);
}
let local_address = address_bus - self.offset;
println!("Mos6522 Tick Start -> D:0x{data_bus:02x} / A:0x{address_bus:02x} / {rw} (Actual 0x{local_address:02x} / 0b{local_address:08b})");
if reset {
// reset process
println!("Resetting Mos6522");
self.data_bus = data_bus;
self.dda = 0x00;
self.ddb = 0x00;
self.porta = 0x00;
self.portb = 0x00;
return (self.address_bus, self.data_bus)
}
if rw {
// RW true = CPU is writing
self.data_bus = data_bus;
match local_address as u8 {
VIA6522_DDRA => {
println!("Setting DDA to 0x{data_bus:02x}");
// setting the Data Direction for Port A
self.dda = data_bus;
},
VIA6522_ORB => {
// writing data to ORB
let masked_data = data_bus & self.ddb;
println!("Setting ORB to 0x{data_bus:02x} / masked at 0x{masked_data:02x}");
self.orb = data_bus;
self.portb = masked_data;
},
VIA6522_DDRB => {
println!("Setting DDB to 0x{data_bus:02x}");
// setting the data direction for port b
self.ddb = data_bus;
},
VIA6522_ORA => {
// writing data to ORA
let masked_data = data_bus & self.dda;
println!("Setting ORA to 0x{data_bus:02x} / masked at 0x{masked_data:02x}");
self.ora = data_bus;
self.porta = masked_data;
},
_ => {}
}
} else {
// RW false = CPU is reading
self.data_bus = match local_address as u8 {
VIA6522_DDRA => {
self.dda
}
VIA6522_DDRB => {
self.ddb
}
VIA6522_ORA => {
self.porta & self.dda
}
VIA6522_ORB => {
self.portb & self.ddb
}
_ => {
debug!("VIA got request for b{:08b} / 0x{:02x}", address_bus, address_bus);
// do nothing. bad address for VIA
self.data_bus
}
}
}
(self.address_bus, self.data_bus)
}
}
-11
View File
@@ -1,11 +0,0 @@
use crate::periph::mos6530::mos6530::Mos6530;
impl Mos6530 {
pub fn dump(&self) {
println!("Dumping state of Mos6530 RRIOT");
}
pub fn dump_data(&self) -> (u16, u16, u16) {
(self.io_offset, self.ram_offset, self.rom_offset)
}
}
-4
View File
@@ -1,4 +0,0 @@
pub mod mos6530;
pub mod tick;
mod new;
mod dump;
-31
View File
@@ -1,31 +0,0 @@
use crate::constants::constants_system::*;
use crate::periph::mos6522::mos6522::Mos6522;
/// Mos6530 RRIOT
/// Ram/Rom/IO/Timer
///
/// Represents a single Mos6530 RRIOT Chip
///
/// Used in the TIM-1, KIM-1
///
/// 1kb Rom
/// 64 bytes RAM
/// IO Ports (A, B)
/// Timer
pub struct Mos6530 {
pub(crate) data: [u8; SIZE_1KB],
pub(crate) ram: [u8; 64],
pub(crate) porta: u8,
pub(crate) portb: u8,
pub(crate) data_bus: u8,
pub(crate) address_bus: u16,
pub(crate) cs1: bool,
pub(crate) cs2: bool,
// when true, CPU is reading
pub(crate) rw: bool,
pub(crate) reset: bool,
pub(crate) io_offset: u16,
pub(crate) ram_offset: u16,
pub(crate) rom_offset: u16
}
-25
View File
@@ -1,25 +0,0 @@
use crate::constants::constants_system::SIZE_1KB;
use crate::periph::mos6530::mos6530::Mos6530;
impl Mos6530 {
pub fn new(io_offset: u16,
ram_offset: u16,
rom_offset: u16,
data: &[u8; SIZE_1KB]) -> Self {
Mos6530 {
data: *data,
ram: [0x00; 64],
porta: 0,
portb: 0,
data_bus: 0,
address_bus: 0,
cs1: false,
cs2: false,
rw: false,
reset: false,
io_offset,
ram_offset,
rom_offset
}
}
}
-26
View File
@@ -1,26 +0,0 @@
use log::debug;
use crate::periph::mos6530::mos6530::Mos6530;
impl Mos6530 {
pub fn tick(&mut self, address_bus: u16, data_bus: u8, reset: bool, rw: bool) {
debug!("Starting tick of MOS6530 RRIOT with 0x{address_bus:04x} / 0b{data_bus:08b} / R:{reset} / RW:{rw} (OFFSETS: I{:04x}, RA{:04x}, RO{:04x})", self.io_offset, self.ram_offset, self.rom_offset);
let io_max = self.io_offset + 0x3f;
let ram_max = self.ram_offset + 0x3f;
let rom_max = self.rom_offset + 0x400;
if address_bus.ge(&self.io_offset) && address_bus.le(&io_max) {
let effective = address_bus - self.io_offset;
println!("IO Activity at effective 0x{effective:02x}");
}
if address_bus.ge(&self.ram_offset) && address_bus.le(&ram_max) {
let effective = address_bus - self.ram_offset;
println!("RAM Activity at effective 0x{effective:02x}");
}
if address_bus.ge(&self.rom_offset) && address_bus.le(&rom_max) {
let effective = address_bus - self.rom_offset;
println!("Rom Activity at effective 0x{effective:02x}");
}
}
}
-8
View File
@@ -1,8 +0,0 @@
pub trait BusDevice {
fn address_bus(&self) -> u16;
fn data_bus(&self) -> u8;
fn set_address_bus(&mut self, new_value: u16);
fn set_data_bus(&mut self, new_value: u8);
}
-1
View File
@@ -1 +0,0 @@
pub mod bus_device;
+1 -3
View File
@@ -6,6 +6,4 @@ edition = "2024"
[dependencies]
macroquad.workspace = true
core = { path = "../core" }
egui_extras = "0.32"
egui = "0.27"
eframe = "0.27"
egui-macroquad = "0.17"
-88
View File
@@ -1,88 +0,0 @@
use eframe::egui;
use core::computers::rom_only::RomOnlyComputer;
struct MyApp {
address: String,
data: String,
cpu_read: bool,
computer: RomOnlyComputer
}
impl Default for MyApp {
fn default() -> Self {
let rom_data = vec![0x01, 0x02, 0x03, 0x04];
Self {
address: String::new(),
data: String::new(),
cpu_read: false,
computer: RomOnlyComputer::program(rom_data), // Example memory: 0x00 to 0xFF
}
}
}
impl eframe::App for MyApp {
fn update(&mut self, ctx: &egui::Context, _frame: &mut eframe::Frame) {
egui::CentralPanel::default().show(ctx, |ui| {
ui.heading("Memory Inspector");
ui.horizontal(|ui| {
ui.label("Address:");
ui.text_edit_singleline(&mut self.address);
});
ui.horizontal(|ui| {
ui.label("Data:");
ui.text_edit_singleline(&mut self.data);
});
ui.checkbox(&mut self.cpu_read, "CPU Read");
if ui.button("Tick").clicked() {
println!(
"Ticked with Address: {}, Data: {}, CPU Read: {}",
self.address, self.data, self.cpu_read
);
}
ui.horizontal(|ui| {
ui.label(format!("Address Bus ${:?}", self.address).as_str());
ui.label(format!("Data Bus ${:?}", self.data).as_str());
});
ui.separator();
ui.label("Memory View (Hex Dump):");
egui::ScrollArea::vertical().show(ui, |ui| {
let bytes_per_row = 16;
for (i, chunk) in self.computer.rom_chunks(bytes_per_row).enumerate() {
let address = i * bytes_per_row;
let hex_values: String = chunk
.iter()
.map(|b| format!("{:02X} ", b))
.collect();
let ascii_values: String = chunk
.iter()
.map(|b| {
if b.is_ascii_graphic() {
*b as char
} else {
'.'
}
})
.collect();
ui.monospace(format!("{:08X}: {:<48} {}", address, hex_values, ascii_values));
}
});
});
}
}
fn main() -> eframe::Result<()> {
let options = eframe::NativeOptions::default();
eframe::run_native(
"Memory Inspector",
options,
Box::new(|_cc| Box::new(MyApp::default())),
)
}
-3
View File
@@ -1,3 +0,0 @@
To Build
64tass -a -b -o <your_bin> <your_asm>
-26
View File
@@ -1,26 +0,0 @@
* = $A000
.fill Reset - *, $ea
Reset:
SEI
CLD
LDX #$FF
TXS
; Drop to the start of our main loop
MainLoop:
LDA #$AA
ROR
JMP MainLoop
; What to do when we get a NMI
NMI:
RTI
; What do we get when we get an interrupt
IRQ:
RTI
; setup the requirements for the CPU
* = $FFF8
.word NMI
.word Reset
.word IRQ
View File
-22
View File
@@ -1,22 +0,0 @@
* = $0000
.fill Reset - *, $ea
Reset:
SEI
CLD
LDX #$FF
TXS
MainLoop:
NOP
JMP MainLoop
NMI:
RTI
IRQ:
RTI
* = $FFF8
.word NMI
.word RESET
.word IRQ
Binary file not shown.
Binary file not shown.
-189
View File
@@ -1,189 +0,0 @@
; Test of instructions for the decompiler
;
; This file is intended to be assembled and then
; used as an input to a test that decompiles the
; binary back to the text version of the instructions
ADC #$ab ; ADC Immediate
ADC $ab ; ADC ZeroPage
ADC $ab,X ; ADC ZeroPageX
ADC $abcd ; ADC Absolute
ADC $abcd,X; ADC AbsoluteX
ADC $abcd,Y; ADC AbsoluteY
ADC ($ab,X); ADC IndirectX
ADC ($ab),Y; ADC IndirectY
AND #$ab ; AND Immediate
AND $ab ; AND ZeroPage
AND $ab,X ; AND ZeroPageX
AND $abcd ; AND Absolute
AND $abcd,X; AND AbsoluteX
AND $abcd,Y; AND AbsoluteY
AND ($ab,X); AND IndirectX
AND ($ab),Y; AND IndirectY
ASL ; ASL Accumulator
ASL $ab ; ASL ZeroPage
ASL $ab,X ; ASL ZeroPageX
ASL $abcd ; ASL Absolute
ASL $abcd,X; ASL AbsoluteX
BCC $71 ; BCC Immediate
BCS $71 ; BCS Immediate
BEQ $71 ; BEQ Immediate
BIT $ab ; BIT ZeroPage
BIT $abcd ; BIT Absolute
BMI $7b ; BMI Immediate
BNE $7b ; BNI Immediate
BPL $7b ; BPL Immediate
BRK ; BRK
BVC $ab ; BVC Immediate
BVS $ab ; BVS Immediate
CLC ; CLC
CLD ; CLD
CLI ; CLI
CLV ; CLV
CMP #$ab ; CMP Immediate
CMP $ab ; CMP ZeroPage
CMP $ab,X ; CMP ZeroPageX
CMP $abcd ; CMP Absolute
CMP $abcd,X; CMP AbsoluteX
CMP $abcd,Y; CMP AbsoluteY
CMP ($ab,X); CMP IndirectX
CMP ($ab),Y; CMP IndirectY
CPX #$ab ; CPX Immediate
CPX $ab ; CPX ZeroPage
CPX $abcd ; CPX Absolute
CPY #$ab ; CPY Immediate
CPY $ab ; CPY ZeroPage
CPY $abcd ; CPY Absolute
DEC $ab ; DEC ZeroPage
DEC $ab,X ; DEC ZeroPageX
DEC $abcd ; DEC Absolute
DEC $abcd,X; DEC AbsoluteX
DEX ; DEX
DEY ; DEY
EOR #$ab ; EOR Immediate
EOR $ab ; EOR ZeroPage
EOR $ab,X ; EOR ZeroPageX
EOR $abcd ; EOR Absolute
EOR $abcd,X; EOR AbsoluteX
EOR $abcd,Y; EOR AbsoluteY
EOR ($ab,X); EOR IndirectX
EOR ($ab),Y; EOR IndirectY
INC $ab ; INC ZeroPage
INC $ab,X ; INC ZeroPage,X
INC $abcd ; INC Absolute
INC $abcd,X; INC AbsoluteX
INX ; INX
INY ; INY
JMP $abcd ; JMP Absolute
JMP ($abcd); JMP Indirect
JSR $abcd ; JSR Absolute
LDA #$ab ; LDA Immediate
LDA $ab ; LDA ZeroPage
LDA $ab,X ; LDA ZeroPageX
LDA $abcd ; LDA Absolute
LDA $abcd,X; LDA AbsoluteX
LDA $abcd,Y; LDA AbsoluteY
LDA ($ab,X); LDA IndirectX
LDA ($ab),Y; LDA IndirectY
LDX #$ab ; LDX Immediate
LDX $ab ; LDX ZeroPage
LDX $ab,Y ; LDX ZeroPageY
LDX $abcd ; LDX Absolute
LDX $abcd,Y; LDX AbsoluteY
LDY #$ab ; LDY Immediate
LDY $ab ; LDY ZeroPage
LDY $ab,X ; LDY ZeroPageX
LDY $abcd ; LDY Absolute
LDY $abcd,X; LDY AbsoluteX
LSR ; LSR Accumulator
LSR $ab ; LSR ZeroPage
LSR $ab,X ; LSR ZeroPageX
LSR $abcd ; LSR Absolute
LSR $abcd,X; LSR AbsoluteX
NOP ; The great and powerful NOP
ORA #$ab ; ORA Immediate
ORA $ab ; ORA ZeroPage
ORA $ab,X ; ORA ZeroPageX
ORA $abcd ; ORA Absolute
ORA $abcd,X; ORA AbsoluteX
ORA $abcd,Y; ORA AbsoluteY
ORA ($ab,X); ORA IndirectX
ORA ($ab),Y; ORA IndirectY
PHA ; PHA
PHP ; PHP
PLA ; PLA
PLP ; PLP
ROL ; ROL Accumulator
ROL $ab ; ROL ZeroPage
ROL $ab,X ; ROL ZeroPageX
ROL $abcd ; ROL Absolute
ROL $abcd,X; ROL AbsoluteX
ROR ; ROR Accumulator
ROR $ab ; ROR ZeroPage
ROR $ab,X ; ROR ZeroPageX
ROR $abcd ; ROR Absolute
ROR $abcd,X; ROR AbsoluteX
RTI ; Interrupt Return
RTS ; Subroutine Return
SBC #$ab ; SBC Immediate
SBC $ab ; SBC ZeroPage
SBC $ab,X ; SBC ZeroPageX
SBC $abcd ; SBC Absolute
SBC $abcd,X; SBC AbsoluteX
SBC ($ab,X); SBC IndirectX
SBC ($ab),Y; SBC IndirectY
SEC ; SEC
SED ; SED
SEI ; SEI
STA $ab ; STA ZeroPage
STA $ab,X ; STA ZeroPageX
STA $abcd ; STA Absolute
STA $abcd,X; STA AbsoluteX
STA $abcd,Y; STA AbsoluteY
STA ($ab,X); STA IndirectX
STA ($ab),Y; STA IndirectY
STX $ab ; STX ZeroPage
STX $ab,Y ; STX ZeroPageY
STX $abcd ; STX Absolute
STY $ab ; STY ZeroPage
STY $ab,X ; STY ZeroPageX
STY $abcd ; STY Absolute
TAX ; TAX
TAY ; TAY
TSX ; TSX
TXA ; TXA
TXS ; TXS
TYA ; TYA
-8
View File
@@ -1,8 +0,0 @@
* = $4000
.fill start - *, $00
start:
LDA #$ab
ROR
LDX #$ba
TXA
JMP start
Binary file not shown.