Initial commit
Start of the project
This commit is contained in:
commit
533b519d15
1
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[[package]]
|
||||
name = "wasi"
|
||||
version = "0.14.2+wasi-0.2.4"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "9683f9a5a998d873c0d21fcbe3c083009670149a8fab228644b8bd36b2c48cb3"
|
||||
dependencies = [
|
||||
"wit-bindgen-rt",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "winapi-util"
|
||||
version = "0.1.9"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "cf221c93e13a30d793f7645a0e7762c55d169dbb0a49671918a2319d289b10bb"
|
||||
dependencies = [
|
||||
"windows-sys",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "windows-sys"
|
||||
version = "0.59.0"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "1e38bc4d79ed67fd075bcc251a1c39b32a1776bbe92e5bef1f0bf1f8c531853b"
|
||||
dependencies = [
|
||||
"windows-targets",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "windows-targets"
|
||||
version = "0.52.6"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "9b724f72796e036ab90c1021d4780d4d3d648aca59e491e6b98e725b84e99973"
|
||||
dependencies = [
|
||||
"windows_aarch64_gnullvm",
|
||||
"windows_aarch64_msvc",
|
||||
"windows_i686_gnu",
|
||||
"windows_i686_gnullvm",
|
||||
"windows_i686_msvc",
|
||||
"windows_x86_64_gnu",
|
||||
"windows_x86_64_gnullvm",
|
||||
"windows_x86_64_msvc",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "windows_aarch64_gnullvm"
|
||||
version = "0.52.6"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "32a4622180e7a0ec044bb555404c800bc9fd9ec262ec147edd5989ccd0c02cd3"
|
||||
|
||||
[[package]]
|
||||
name = "windows_aarch64_msvc"
|
||||
version = "0.52.6"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "09ec2a7bb152e2252b53fa7803150007879548bc709c039df7627cabbd05d469"
|
||||
|
||||
[[package]]
|
||||
name = "windows_i686_gnu"
|
||||
version = "0.52.6"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "8e9b5ad5ab802e97eb8e295ac6720e509ee4c243f69d781394014ebfe8bbfa0b"
|
||||
|
||||
[[package]]
|
||||
name = "windows_i686_gnullvm"
|
||||
version = "0.52.6"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "0eee52d38c090b3caa76c563b86c3a4bd71ef1a819287c19d586d7334ae8ed66"
|
||||
|
||||
[[package]]
|
||||
name = "windows_i686_msvc"
|
||||
version = "0.52.6"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "240948bc05c5e7c6dabba28bf89d89ffce3e303022809e73deaefe4f6ec56c66"
|
||||
|
||||
[[package]]
|
||||
name = "windows_x86_64_gnu"
|
||||
version = "0.52.6"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "147a5c80aabfbf0c7d901cb5895d1de30ef2907eb21fbbab29ca94c5b08b1a78"
|
||||
|
||||
[[package]]
|
||||
name = "windows_x86_64_gnullvm"
|
||||
version = "0.52.6"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "24d5b23dc417412679681396f2b49f3de8c1473deb516bd34410872eff51ed0d"
|
||||
|
||||
[[package]]
|
||||
name = "windows_x86_64_msvc"
|
||||
version = "0.52.6"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "589f6da84c646204747d1270a2a5661ea66ed1cced2631d546fdfb155959f9ec"
|
||||
|
||||
[[package]]
|
||||
name = "wit-bindgen-rt"
|
||||
version = "0.39.0"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "6f42320e61fe2cfd34354ecb597f86f413484a798ba44a8ca1165c58d42da6c1"
|
||||
dependencies = [
|
||||
"bitflags",
|
||||
]
|
||||
10
Cargo.toml
Normal file
10
Cargo.toml
Normal file
@ -0,0 +1,10 @@
|
||||
[package]
|
||||
name = "slu4_cpu"
|
||||
version = "0.1.0"
|
||||
edition = "2024"
|
||||
|
||||
[dependencies]
|
||||
trevors_utilities = { path = "/home/tmerritt/Projects/trevors_utilities" }
|
||||
|
||||
pretty_env_logger = { version = "0.5" }
|
||||
log = { version = "0.4" }
|
||||
69
src/adder.rs
Normal file
69
src/adder.rs
Normal file
@ -0,0 +1,69 @@
|
||||
use log::debug;
|
||||
use crate::busses::{AddressBus, DataBus};
|
||||
use crate::control_signals::ControlSignals;
|
||||
use crate::cycle_stages::CycleStages;
|
||||
|
||||
#[derive(Default)]
|
||||
pub struct AdderFlags {
|
||||
negative: bool,
|
||||
carry: bool,
|
||||
zero: bool
|
||||
}
|
||||
|
||||
#[derive(Default)]
|
||||
pub struct Adder {
|
||||
a_value: u8,
|
||||
b_value: u8,
|
||||
y_value: u8,
|
||||
flags_value: AdderFlags
|
||||
}
|
||||
|
||||
impl Adder {
|
||||
pub fn set_flags(&mut self, new_flags: AdderFlags) {
|
||||
self.flags_value = new_flags;
|
||||
}
|
||||
pub fn set_a(&mut self, new_value: u8) {
|
||||
self.a_value = new_value;
|
||||
}
|
||||
|
||||
pub fn set_b(&mut self, new_value: u8) {
|
||||
self.b_value = new_value;
|
||||
}
|
||||
|
||||
pub fn get_y(&self) -> u8 {
|
||||
self.y_value
|
||||
}
|
||||
|
||||
pub fn get_flags(&self) -> AdderFlags {
|
||||
AdderFlags::default()
|
||||
}
|
||||
}
|
||||
|
||||
impl CycleStages for Adder {
|
||||
fn falling_edge(address_bus: AddressBus, data_bus: DataBus, state: ControlSignals) {
|
||||
todo!()
|
||||
}
|
||||
|
||||
fn low_state(address_bus: AddressBus, data_bus: DataBus, state: ControlSignals) {
|
||||
todo!()
|
||||
}
|
||||
|
||||
fn rising_edge(address_bus: AddressBus, data_bus: DataBus, state: ControlSignals) {
|
||||
todo!()
|
||||
}
|
||||
|
||||
fn high_state(address_bus: AddressBus, data_bus: DataBus, state: ControlSignals) {
|
||||
todo!()
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(Test)]
|
||||
mod test {
|
||||
use super::*;
|
||||
|
||||
#[test]
|
||||
fn add_two_numbers() {
|
||||
let adder = Adder::new();
|
||||
|
||||
}
|
||||
}
|
||||
38
src/busses.rs
Normal file
38
src/busses.rs
Normal file
@ -0,0 +1,38 @@
|
||||
use log::trace;
|
||||
|
||||
pub struct AddressBus {
|
||||
value: u16
|
||||
}
|
||||
|
||||
impl AddressBus {
|
||||
pub fn new() -> Self {
|
||||
AddressBus { value : 0x0000 }
|
||||
}
|
||||
|
||||
pub fn set_address(&mut self, new_address: u16) {
|
||||
trace!("Address bus updated from {} to {}", self.value, new_address);
|
||||
self.value = new_address
|
||||
}
|
||||
|
||||
pub fn address(&self) -> u16 {
|
||||
self.value
|
||||
}
|
||||
}
|
||||
|
||||
pub struct DataBus {
|
||||
value: u8
|
||||
}
|
||||
|
||||
impl DataBus {
|
||||
pub fn new() -> Self {
|
||||
DataBus { value: 0x00 }
|
||||
}
|
||||
|
||||
pub fn set_data(&mut self, new_value: u8) {
|
||||
self.value = new_value;
|
||||
}
|
||||
|
||||
pub fn data(&self) -> u8 {
|
||||
self.value
|
||||
}
|
||||
}
|
||||
52
src/computer.rs
Normal file
52
src/computer.rs
Normal file
@ -0,0 +1,52 @@
|
||||
use std::time::{Duration, Instant};
|
||||
use log::debug;
|
||||
use crate::adder::Adder;
|
||||
use crate::memory::Memory;
|
||||
use crate::register::Register;
|
||||
|
||||
pub struct Computer {
|
||||
last_updated: Instant,
|
||||
current_input: String,
|
||||
adder: Adder,
|
||||
register: Register,
|
||||
memory: Memory
|
||||
|
||||
}
|
||||
|
||||
impl Computer {
|
||||
pub fn new() -> Self {
|
||||
debug!("Created new CPU");
|
||||
Computer {
|
||||
last_updated: Instant::now(),
|
||||
current_input: String::from(""),
|
||||
adder: Adder::default(),
|
||||
register: Register::default(),
|
||||
memory: Memory::default()
|
||||
}
|
||||
}
|
||||
|
||||
pub fn reset(mut self) {
|
||||
self = Computer::new();
|
||||
}
|
||||
|
||||
pub fn update(&mut self) {
|
||||
let now = Instant::now();
|
||||
if now.duration_since(self.last_updated).as_millis() > 10 {
|
||||
debug!("Time to update cpu.");
|
||||
self.last_updated = now;
|
||||
|
||||
// Rising Edge
|
||||
|
||||
// High State
|
||||
|
||||
// Falling Edge
|
||||
|
||||
// Low State
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
pub fn input(&mut self, c: char) {
|
||||
self.current_input = format!("{}{}", self.current_input, c);
|
||||
}
|
||||
}
|
||||
1
src/constants.rs
Normal file
1
src/constants.rs
Normal file
@ -0,0 +1 @@
|
||||
pub const SIZE_32KB: usize = 1024*1024*32;
|
||||
56
src/control_signals.rs
Normal file
56
src/control_signals.rs
Normal file
@ -0,0 +1,56 @@
|
||||
use std::collections::BTreeMap;
|
||||
|
||||
pub enum ControlSignal {
|
||||
// UART Transmitter Register In
|
||||
TI,
|
||||
// UART Receiver Register Out
|
||||
TO,
|
||||
// UART Receiver Register Clear,
|
||||
TC,
|
||||
// Memory Address Register In (LSB)
|
||||
MIL,
|
||||
// Memory Address Register In (MSB)
|
||||
MIH,
|
||||
// Memory Address Register Increment
|
||||
ME,
|
||||
// Bank Register In
|
||||
KI,
|
||||
// RAM In
|
||||
RI,
|
||||
// RAM Out
|
||||
RO,
|
||||
// Program Counter In (LSB)
|
||||
CIL,
|
||||
// Program Counter In (MSB)
|
||||
CIH,
|
||||
// Program Counter Out (LSB)
|
||||
COL,
|
||||
// Program Counter Out (MSB),
|
||||
COH,
|
||||
// Program Counter Increment
|
||||
CI,
|
||||
// A Register In
|
||||
AI,
|
||||
// A Register Out
|
||||
AO,
|
||||
// B Register In
|
||||
BI,
|
||||
// B Register Out
|
||||
BO,
|
||||
// Adder Sum Out
|
||||
EO,
|
||||
// Adder Invert Operand B
|
||||
ES,
|
||||
// Adder Carry In
|
||||
EC,
|
||||
// Flags REgister IN
|
||||
FI,
|
||||
// Instruction Register In
|
||||
II,
|
||||
// Step Counter Clear
|
||||
IC
|
||||
}
|
||||
|
||||
pub struct ControlSignals {
|
||||
pub signals: BTreeMap<ControlSignal, bool>
|
||||
}
|
||||
28
src/cycle_stages.rs
Normal file
28
src/cycle_stages.rs
Normal file
@ -0,0 +1,28 @@
|
||||
use crate::busses::{AddressBus, DataBus};
|
||||
use crate::control_signals::ControlSignals;
|
||||
|
||||
/// Cycle Stages
|
||||
///
|
||||
/// The 4 stages of a clock cycle
|
||||
pub trait CycleStages {
|
||||
|
||||
/// Falling Edge
|
||||
///
|
||||
/// When the clock pulse is moving from high to low
|
||||
fn falling_edge(address_bus: AddressBus, data_bus: DataBus, state: ControlSignals);
|
||||
|
||||
/// Low State
|
||||
///
|
||||
/// Clock pulse is stabilized at the low level
|
||||
fn low_state(address_bus: AddressBus, data_bus: DataBus, state: ControlSignals);
|
||||
|
||||
/// Rising Edge
|
||||
///
|
||||
/// When the clock pulse is moving from low to high
|
||||
fn rising_edge(address_bus: AddressBus, data_bus: DataBus, state: ControlSignals);
|
||||
|
||||
/// High State
|
||||
///
|
||||
/// Clock pulse is stabilized at the high level
|
||||
fn high_state(address_bus: AddressBus, data_bus: DataBus, state: ControlSignals);
|
||||
}
|
||||
24
src/main.rs
Normal file
24
src/main.rs
Normal file
@ -0,0 +1,24 @@
|
||||
use crate::computer::Computer;
|
||||
|
||||
mod cycle_stages;
|
||||
mod computer;
|
||||
mod register;
|
||||
mod adder;
|
||||
mod memory;
|
||||
mod busses;
|
||||
mod constants;
|
||||
mod control_signals;
|
||||
|
||||
fn main() {
|
||||
pretty_env_logger::init();
|
||||
|
||||
let mut cpu = Computer::new();
|
||||
|
||||
let mut keep_running = true;
|
||||
|
||||
while keep_running {
|
||||
cpu.update();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
48
src/memory.rs
Normal file
48
src/memory.rs
Normal file
@ -0,0 +1,48 @@
|
||||
use log::debug;
|
||||
use crate::busses::{AddressBus, DataBus};
|
||||
use crate::constants::SIZE_32KB;
|
||||
use crate::control_signals::ControlSignals;
|
||||
use crate::cycle_stages::CycleStages;
|
||||
|
||||
pub struct Memory {
|
||||
data: [u8; SIZE_32KB]
|
||||
}
|
||||
|
||||
impl Memory {
|
||||
pub fn peek(&self, offset: u16) -> u8 { self.data[offset as usize] }
|
||||
pub fn poke(&mut self, new_value: u8, offset: u16) { self.data[offset as usize] = new_value; }
|
||||
|
||||
pub fn clear(&mut self) {
|
||||
for i in 0..SIZE_32KB {
|
||||
self.poke(0x00, i as u16);
|
||||
}
|
||||
}
|
||||
|
||||
pub fn new() -> Self {
|
||||
Memory { data: [0; SIZE_32KB] }
|
||||
}
|
||||
}
|
||||
|
||||
impl Default for Memory {
|
||||
fn default() -> Self {
|
||||
Memory::new()
|
||||
}
|
||||
}
|
||||
|
||||
impl CycleStages for Memory {
|
||||
fn falling_edge(address_bus: AddressBus, data_bus: DataBus, state: ControlSignals) {
|
||||
todo!()
|
||||
}
|
||||
|
||||
fn low_state(address_bus: AddressBus, data_bus: DataBus, state: ControlSignals) {
|
||||
todo!()
|
||||
}
|
||||
|
||||
fn rising_edge(address_bus: AddressBus, data_bus: DataBus, state: ControlSignals) {
|
||||
todo!()
|
||||
}
|
||||
|
||||
fn high_state(address_bus: AddressBus, data_bus: DataBus, state: ControlSignals) {
|
||||
todo!()
|
||||
}
|
||||
}
|
||||
46
src/register.rs
Normal file
46
src/register.rs
Normal file
@ -0,0 +1,46 @@
|
||||
use log::debug;
|
||||
use crate::busses::{AddressBus, DataBus};
|
||||
use crate::control_signals::ControlSignals;
|
||||
use crate::cycle_stages::CycleStages;
|
||||
|
||||
#[derive(Default)]
|
||||
pub struct Register {
|
||||
value: u16,
|
||||
in_mask: u16,
|
||||
out_mask: u16,
|
||||
count_mask: u16,
|
||||
hi_mask: u16,
|
||||
port_lines: u8,
|
||||
control_lines: u16,
|
||||
name: String
|
||||
}
|
||||
|
||||
impl Register {
|
||||
pub fn new(name: String) -> Self {
|
||||
let mut working= Register::default();
|
||||
working.name = name;
|
||||
working
|
||||
}
|
||||
|
||||
pub fn reset(&mut self) -> Self {
|
||||
Register::new(self.name.clone())
|
||||
}
|
||||
}
|
||||
|
||||
impl CycleStages for Register {
|
||||
fn falling_edge(address_bus: AddressBus, data_bus: DataBus, state: ControlSignals) {
|
||||
todo!()
|
||||
}
|
||||
|
||||
fn low_state(address_bus: AddressBus, data_bus: DataBus, state: ControlSignals) {
|
||||
todo!()
|
||||
}
|
||||
|
||||
fn rising_edge(address_bus: AddressBus, data_bus: DataBus, state: ControlSignals) {
|
||||
todo!()
|
||||
}
|
||||
|
||||
fn high_state(address_bus: AddressBus, data_bus: DataBus, state: ControlSignals) {
|
||||
todo!()
|
||||
}
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user